 Development of an extended version of this architecture commenced in 2006 and resulted in the XAP5, which was announced in July 2008.XAP5 is a 16-bit processor with a 24-bit address bus making it capable of running programs from memory up to 16 MBytes.XAP4 and XAP5 are both implemented with a two-stage instruction pipeline, which maximises their performance when clocked at low frequencies.