 The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect.The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by in size.The VAX 9000's CPU was coupled with a vector processor with a maximum theoretical performance of 125 MFLOPS.