 The KA64A contained a 35.71 MHz (28 ns cycle time) Rigel chip set with an external 128 KB B-cache (L2 cache).The B-cache was direct-mapped and used a 64-byte cache line size with a 16-byte sub-block size.It was constructed from twenty-four 64 KB (4-bit by 16,384-word) 15 ns SRAMs.