 The system was based around a crossbar switch in the system control unit (SCU), to which the one to four CPUs, two memory controllers, two input/output (I/O) controllers and a service processor connected.I/O was provided by four Extended Memory Interconnect (XMI) buses.Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic.