 The cores (renamed "S3" from "VT") included a dual-issue 16 stage integer pipeline, and 11-cycle floating point pipeline, both giving improvements over the previous ("S2") core used in the SPARC T3 processor.Each core has associated 16 KB data and 16 KB instruction L1 caches, and a unified 128 KB L2 Cache.All eight cores share 4 MB L3 cache, and the total transistor count is approximately 855 million.