 To manufacture such a device layers of conducting polysilicon and silicon dioxide dielectric are deposited first on top of a silicon substrate that contains standard CMOS logic elements.A trench is then etched and its walls are deposited first with silicon dioxide (blue), then silicon nitride (yellow), then another silicon dioxide (blue) layer, forming the gate dielectric, the charge trap, and the tunnel dielectric in that order.Finally the hole is filled with conducting polysilicon (red) which forms the channel.