 It was believed in 2006 that the existing floating gate cap structure could not be manufactured at processes smaller than the 50 nm node due to difficulties in producing the complex three-layer ONO gate oxide that these devices require.Samsung even announced in late 2006 that by 2008 it would put such a device into production at the 40 nm process node, but over the five years following this announcement many device designers found ways to push the cap structure to increasingly tighter process geometries, successfully producing NAND down to 20 nm node with this approach.The charge trapping approach is still viewed as a future for NAND flash for processes smaller than 20 nm and is being considered for both planar as well as vertical 3D structures.