 The new latching clock region would be completely independent from the other four clocking zones illustrated in figure 9.For instance, if the value of interest to the new latching region were to be the value that D presents every 16th phase, the clocking mechanism of the new region would have to be configured to latch a value in the 4th phase and every 16th phase from then on, thus, ignoring all inputs but D.

Adding a second serial line to the device, and adding another latching region would allow for the latching of two input values at the two different outputs.To perform computation, a gate that takes as inputs both serial lines at their respective outputs is added.