 Development efforts into multigate transistors have been reported by the Electrotechnical Laboratory, Toshiba, Grenoble INP, Hitachi, IBM, TSMC, UC Berkeley, Infineon Technologies, Intel, AMD, Samsung Electronics, KAIST, Freescale Semiconductor, and others, and the ITRS predicted correctly that such devices will be the cornerstone of sub-32 nm technologies.The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning.Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-κ/metal gate materials.