 It used newer 20,000-gate CMOS and 10,000-gate emitter-coupled logic (ECL) gate arrays for a boost in clock speed from 10 MHz to 25 MHz, and rated at 50 MFLOPS peak for double precision per CPU (100 MFLOPS peak for single precision).It was Convex's most successful product.The C2 was followed by the C3 in 1991, being essentially similar to the C2 but with a faster clock and support for up to eight CPUs implemented with low-density GaAs FPGAs.