 IC Compiler by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure.When the user requires the circuit to meet exceptionally difficult timing constraints, it may be necessary to utilize machine learning programs to find an optimum set of FPGA synthesis, map, place and route tool configuration parameters that ensures the circuit will close timing.A timing requirement needs to be translated into a static timing constraint for an EDA tool to be able to handle it.