 It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer.This technique is used in DRAM cells and is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.Since 32 nm node, Intel has applied the above-mentioned self-aligned via approach, which allows two vias separated by a small enough pitch (112.5 nm for Intel 32 nm metal) to be patterned with one resist opening instead of two separate ones.