 Most FPGAs are based on SRAM configuration cells and require an external configuration device, often a serial flash chip, to reload the configuration bitstream every power cycle.With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to.Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns.