 When operating in native mode, the 65C802/65C816 provide separate vectors for and .When set, the interrupt request disable flag (the bit in the status register) will disable detection of the signal, but will have no effect on any other interrupts (however, see below section on the instruction implemented in WDC CMOS processors).Additionally, with the 65(c)02 or the 65C816/65C802 operating in emulation mode, the copy of the status register that is pushed on to the stack will have the flag set if a (software interrupt) was the cause of the interrupt, or cleared if an was the cause.