 If these timing constraints are not observed, the abort interrupt handler itself may be aborted, causing registers and/or memory to be changed in a possibly-undefined manner.In the NMOS 6502 and derivatives (e.g., 6510), the simultaneous assertion of a hardware interrupt line and execution of was not accounted for in the design—the instruction will be ignored in such a case.Also, the status of the decimal mode flag in the processor status register is unchanged following an interrupt of any kind.