title: Muon

text: Due to their greater mass, muons accelerate more slowly than electrons in electromagnetic fields, and emit less bremsstrahlung (deceleration radiation). This allows muons of a given energy to penetrate far deeper into matter because the deceleration of electrons and muons is primarily due to energy loss by the bremsstrahlung mechanism. For example, so-called "secondary muons", created by cosmic rays hitting the atmosphere, can penetrate the atmosphere and reach Earth's land surface and even into deep mines.


title: Muon

text: Because muons have a greater mass and energy than the decay energy of radioactivity, they are not produced by radioactive decay. However they are produced in great amounts in high-energy interactions in normal matter, in certain particle accelerator experiments with hadrons, and in cosmic ray interactions with matter. These interactions usually produce pi mesons initially, which almost always decay to muons.


title: Muon

text: As with the other charged leptons, the muon has an associated muon neutrino, denoted by , which differs from the electron neutrino and participates in different nuclear reactions.


title: Muon

text: Muons were discovered by Carl D. Anderson and Seth Neddermeyer at Caltech in 1936, while studying cosmic radiation. Anderson noticed particles that curved differently from electrons and other known particles when passed through a magnetic field. They were negatively charged but curved less sharply than electrons, but more sharply than protons, for particles of the same velocity. It was assumed that the magnitude of their negative electric charge was equal to that of the electron, and so to account for the difference in curvature, it was supposed that their mass was greater than an electron but smaller than a proton. Thus Anderson initially called the new particle a "mesotron", adopting the prefix "meso-" from the Greek word for "mid-". The existence of the muon was confirmed in 1937 by J. C. Street and E. C. Stevenson's cloud chamber experiment.


title: Muon

text: A particle with a mass in the meson range had been predicted before the discovery of any mesons, by theorist Hideki Yukawa:


title: Muon

text: It seems natural to modify the theory of Heisenberg and Fermi in the following way. The transition of a heavy particle from neutron state to proton state is not always accompanied by the emission of light particles. The transition is sometimes taken up by another heavy particle.


title: Muon

text: Because of its mass, the mu meson was initially thought to be Yukawa's particle and some scientists, including Niels Bohr, originally named it the yukon. Yukawa's predicted particle, the pi meson, was finally identified in 1947 (again from cosmic ray interactions), and was shown to differ from the mu meson by having the properties of a particle that mediated the nuclear force.


title: Muon

text: With two particles now known with the intermediate mass, the more general term "meson" was adopted to refer to any such particle within the correct mass range between electrons and nucleons. Further, in order to differentiate between the two different types of mesons after the second meson was discovered, the initial mesotron particle was renamed the "mu meson" (the Greek letter "μ" ["mu"] corresponds to "m"), and the new 1947 meson (Yukawa's particle) was named the pi meson.


title: Muon

text: As more types of mesons were discovered in accelerator experiments later, it was eventually found that the mu meson significantly differed not only from the pi meson (of about the same mass), but also from all other types of mesons. The difference, in part, was that mu mesons did not interact with the nuclear force, as pi mesons did (and were required to do, in Yukawa's theory). Newer mesons also showed evidence of behaving like the pi meson in nuclear interactions, but not like the mu meson. Also, the mu meson's decay products included both a neutrino and an antineutrino, rather than just one or the other, as was observed in the decay of other charged mesons.


title: Muon

text: In the eventual Standard Model of particle physics codified in the 1970s, all mesons other than the mu meson were understood to be hadrons – that is, particles made of quarks – and thus subject to the nuclear force. In the quark model, a "meson" was no longer defined by mass (for some had been discovered that were very massive – more than nucleons), but instead were particles composed of exactly two quarks (a quark and antiquark), unlike the baryons, which are defined as particles composed of three quarks (protons and neutrons were the lightest baryons). Mu mesons, however, had shown themselves to be fundamental particles (leptons) like electrons, with no quark structure. Thus, mu "mesons" were not mesons at all, in the new sense and use of the term "meson" used with the quark model of particle structure.


title: Muon

text: With this change in definition, the term "mu meson" was abandoned, and replaced whenever possible with the modern term "muon", making the term "mu meson" only a historical footnote. In the new quark model, other types of mesons sometimes continued to be referred to in shorter terminology (e.g., "pion" for pi meson), but in the case of the muon, it retained the shorter name and was never again properly referred to by older "mu meson" terminology.


title: Muon

text: The eventual recognition of the muon as a simple "heavy electron", with no role at all in the nuclear interaction, seemed so incongruous and surprising at the time, that Nobel laureate I. I. Rabi famously quipped, "Who ordered that?"


title: Muon

text: In the Rossi–Hall experiment (1941), muons were used to observe the time dilation (or, alternatively, length contraction) predicted by special relativity, for the first time.


title: Muon

text: Muons arriving on the Earth's surface are created indirectly as decay products of collisions of cosmic rays with particles of the Earth's atmosphere.


title: Muon

text: When a cosmic ray proton impacts atomic nuclei in the upper atmosphere, pions are created. These decay within a relatively short distance (meters) into muons (their preferred decay product), and muon neutrinos. The muons from these high-energy cosmic rays generally continue in about the same direction as the original proton, at a velocity near the speed of light. Although their lifetime "without" relativistic effects would allow a half-survival distance of only about 456 meters at most (as seen from Earth) the time dilation effect of special relativity (from the viewpoint of the Earth) allows cosmic ray secondary muons to survive the flight to the Earth's surface, since in the Earth frame the muons have a longer half-life due to their velocity. From the viewpoint (inertial frame) of the muon, on the other hand, it is the length contraction effect of special relativity which allows this penetration, since in the muon frame its lifetime is unaffected, but the length contraction causes distances through the atmosphere and Earth to be far shorter than these distances in the Earth rest-frame. Both effects are equally valid ways of explaining the fast muon's unusual survival over distances.


title: Muon

text: Since muons are unusually penetrative of ordinary matter, like neutrinos, they are also detectable deep underground (700 meters at the Soudan 2 detector) and underwater, where they form a major part of the natural background ionizing radiation. Like cosmic rays, as noted, this secondary muon radiation is also directional.


title: Muon

text: The same nuclear reaction described above (i.e. hadron-hadron impacts to produce pion beams, which then quickly decay to muon beams over short distances) is used by particle physicists to produce muon beams, such as the beam used for the muon "g"−2 experiment.


title: Muon

text: Muons are unstable elementary particles and are heavier than electrons and neutrinos but lighter than all other matter particles. They decay via the weak interaction. Because leptonic family numbers are conserved in the absence of an extremely unlikely immediate neutrino oscillation, one of the product neutrinos of muon decay must be a muon-type neutrino and the other an electron-type antineutrino (antimuon decay produces the corresponding antiparticles, as detailed below).


title: Muon

text: Because charge must be conserved, one of the products of muon decay is always an electron of the same charge as the muon (a positron if it is a positive muon). Thus all muons decay to at least an electron, and two neutrinos. Sometimes, besides these necessary products, additional other particles that have no net charge and spin of zero (e.g., a pair of photons, or an electron-positron pair), are produced.


title: Muon

text: The dominant muon decay mode (sometimes called the Michel decay after Louis Michel) is the simplest possible: the muon decays to an electron, an electron antineutrino, and a muon neutrino. Antimuons, in mirror fashion, most often decay to the corresponding antiparticles: a positron, an electron neutrino, and a muon antineutrino. In formulaic terms, these two decays are:


title: Muon

text: The mean lifetime, , of the (positive) muon is . The equality of the muon and antimuon lifetimes has been established to better than one part in 10.


title: Muon

text: Certain neutrino-less decay modes are kinematically allowed but are, for all practical purposes, forbidden in the Standard Model, even given that neutrinos have mass and oscillate. Examples forbidden by lepton flavour conservation are:


title: Muon

text: To be precise: in the Standard Model with neutrino mass, a decay like → + is technically possible, for example by neutrino oscillation of a virtual muon neutrino into an electron neutrino, but such a decay is astronomically unlikely and therefore should be experimentally unobservable: Less than one in 10 muon decays should produce such a decay.


title: Muon

text: Observation of such decay modes would constitute clear evidence for theories beyond the Standard Model. Upper limits for the branching fractions of such decay modes were measured in many experiments starting more than years ago. The current upper limit for the → + branching fraction was measured 2009–2013 in the MEG experiment and is .


title: Muon

text: The muon decay width which follows from Fermi's golden rule has dimension of energy, and must be proportional to the square of the amplitude, and thus the square of Fermi's coupling constant (formula_1), with over-all dimension of inverse fourth power of energy. By dimensional analysis, this leads to Sargent's rule of fifth-power dependence on ,


title: Muon

text: The decay distributions of the electron in muon decays have been parameterised using the so-called Michel parameters. The values of these four parameters are predicted unambiguously in the Standard Model of particle physics, thus muon decays represent a good test of the spacetime structure of the weak interaction. No deviation from the Standard Model predictions has yet been found.


title: Muon

text: For the decay of the muon, the expected decay distribution for the Standard Model values of Michel parameters is


title: Muon

text: where formula_6 is the angle between the muon's polarization vector formula_7 and the decay-electron momentum vector, and formula_8 is the fraction of muons that are forward-polarized. Integrating this expression over electron energy gives the angular distribution of the daughter electrons:


title: Muon

text: Because the direction the electron is emitted in (a polar vector) is preferentially aligned opposite the muon spin (an axial vector), the decay is an example of non-conservation of parity by the weak interaction. This is essentially the same experimental signature as used by the original demonstration. More generally in the Standard Model, all charged leptons decay via the weak interaction and likewise violate parity symmetry.


title: Muon

text: "Negative" muons can form muonic atoms (previously called mu-mesic atoms), by replacing an electron in ordinary atoms. Muonic hydrogen atoms are much smaller than typical hydrogen atoms because the much larger mass of the muon gives it a much more localized ground-state wavefunction than is observed for the electron. In multi-electron atoms, when only one of the electrons is replaced by a muon, the size of the atom continues to be determined by the other electrons, and the atomic size is nearly unchanged. However, in such cases the orbital of the muon continues to be smaller and far closer to the nucleus than the atomic orbitals of the electrons.


title: Muon

text: Spectroscopic measurements in muonic hydrogen have been to used to produce a precise estimate of the proton radius. The results of these measurements diverged from the then accepted value giving rise to the so called proton radius puzzle. Later this puzzle found its resolution when new improved measurements of the proton radius in the electronic hydrogen became available.


title: Muon

text: Muonic helium is created by substituting a muon for one of the electrons in helium-4. The muon orbits much closer to the nucleus, so muonic helium can therefore be regarded like an isotope of helium whose nucleus consists of two neutrons, two protons and a muon, with a single electron outside. Colloquially, it could be called "helium 4.1", since the mass of the muon is slightly greater than 0.1 dalton. Chemically, muonic helium, possessing an unpaired valence electron, can bond with other atoms, and behaves more like a hydrogen atom than an inert helium atom.


title: Muon

text: Muonic heavy hydrogen atoms with a negative muon may undergo nuclear fusion in the process of muon-catalyzed fusion, after the muon may leave the new atom to induce fusion in another hydrogen molecule. This process continues until the negative muon is captured by a helium nucleus, where it remains until it decays.


title: Muon

text: Negative muons bound to conventional atoms can be captured (muon capture) through the weak force by protons in nuclei, in a sort of electron-capture-like process. When this happens, nuclear transmutation results: The proton becomes a neutron and a muon neutrino is emitted.


title: Muon

text: A "positive" muon, when stopped in ordinary matter, cannot be captured by a proton since the two positive charges can only repel. The positive muon is also not attracted to the nucleus of atoms. Instead, it binds a random electron and with this electron forms an exotic atom known as muonium (mu) atom. In this atom, the muon acts as the nucleus. The positive muon, in this context, can be considered a pseudo-isotope of hydrogen with one ninth of the mass of the proton. Because the mass of the electron is much smaller than the mass of both the proton and the muon, the reduced mass of muonium, and hence its Bohr radius, is very close to that of hydrogen. Therefore this bound muon-electron pair can be treated to a first approximation as a short-lived "atom" that behaves chemically like the isotopes of hydrogen (protium, deuterium and tritium).


title: Muon

text: Both positive and negative muons can be part of a short-lived pi-mu atom consisting of a muon and an oppositely charged pion. These atoms were observed in the 1970s in experiments at Brookhaven and Fermilab.


title: Muon

text: The anomalous magnetic dipole moment is the difference between the experimentally observed value of the magnetic dipole moment and the theoretical value predicted by the Dirac equation. The measurement and prediction of this value is very important in the precision tests of QED. The E821 experiment at Brookhaven National Laboratory (BNL) and the Muon g-2 experiment at Fermilab studied the precession of the muon spin in a constant external magnetic field as the muons circulated in a confining storage ring. The Muon g-2 collaboration reported in 2021:


title: Muon

text: The difference between the "g"-factors of the muon and the electron is due to their difference in mass. Because of the muon's larger mass, contributions to the theoretical calculation of its anomalous magnetic dipole moment from Standard Model weak interactions and from contributions involving hadrons are important at the current level of precision, whereas these effects are not important for the electron. The muon's anomalous magnetic dipole moment is also sensitive to contributions from new physics beyond the Standard Model, such as supersymmetry. For this reason, the muon's anomalous magnetic moment is normally used as a probe for new physics beyond the Standard Model rather than as a test of QED. Muon "g"−2, a new experiment at Fermilab using the E821 magnet improved the precision of this measurement.


title: Muon

text: In 2020 an international team of 170 physicists calculated the most accurate prediction for the theoretical value of the muon's anomalous magnetic moment.


title: Muon

text: In 2021, the Fermilab National Accelerator Laboratory (FNAL) Muon g−2 Experiment presented their first results of a new experimental average which increased the difference between experiment and theory to 4.2 standard deviations.


title: Muon

text: The current experimental limit on the muon electric dipole moment, |"d"| < 1.9 × 10 e·cm set by the E821 experiment at the Brookhaven Laboratory, is orders of magnitude above the Standard Model prediction. The observation of a non-zero muon electric dipole moment would provide an additional source of CP violation. An improvement in sensitivity by two orders of magnitude over the Brookhaven limit is expected from the experiments at Fermilab.


title: Muon

text: Since muons are much more deeply penetrating than X-rays or gamma rays, muon imaging can be used with much thicker material or, with cosmic ray sources, larger objects. One example is commercial muon tomography used to image entire cargo containers to detect shielded nuclear material, as well as explosives or other contraband.


title: Muon

text: The technique of muon transmission radiography based on cosmic ray sources was first used in the 1950s to measure the depth of the overburden of a tunnel in Australia and in the 1960s to search for possible hidden chambers in the Pyramid of Chephren in Giza. In 2017, the discovery of a large void (with a length of 30 metres minimum) by observation of cosmic-ray muons was reported.


title: Muon

text: In 2003, the scientists at Los Alamos National Laboratory developed a new imaging technique: "muon scattering tomography". With muon scattering tomography, both incoming and outgoing trajectories for each particle are reconstructed, such as with sealed aluminum drift tubes. Since the development of this technique, several companies have started to use it.


title: Muon

text: In August 2014, Decision Sciences International Corporation announced it had been awarded a contract by Toshiba for use of its muon tracking detectors in reclaiming the Fukushima nuclear complex. The Fukushima Daiichi Tracker (FDT) was proposed to make a few months of muon measurements to show the distribution of the reactor cores. In December 2014, Tepco reported that they would be using two different muon imaging techniques at Fukushima, "muon scanning method" on Unit 1 (the most badly damaged, where the fuel may have left the reactor vessel) and "muon scattering method" on Unit 2. The International Research Institute for Nuclear Decommissioning IRID in Japan and the High Energy Accelerator Research Organization KEK call the method they developed for Unit 1 the "muon permeation method"; 1,200 optical fibers for wavelength conversion light up when muons come into contact with them. After a month of data collection, it is hoped to reveal the location and amount of fuel debris still inside the reactor. The measurements began in February 2015.


title: David Paulides

text: David Paulides is a former police officer who is now an investigator and writer known primarily for his self-published books dedicated to proving the reality of Bigfoot, and establishing the "Missing 411" conspiracy theory. "Missing 411" is a series of books and films, which document cases of people who have gone missing in national parks and elsewhere, and maintain that these cases are unusual and mysterious, contrary to data analysis which suggests that they are not actually statistically mysterious or even unexpected.


title: David Paulides

text: In his online biography page, Paulides states that he received his undergraduate and graduate degrees from the University of San Francisco, and in 1977 he began a 20-year career in law enforcement, transferring in 1980 to the San Jose Police Department, working in the patrol division on the SWAT Team, patrol, and Street Crimes Unit, and a variety of assignments in the detective division. While working as a court liaison officer in December 1996, Paulides was charged with a misdemeanor count of falsely soliciting for a charity.


title: David Paulides

text: After leaving the police force, Paulides wrote books on the topic of Bigfoot, as well as on the disappearances of people in national parks and elsewhere which he attributes to unspecified, unknown causes.


title: David Paulides

text: In his pursuit of Bigfoot, Paulides self-published two Bigfoot-related books and founded the research group North America Bigfoot Search, for which he serves as director.


title: David Paulides

text: Paulides has said North America Bigfoot Search was instrumental in the genesis of a paper published in 2013, which claimed that Bigfoot was real: "The world needs to understand that North America Bigfoot Search was the organizer of the study. We orchestrated the search that led to picking Dr. Ketchum to conduct a study of bigfoot DNA." The resulting paper documented the analysis of 111 samples of hypothesized Bigfoot DNA and was written by 11 different authors. On November 24, 2012, DNA Diagnostics, a veterinary laboratory headed by Ketchum, issued a press release prior to peer review claiming that their DNA sequencing study confirmed the existence of a hominin hybrid cross between modern humans with an unknown primate. Two months later, in the inaugural issue of "DeNovo: Journal of Science", the paper was analyzed by Sharon Hill of Doubtful News for the Committee for Skeptical Inquiry. Hill's report concluded that the paper was of poor quality, stating that "The few experienced geneticists who viewed the paper reported a dismal opinion of it, noting it made little sense."


title: David Paulides

text: "The Scientist" magazine also analyzed the paper, reporting that the analyses and data fail to support the claims of existence of a human-primate hybrid, but rather, "analyses either come back as 100 percent human, or fail in ways that suggest technical artifacts." The website for the DeNovo Journal of Science was set up on February 4, and there is no indication that Ketchum's work, the only study it has published, was peer reviewed.


title: David Paulides

text: Following his work on Bigfoot, Paulides' next project was "Missing 411", a series of self-published books and two documentary films, documenting unsolved cases of people who have gone missing in national parks and elsewhere.


title: David Paulides

text: According to Paulides, his work on this subject began when he was doing research in a national park and an off-duty park ranger found him and expressed concern about the questionable nature of some of the missing person cases which occurred in the parks. The ranger knew Paulides' background and asked him to research the issue. Paulides obliged, and asserts that he uncovered multiple lines of evidence suggesting negligence on the part of the park service in failing to locate the missing people. He broadened his investigation to include missing people from across the world, and this led to his belief that he has uncovered a mysterious series of worldwide disappearances, which he said defied logical and conventional explanations.


title: David Paulides

text: Paulides' books publicized the fact that the US National Park Service does not keep an independent list of people that go missing in their parks. While there is a database for incident and criminal reports, it is not widely or consistently used and it doesn't interface with other criminal databases. In response, a petition was created to make the department accountable.


title: David Paulides

text: The interest in the book series prompted the creation of a documentary film based on the "Missing 411" books; this film was released in 2017. Images of maps made by Paulides regarding his theory have been frequently shared on social media. The theory has also gone viral on TikTok.


title: David Paulides

text: Kyle Polich, a data scientist and host of the "Data Skeptic" podcast, documented his analysis of Paulides' claims in the article "Missing411" and presented his analysis to a SkeptiCamp held in 2017 by the Monterey County Skeptics. He concluded that the allegedly unusual disappearances represent nothing unusual at all, and are instead best explained by non-mysterious causes such as falling or sudden health crises leading to a lone person becoming immobilized off-trail, drowning, bear (or other animal) attack, environmental exposure, or even deliberate disappearance. After analyzing the missing person data, Polich concluded that these cases are not "outside the frequency that one would expect, or that there is anything unexplainable that I was able to identify." This presentation was discussed in a February 2017 article in "Skeptical Inquirer", a publication of the CSI. In the article, Susan Gerbic reported "Paulides... gave no reason for these disappearances but finds odd correlations for them. For example, two women missing in different years both had names starting with an 'A' with three-letters, Amy and Ann." Polich concluded in his analysis: "I've exhausted my exploration for anything genuinely unusual. After careful review, to me, not a single case stands out nor do the frequencies involved seem outside of expectations."


title: Computing

text: Computing is any goal-oriented activity requiring, benefiting from, or creating computing machinery. It includes the study and experimentation of algorithmic processes, and development of both hardware and software. Computing has scientific, engineering, mathematical, technological and social aspects. Major computing disciplines include computer engineering, computer science, cybersecurity, data science, information systems, information technology and software engineering.


title: Computing

text: The term "computing" is also synonymous with counting and calculating. In earlier times, it was used in reference to the action performed by mechanical computing machines, and before that, to human computers.


title: Computing

text: The history of computing is longer than the history of computing hardware and includes the history of methods intended for pen and paper (or for chalk and slate) with or without the aid of tables. Computing is intimately tied to the representation of numbers, though mathematical concepts necessary for computing existed before numeral systems. The earliest known tool for use in computation is the abacus, and it is thought to have been invented in Babylon circa between 2700–2300 BC. Abaci, of a more modern design, are still used as calculation tools today.


title: Computing

text: The first recorded proposal for using digital electronics in computing was the 1931 paper "The Use of Thyratrons for High Speed Automatic Counting of Physical Phenomena" by C. E. Wynn-Williams. Claude Shannon's 1938 paper "A Symbolic Analysis of Relay and Switching Circuits" then introduced the idea of using electronics for Boolean algebraic operations.


title: Computing

text: The concept of a field-effect transistor was proposed by Julius Edgar Lilienfeld in 1925. John Bardeen and Walter Brattain, while working under William Shockley at Bell Labs, built the first working transistor, the point-contact transistor, in 1947. In 1953, the University of Manchester built the first transistorized computer, the Manchester Baby. However, early junction transistors were relatively bulky devices that were difficult to mass-produce, which limited them to a number of specialised applications. The metal–oxide–silicon field-effect transistor (MOSFET, or MOS transistor) was invented by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959. The MOSFET made it possible to build high-density integrated circuits, leading to what is known as the computer revolution or microcomputer revolution.


title: Computing

text: A computer is a machine that manipulates data according to a set of instructions called a computer program. The program has an executable form that the computer can use directly to execute the instructions. The same program in its human-readable source code form, enables a programmer to study and develop a sequence of steps known as an algorithm. Because the instructions can be carried out in different types of computers, a single set of source instructions converts to machine instructions according to the CPU type.


title: Computing

text: The execution process carries out the instructions in a computer program. Instructions express the computations performed by the computer. They trigger sequences of simple actions on the executing machine. Those actions produce effects according to the semantics of the instructions.


title: Computing

text: Computer hardware includes the physical parts of a computer, including central processing unit, memory and input/output. Computational logic and computer architecture are key topics in the field of computer hardware.


title: Computing

text: Computer software, or just "software", is a collection of computer programs and related data, which provides instructions to a computer. Software refers to one or more computer programs and data held in the storage of the computer. It is a set of "programs, procedures, algorithms," as well as its "documentation" concerned with the operation of a data processing system. Program software performs the function of the program it implements, either by directly providing instructions to the computer hardware or by serving as input to another piece of software. The term was coined to contrast with the old term "hardware" (meaning physical devices). In contrast to hardware, software is intangible.


title: Computing

text: System software, or systems software, is computer software designed to operate and control computer hardware, and to provide a platform for running application software. System software includes operating systems, utility software, device drivers, window systems, and firmware. Frequently used development tools such as compilers, linkers, and debuggers are classified as system software. System software and middleware manage and integrate a computer's capabilities, but typically do not directly apply them in the performance of tasks that benefit the user, unlike application software.


title: Computing

text: Application software, also known as an "application" or an "app", is computer software designed to help the user perform specific tasks. Examples include enterprise software, accounting software, office suites, graphics software and media players. Many application programs deal principally with documents. Apps may be bundled with the computer and its system software, or may be published separately. Some users are satisfied with the bundled apps and need never install additional applications. The system software manages the hardware and serves the application, which in turn serves the user.


title: Computing

text: Application software applies the power of a particular computing platform or system software to a particular purpose. Some apps, such as Microsoft Office, are developed in multiple versions for several different platforms; others have narrower requirements and are generally referred to by the platform they run on. For example, a "geography application for Windows" or an "Android application for education" or "Linux gaming". Applications that run only on one platform and increase the desirability of that platform due to the popularity of the application, known as killer applications.


title: Computing

text: A computer network, often simply referred to as a network, is a collection of hardware components and computers interconnected by communication channels that allow sharing of resources and information. When at least one process in one device is able to send or receive data to or from at least one process residing in a remote device, the two devices are said to be in a network. Networks may be classified according to a wide variety of characteristics such as the medium used to transport the data, communications protocol used, scale, topology, and organizational scope.


title: Computing

text: Communications protocols define the rules and data formats for exchanging information in a computer network, and provide the basis for network programming. One well-known communications protocol is Ethernet, a hardware and link layer standard that is ubiquitous in local area networks. Another common protocol is the Internet Protocol Suite, which defines a set of protocols for internetworking, i.e. for data communication between multiple networks, host-to-host data transfer, and application-specific data transmission formats.


title: Computing

text: Computer networking is sometimes considered a sub-discipline of electrical engineering, telecommunications, computer science, information technology or computer engineering, since it relies upon the theoretical and practical application of these disciplines.


title: Computing

text: The Internet is a global system of interconnected computer networks that use the standard Internet Protocol Suite (TCP/IP) to serve billions of users. This includes millions of private, public, academic, business, and government networks, ranging in scope from local to global. These networks are linked by a broad array of electronic, wireless and optical networking technologies. The Internet carries an extensive range of information resources and services, such as the inter-linked hypertext documents of the World Wide Web and the infrastructure to support email.


title: Computing

text: Computer programming is the process of writing, testing, debugging, and maintaining the source code and documentation of computer programs. This source code is written in a programming language, which is an artificial language that is often more restrictive than natural languages, but easily translated by the computer. Programming is used to invoke some desired behavior (customization) from the machine.


title: Computing

text: Writing high quality source code requires knowledge of both the computer science domain and the domain in which the application will be used. The highest-quality software is thus often developed by a team of domain experts, each a specialist in some area of development. However, the term "programmer" may apply to a range of program quality, from hacker to open source contributor to professional. It is also possible for a single programmer to do most or all of the computer programming needed to generate the proof of concept to launch a new "killer" application.


title: Computing

text: A programmer, computer programmer, or coder is a person who writes computer software. The term "computer programmer" can refer to a specialist in one area of computer programming or to a generalist who writes code for many kinds of software. One who practices or professes a formal approach to programming may also be known as a programmer analyst. A programmer's primary computer language (C, C++, Java, Lisp, Python etc.) is often prefixed to the above titles, and those who work in a web environment often prefix their titles with "Web". The term "programmer" can be used to refer to a software developer, software engineer, computer scientist, or software analyst. However, members of these professions typically possess other software engineering skills, beyond programming.


title: Computing

text: The computer industry is made up of businesses involved in developing computer software, designing computer hardware and computer networking infrastructures, manufacturing computer components and providing information technology services, including system administration and maintenance.


title: Computing

text: The software industry includes businesses engaged in development, maintenance and publication of software. The industry also includes software services, such as training, documentation, and consulting.


title: Computing

text: Computer engineering is a discipline that integrates several fields of electrical engineering and computer science required to develop computer hardware and software. Computer engineers usually have training in electronic engineering (or electrical engineering), software design, and hardware-software integration, rather than just software engineering or electronic engineering. Computer engineers are involved in many hardware and software aspects of computing, from the design of individual microprocessors, personal computers, and supercomputers, to circuit design. This field of engineering includes not only the design of hardware within its own domain, but also the interactions between hardware and the context in which it operates.


title: Computing

text: Software engineering (SE) is the application of a systematic, disciplined and quantifiable approach to the design, development, operation, and maintenance of software, and the study of these approaches. That is, the application of engineering to software. It is the act of using insights to conceive, model and scale a solution to a problem. The first reference to the term is the 1968 NATO Software Engineering Conference, and was intended to provoke thought regarding the perceived "software crisis" at the time. Software development, a widely-used and more generic term, does not necessarily subsume the engineering paradigm. The generally accepted concepts of Software Engineering as an engineering discipline have been specified in the Guide to the Software Engineering Body of Knowledge (SWEBOK). The SWEBOK has become an internationally accepted standard in ISO/IEC TR 19759:2015.


title: Computing

text: Computer science or computing science (abbreviated CS or Comp Sci) is the scientific and practical approach to computation and its applications. A computer scientist specializes in the theory of computation and the design of computational systems.


title: Computing

text: Its subfields can be divided into practical techniques for its implementation and application in computer systems, and purely theoretical areas. Some, such as computational complexity theory, which studies fundamental properties of computational problems, are highly abstract, while others, such as computer graphics, emphasize real-world applications. Others focus on the challenges in implementing computations. For example, programming language theory studies approaches to description of computations, while the study of computer programming investigates the use of programming languages and complex systems. The field of human–computer interaction focuses on the challenges in making computers and computations useful, usable, and universally accessible to humans.


title: Computing

text: The field of cybersecurity pertains to the protection of computer systems and networks. This includes information and data privacy, preventing disruption of IT services and prevention of theft of and damage to hardware, software and data.


title: Computing

text: Data science is a field that uses scientific and computing tools to extract information and insights from data, driven by the increasing volume and availability of data. Data mining, big data, statistics and machine learning are all interwoven with data science.


title: Computing

text: Information systems (IS) is the study of complementary networks of hardware and software (see information technology) that people and organizations use to collect, filter, process, create, and distribute data. The ACM's "Computing Careers" describes IS as:


title: Computing

text: The study of IS bridges business and computer science, using the theoretical foundations of information and computation to study various business models and related algorithmic processes within a computer science discipline. The field of Computer Information Systems (CIS) studies computers and algorithmic processes, including their principles, their software and hardware designs, their applications, and their impact on society while IS emphasizes functionality over design.


title: Computing

text: Information technology (IT) is the application of computers and telecommunications equipment to store, retrieve, transmit and manipulate data, often in the context of a business or other enterprise. The term is commonly used as a synonym for computers and computer networks, but also encompasses other information distribution technologies such as television and telephones. Several industries are associated with information technology, including computer hardware, software, electronics, semiconductors, internet, telecom equipment, e-commerce and computer services.


title: Computing

text: DNA-based computing and quantum computing are areas of active research for both computing hardware and software, such as the development of quantum algorithms. Potential infrastructure for future technologies includes DNA origami on photolithography and quantum antennae for transferring information between ion traps. By 2011, researchers had entangled 14 qubits. Fast digital circuits, including those based on Josephson junctions and rapid single flux quantum technology, are becoming more nearly realizable with the discovery of nanoscale superconductors.


title: Computing

text: Fiber-optic and photonic (optical) devices, which already have been used to transport data over long distances, are starting to be used by data centers, along with CPU and semiconductor memory components. This allows the separation of RAM from CPU by optical interconnects. IBM has created an integrated circuit with both electronic and optical information processing in one chip. This is denoted "CMOS-integrated nanophotonics" or (CINP). One benefit of optical interconnects is that motherboards, which formerly required a certain kind of system on a chip (SoC), can now move formerly dedicated memory and network controllers off the motherboards, spreading the controllers out onto the rack. This allows standardization of backplane interconnects and motherboards for multiple types of SoCs, which allows more timely upgrades of CPUs.


title: Computing

text: Another field of research is spintronics. Spintronics can provide computing power and storage, without heat buildup. Some research is being done on hybrid chips, which combine photonics and spintronics. There is also research ongoing on combining plasmonics, photonics, and electronics.


title: Computing

text: Cloud computing is a model that allows for the use of computing resources, such as servers or applications, without the need for interaction between the owner of these resources and the end user. It is typically offered as a service, making it an example of Software as a Service, Platforms as a Service, and Infrastructure as a Service, depending on the functionality offered. Key characteristics include on-demand access, broad network access, and the capability of rapid scaling. It allows individual users or small business to benefit from economies of scale.


title: Computing

text: One area of interest in this field is its potential to support energy efficiency. Allowing thousands of instances of computation to occur on one single machine instead of thousands of individual machines could help save energy. It could also ease the transition to renewable energy source, since it would suffice to power one server farm with renewable energy, rather than millions of homes and offices.


title: Computing

text: However, this centralized computing model poses several challenges, especially in security and privacy. Current legislation does not sufficiently protect users from companies mishandling their data on company servers. This suggests potential for further legislative regulations on cloud computing and tech companies.


title: Computing

text: Quantum computing is an area of research that brings together the disciplines of computer science, information theory, and quantum physics. While the idea of information as part of physics is relatively new, there appears to be a strong tie between information theory and quantum mechanics. Whereas traditional computing operates on a binary system of ones and zeros, quantum computing uses qubits. Qubits are capable of being in a superposition, i.e. in both states of one and zero, simultaneously. Thus, the value of the qubit is not between 1 and 0, but changes depending on when it is measured. This trait of qubits is known as quantum entanglement, and is the core idea of quantum computing that allows quantum computers to do large scale computations. Quantum computing is often used for scientific research in cases where traditional computers do not have the computing power to do the necessary calculations, such in molecular modeling. Large molecules and their reactions are far too complex for traditional computers to calculate, but the computational power of quantum computers could provide a tool to perform such calculations.


title: Dynamic random-access memory

text: Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors gradually leaks away; without intervention the data on the capacitor would soon be lost. To prevent this, DRAM requires an external "memory refresh" circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.


title: Dynamic random-access memory

text: DRAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in digital electronics where low-cost and high-capacity computer memory is required. One of the largest applications for DRAM is the "main memory" (colloquially called the "RAM") in modern computers and graphics cards (where the "main memory" is called the "graphics memory"). It is also used in many portable devices and video game consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.


title: Dynamic random-access memory

text: The need to refresh DRAM demands more complicated circuitry and timing than SRAM. This is offset by the structural simplicity of DRAM memory cells: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities with a simultaneous reduction in cost per bit. Refreshing the data consumes power and a variety of techniques are used to manage the overall power consumption.


title: Dynamic random-access memory

text: DRAM had a 47% increase in the price-per-bit in 2017, the largest jump in 30 years since the 45% jump in 1988, while in recent years the price has been going down. In 2018, a "key characteristic of the DRAM market is that there are currently only three major suppliers — Micron Technology, SK Hynix and Samsung Electronics" that are "keeping a pretty tight rein on their capacity.” There is also Kioxia (previously Toshiba Memory Corporation after 2017 spin-off). Other manufactures make and sell DIMMs (but not the DRAM chips in them), such as Kingston Technology, and some manufacturers that sell stacked DRAM (used e.g in the fastest exascale supercomputers), separately such as Viking Technology. Others sell such integrated into other products, such as Fujitsu into its CPUs, AMD in GPUs, and Nvidia, with HBM2 in some of their GPU chips.


title: Dynamic random-access memory

text: The cryptanalytic machine code-named ""Aquarius"" used at Bletchley Park during World War II incorporated a hard-wired dynamic memory. Paper tape was read and the characters on it "were remembered in a dynamic store. ... The store used a large bank of capacitors, which were either charged or not, a charged capacitor representing cross (1) and an uncharged capacitor dot (0). Since the charge gradually leaked away, a periodic pulse was applied to top up those still charged (hence the term 'dynamic')".


title: Dynamic random-access memory

text: In 1964, Arnold Farber and Eugene Schlig, working for IBM, created a hard-wired memory cell, using a transistor gate and tunnel diode latch. They replaced the latch with two transistors and two resistors, a configuration that became known as the Farber-Schlig cell. That year they submitted an invention closure, but it was initially rejected. In 1965, Benjamin Agusta and his team at IBM created a 16-bit silicon memory chip based on the Farber-Schlig cell, with 80 transistors, 64 resistors, and 4 diodes. The Toshiba ""Toscal" BC-1411" electronic calculator, which was introduced in November 1965, used a form of capacitive DRAM (180 bit) built from discrete bipolar memory cells.


title: Dynamic random-access memory

text: The earliest forms of DRAM mentioned above used bipolar transistors. While it offered improved performance over magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory. Capacitors had also been used for earlier memory schemes, such as the drum of the Atanasoff–Berry Computer, the Williams tube and the Selectron tube.


title: Dynamic random-access memory

text: In 1966, Dr. Robert Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory and was trying to create an alternative to SRAM which required six MOS transistors for each bit of data. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of the single-transistor MOS DRAM memory cell. He filed a patent in 1967, and was granted U.S. patent number 3,387,286 in 1968. MOS memory offered higher performance, was cheaper, and consumed less power, than magnetic-core memory.


title: Dynamic random-access memory

text: MOS DRAM chips were commercialized in 1969 by Advanced Memory Systems, Inc of Sunnyvale, CA. This 1024 bit chip was sold to Honeywell, Raytheon, Wang Laboratories, and others.


title: Dynamic random-access memory

text: The same year, Honeywell asked Intel to make a DRAM using a three-transistor cell that they had developed. This became the Intel 1102 in early 1970. However, the 1102 had many problems, prompting Intel to begin work on their own improved design, in secrecy to avoid conflict with Honeywell. This became the first commercially available DRAM, the Intel 1103, in October 1970, despite initial problems with low yield until the fifth revision of the masks. The 1103 was designed by Joel Karp and laid out by Pat Earhart. The masks were cut by Barbara Maness and Judy Garcia. MOS memory overtook magnetic-core memory as the dominant memory technology in the early 1970s.


title: Dynamic random-access memory

text: The first DRAM with multiplexed row and column address lines was the Mostek MK4096 4 Kbit DRAM designed by Robert Proebsting and introduced in 1973. This addressing scheme uses the same address pins to receive the low half and the high half of the address of the memory cell being referenced, switching between the two halves on alternating bus cycles. This was a radical advance, effectively halving the number of address lines required, which enabled it to fit into packages with fewer pins, a cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK4116 DRAM, introduced in 1976, achieved greater than 75% worldwide DRAM market share. However, as density increased to 64 Kbit in the early 1980s, Mostek and other US manufacturers were overtaken by Japanese DRAM manufacturers, which dominated the US and worldwide markets during the 1980s and 1990s.


title: Dynamic random-access memory

text: In 1985, when 64K DRAM memory chips were the most common memory chips used in computers, and when more than 60 percent of those chips were produced by Japanese companies, semiconductor makers in the United States accused Japanese companies of export dumping for the purpose of driving makers in the United States out of the commodity memory chip business. Prices for the 64K product plummeted to as low as 35 cents apiece from $3.50 within 18 months, with disastrous financial consequences for some U.S. firms. On 4 December 1985 the US Commerce Department’s International Trade Administration ruled in favor of the complaint.


title: Dynamic random-access memory

text: Synchronous dynamic random-access memory (SDRAM) was developed by Samsung. The first commercial SDRAM chip was the Samsung KM48SL2000, which had a capacity of 16Mb, and was introduced in 1992. The first commercial DDR SDRAM (double data rate SDRAM) memory chip was Samsung's 64Mb DDR SDRAM chip, released in 1998.


title: Dynamic random-access memory

text: DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit. The figure to the right shows a simple example with a four-by-four cell matrix. Some DRAM matrices are many thousands of cells in height and width.


title: Dynamic random-access memory

text: The long horizontal lines connecting each row are known as word-lines. Each column of cells is composed of two bit-lines, each connected to every other storage cell in the column (the illustration to the right does not include this important detail). They are generally known as the "+" and "−" bit lines.


title: Dynamic random-access memory

text: A sense amplifier is essentially a pair of cross-connected inverters between the bit-lines. The first inverter is connected with input from the + bit-line and output to the − bit-line. The second inverter's input is from the − bit-line with output to the + bit-line. This results in positive feedback which stabilizes after one bit-line is fully at its highest voltage and the other bit-line is at the lowest possible voltage.


title: Dynamic random-access memory

text: To store data, a row is opened and a given column's sense amplifier is temporarily forced to the desired high or low voltage state, thus causing the bit-line to charge or discharge the cell storage capacitor to the desired value. Due to the sense amplifier's positive feedback configuration, it will hold a bit-line at stable voltage even after the forcing voltage is removed. During a write to a particular cell, all the columns in a row are sensed simultaneously just as during reading, so although only a single column's storage-cell capacitor charge is changed, the entire row is refreshed (written back in), as illustrated in the figure to the right.


title: Dynamic random-access memory

text: Typically, manufacturers specify that each row must be refreshed every 64 ms or less, as defined by the JEDEC standard.


title: Dynamic random-access memory

text: Some systems refresh every row in a burst of activity involving all rows every 64 ms. Other systems refresh one row at a time staggered throughout the 64 ms interval. For example, a system with 2 = 8,192 rows would require a staggered refresh rate of one row every 7.8 µs which is 64 ms divided by 8,192 rows. A few real-time systems refresh a portion of memory at a time determined by an external timer function that governs the operation of the rest of a system, such as the vertical blanking interval that occurs every 10–20 ms in video equipment.


title: Dynamic random-access memory

text: The row address of the row that will be refreshed next is maintained by external logic or a counter within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct the DRAM to refresh or to provide a row address.


title: Dynamic random-access memory

text: Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.


title: Dynamic random-access memory

text: Many parameters are required to fully describe the timing of DRAM operation. Here are some examples for two timing grades of asynchronous DRAM, from a data sheet published in 1998:


title: Dynamic random-access memory

text: Thus, the generally quoted number is the minimum /RAS low time. This is the time to open a row, allowing the sense amplifiers to settle. Note that the data access for a bit in the row is shorter, since that happens as soon as the sense amplifier has settled, but the DRAM requires additional time to propagate the amplified data back to recharge the cells. The time to read additional bits from an open page is much less, defined by the /CAS to /CAS cycle time. The quoted number is the clearest way to compare between the performance of different DRAM memories, as it sets the slower limit regardless of the row length or page size. Bigger arrays forcibly result in larger bit line capacitance and longer propagation delays, which cause this time to increase as the sense amplifier settling time is dependant on both the capacitance as well as the propagation latency. This is countered in modern DRAM chips by instead integrating many more complete DRAM arrays within a single chip, to accommodate more capacity without becoming too slow.


title: Dynamic random-access memory

text: When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100 MHz state machine (i.e. a 10 ns clock), the 50 ns DRAM can perform the first read in five clock cycles, and additional reads within the same page every two clock cycles. This was generally described as timing, as bursts of four reads within a page were common.


title: Dynamic random-access memory

text: When describing synchronous memory, timing is described by clock cycle counts separated by hyphens. These numbers represent in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when double data rate signaling is used. JEDEC standard PC3200 timing is with a 200 MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at timing.


title: Dynamic random-access memory

text: Minimum random access time has improved from "t" = 50 ns to , and even the premium 20 ns variety is only 2.5 times better compared to the typical case (~2.22 times better). CAS latency has improved even less, from to 10 ns. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25 ns , while the EDO DRAM can output one word per "t" = 20 ns (50 Mword/s).


title: Dynamic random-access memory

text: Each bit of data in a DRAM is stored as a positive or negative electrical charge in a capacitive structure. The structure providing the capacitance, as well as the transistors that control access to it, is collectively referred to as a "DRAM cell". They are the fundamental building block in DRAM arrays. Multiple DRAM memory cell variants exist, but the most commonly used variant in modern DRAMs is the one-transistor, one-capacitor (1T1C) cell. The transistor is used to admit current into the capacitor during writes, and to discharge the capacitor during reads. The access transistor is designed to maximize drive strength and minimize transistor-transistor leakage (Kenner, pg. 34).


title: Dynamic random-access memory

text: The capacitor has two terminals, one of which is connected to its access transistor, and the other to either ground or V/2. In modern DRAMs, the latter case is more common, since it allows faster operation. In modern DRAMs, a voltage of +V/2 across the capacitor is required to store a logic one; and a voltage of -V/2 across the capacitor is required to store a logic zero. The electrical charge stored in the capacitor is measured in coulombs. For a logic one, the charge is: formula_1, where "Q" is the charge in coulombs and "C" is the capacitance in farads. A logic zero has a charge of: formula_2.


title: Dynamic random-access memory

text: Reading or writing a logic one requires the wordline is driven to a voltage greater than the sum of V and the access transistor's threshold voltage (V). This voltage is called "V pumped" (V). The time required to discharge a capacitor thus depends on what logic value is stored in the capacitor. A capacitor containing logic one begins to discharge when the voltage at the access transistor's gate terminal is above V. If the capacitor contains a logic zero, it begins to discharge when the gate terminal voltage is above V.


title: Dynamic random-access memory

text: Up until the mid-1980s, the capacitors in DRAM cells were co-planar with the access transistor (they were constructed on the surface of the substrate), thus they were referred to as "planar" capacitors. The drive to increase both density and, to a lesser extent, performance, required denser designs. This was strongly motivated by economics, a major consideration for DRAM devices, especially commodity DRAMs. The minimization of DRAM cell area can produce a denser device and lower the cost per bit of storage. Starting in the mid-1980s, the capacitor was moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as "stacked" or "folded plate" capacitors. Those with capacitors buried beneath the substrate surface are referred to as "trench" capacitors. In the 2000s, manufacturers were sharply divided by the type of capacitor used in their DRAMs and the relative cost and long-term scalability of both designs have been the subject of extensive debate. The majority of DRAMs, from major manufactures such as Hynix, Micron Technology, Samsung Electronics use the stacked capacitor structure, whereas smaller manufacturers such Nanya Technology use the trench capacitor structure (Jacob, pp. 355–357).


title: Dynamic random-access memory

text: The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in between two layers of polysilicon plates (the top plate is shared by all DRAM cells in an IC), and its shape can be a rectangle, a cylinder, or some other more complex shape. There are two basic variations of the stacked capacitor, based on its location relative to the bitline—capacitor-over-bitline (COB) and capacitor-under-bitline (CUB). In a former variation, the capacitor is underneath the bitline, which is usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal. In the latter variation, the capacitor is constructed above the bitline, which is almost always made of polysilicon, but is otherwise identical to the COB variation. The advantage the COB variant possesses is the ease of fabricating the contact between the bitline and the access transistor's source as it is physically close to the substrate surface. However, this requires the active area to be laid out at a 45-degree angle when viewed from above, which makes it difficult to ensure that the capacitor contact does not touch the bitline. CUB cells avoid this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology (Kenner, pp. 33–42).


title: Dynamic random-access memory

text: The trench capacitor is constructed by etching a deep hole into the silicon substrate. The substrate volume surrounding the hole is then heavily doped to produce a buried n plate and to reduce resistance. A layer of oxide-nitride-oxide dielectric is grown or deposited, and finally the hole is filled by depositing doped polysilicon, which forms the top plate of the capacitor. The top of the capacitor is connected to the access transistor's drain terminal via a polysilicon strap (Kenner, pp. 42–44). A trench capacitor's depth-to-width ratio in DRAMs of the mid-2000s can exceed 50:1 (Jacob, p. 357).


title: Dynamic random-access memory

text: Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus capacitance (Jacob, pp. 356–357). Alternatively, the capacitance can be increased by etching a deeper hole without any increase to surface area (Kenner, pg. 44). Another advantage of the trench capacitor is that its structure is under the layers of metal interconnect, allowing them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate. The fact that the capacitor is under the logic means that it is constructed before the transistors are. This allows high-temperature processes to fabricate the capacitors, which would otherwise be degrading the logic transistors and their performance. This makes trench capacitors suitable for constructing embedded DRAM (eDRAM) (Jacob, p. 357). Disadvantages of trench capacitors are difficulties in reliably constructing the capacitor's structures within deep holes and in connecting the capacitor to the access transistor's drain terminal (Kenner, pg. 44).


title: Dynamic random-access memory

text: First-generation DRAM ICs (those with capacities of 1 Kbit), of which the first was the Intel 1103, used a three-transistor, one-capacitor (3T1C) DRAM cell. By the second-generation, the requirement to increase density by fitting more bits in a given area, or the requirement to reduce cost by fitting the same amount of bits in a smaller area, lead to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16 Kbit capacities continued to use the 3T1C cell for performance reasons (Kenner, p. 6). These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out (non-destructive read). A second performance advantage relates to the 3T1C cell has separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where a value is read, modified, and then written back as a single, indivisible operation (Jacob, p. 459).


title: Dynamic random-access memory

text: The one-transistor, zero-capacitor (1T) DRAM cell has been a topic of research since the late-1990s. "1T DRAM" is a different way of constructing the basic DRAM memory cell, distinct from the classic one-transistor/one-capacitor (1T/1C) DRAM cell, which is also sometimes referred to as "1T DRAM", particularly in comparison to the 3T and 4T DRAM which it replaced in the 1970s.


title: Dynamic random-access memory

text: In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitorless" bit cell design that stores data using the parasitic body capacitance that is inherent to silicon on insulator (SOI) transistors. Considered a nuisance in logic design, this floating body effect can be used for data storage. This gives 1T DRAM cells the greatest density as well as allowing easier integration with high-performance logic circuits since they are constructed with the same SOI process technologies.


title: Dynamic random-access memory

text: Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the threshold voltage of the transistor. Performance-wise, access times are significantly better than capacitor-based DRAMs, but slightly worse than SRAM. There are several types of 1T DRAMs: the commercialized Z-RAM from Innovative Silicon, the TTRAM from Renesas and the A-RAM from the UGR/CNRS consortium.


title: Dynamic random-access memory

text: DRAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines. The physical layout of the DRAM cells in an array is typically designed so that two adjacent DRAM cells in a column share a single bitline contact to reduce their area. DRAM cell area is given as "n" F, where "n" is a number derived from the DRAM cell design, and "F" is the smallest feature size of a given process technology. This scheme permits comparison of DRAM size over different process technology generations, as DRAM cell area scales at linear or near-linear rates with respect to feature size. The typical area for modern DRAM cells varies between 6–8 F.


title: Dynamic random-access memory

text: The horizontal wire, the wordline, is connected to the gate terminal of every access transistor in its row. The vertical bitline is connected to the source terminal of the transistors in its column. The lengths of the wordlines and bitlines are limited. The wordline length is limited by the desired performance of the array, since propagation time of the signal that must transverse the wordline is determined by the RC time constant. The bitline length is limited by its capacitance (which increases with length), which must be kept within a range for proper sensing (as DRAMs operate by sensing the charge of the capacitor released onto the bitline). Bitline length is also limited by the amount of operating current the DRAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of the bitline.


title: Dynamic random-access memory

text: Sense amplifiers are required to read the state contained in the DRAM cells. When the access transistor is activated, the electrical charge in the capacitor is shared with the bitline. The bitline's capacitance is much greater than that of the capacitor (approximately ten times). Thus, the change in bitline voltage is minute. Sense amplifiers are required to resolve the voltage differential into the levels specified by the logic signaling system. Modern DRAMs use differential sense amplifiers, and are accompanied by requirements as to how the DRAM arrays are constructed. Differential sense amplifiers work by driving their outputs to opposing extremes based on the relative voltages on pairs of bitlines. The sense amplifiers function effectively and efficient only if the capacitance and voltages of these bitline pairs are closely matched. Besides ensuring that the lengths of the bitlines and the number of attached DRAM cells attached to them are equal, two basic architectures to array design have emerged to provide for the requirements of the sense amplifiers: open and folded bitline arrays.


title: Dynamic random-access memory

text: The first generation (1 Kbit) DRAM ICs, up until the 64 Kbit generation (and some 256 Kbit generation devices) had open bitline array architectures. In these architectures, the bitlines are divided into multiple segments, and the differential sense amplifiers are placed in between bitline segments. Because the sense amplifiers are placed between bitline segments, to route their outputs outside the array, an additional layer of interconnect placed above those used to construct the wordlines and bitlines is required.


title: Dynamic random-access memory

text: The DRAM cells that are on the edges of the array do not have adjacent segments. Since the differential sense amplifiers require identical capacitance and bitline lengths from both segments, dummy bitline segments are provided. The advantage of the open bitline array is a smaller array area, although this advantage is slightly diminished by the dummy bitline segments. The disadvantage that caused the near disappearance of this architecture is the inherent vulnerability to noise, which affects the effectiveness of the differential sense amplifiers. Since each bitline segment does not have any spatial relationship to the other, it is likely that noise would affect only one of the two bitline segments.


title: Dynamic random-access memory

text: The folded bitline array architecture routes bitlines in pairs throughout the array. The close proximity of the paired bitlines provide superior common-mode noise rejection characteristics over open bitline arrays. The folded bitline array architecture began appearing in DRAM ICs during the mid-1980s, beginning with the 256 Kbit generation. This architecture is favored in modern DRAM ICs for its superior noise immunity.


title: Dynamic random-access memory

text: This architecture is referred to as "folded" because it takes its basis from the open array architecture from the perspective of the circuit schematic. The folded array architecture appears to remove DRAM cells in alternate pairs (because two DRAM cells share a single bitline contact) from a column, then move the DRAM cells from an adjacent column into the voids.


title: Dynamic random-access memory

text: The location where the bitline twists occupies additional area. To minimize area overhead, engineers select the simplest and most area-minimal twisting scheme that is able to reduce noise under the specified limit. As process technology improves to reduce minimum feature sizes, the signal to noise problem worsens, since coupling between adjacent metal wires is inversely proportional to their pitch. The array folding and bitline twisting schemes that are used must increase in complexity in order to maintain sufficient noise reduction. Schemes that have desirable noise immunity characteristics for a minimal impact in area is the topic of current research (Kenner, p. 37).


title: Dynamic random-access memory

text: Advances in process technology could result in open bitline array architectures being favored if it is able to offer better long-term area efficiencies; since folded array architectures require increasingly complex folding schemes to match any advance in process technology. The relationship between process technology, array architecture, and area efficiency is an active area of research.


title: Dynamic random-access memory

text: The first DRAM integrated circuits did not have any redundancy. An integrated circuit with a defective DRAM cell would be discarded. Beginning with the 64 Kbit generation, DRAM arrays have included spare rows and columns to improve yields. Spare rows and columns provide tolerance of minor fabrication defects which have caused a small number of rows or columns to be inoperable. The defective rows and columns are physically disconnected from the rest of the array by a triggering a programmable fuse or by cutting the wire by a laser. The spare rows or columns are substituted in by remapping logic in the row and column decoders (Jacob, pp. 358–361).


title: Dynamic random-access memory

text: Electrical or magnetic interference inside a computer system can cause a single bit of DRAM to spontaneously flip to the opposite state. The majority of one-off ("soft") errors in DRAM chips occur as a result of background radiation, chiefly neutrons from cosmic ray secondaries, which may change the contents of one or more memory cells or interfere with the circuitry used to read/write them.


title: Dynamic random-access memory

text: The problem can be mitigated by using redundant memory bits and additional circuitry that use these bits to detect and correct soft errors. In most cases, the detection and correction are performed by the memory controller; sometimes, the required logic is transparently implemented within DRAM chips or modules, enabling the ECC memory functionality for otherwise ECC-incapable systems. The extra memory bits are used to record parity and to enable missing data to be reconstructed by error-correcting code (ECC). Parity allows the detection of all single-bit errors (actually, any odd number of wrong bits). The most common error-correcting code, a SECDED Hamming code, allows a single-bit error to be corrected and, in the usual configuration, with an extra parity bit, double-bit errors to be detected.


title: Dynamic random-access memory

text: Recent studies give widely varying error rates with over seven orders of magnitude difference, ranging from , roughly one bit error, per hour, per gigabyte of memory to one bit error, per century, per gigabyte of memory. The Schroeder et al. 2009 study reported a 32% chance that a given computer in their study would suffer from at least one correctable error per year, and provided evidence that most such errors are intermittent hard rather than soft errors and that race amounts of radioactive material that had gotten into the chip packaging were emitting alpha particles and corrupting the data. A 2010 study at the University of Rochester also gave evidence that a substantial fraction of memory errors are intermittent hard errors. Large scale studies on non-ECC main memory in PCs and laptops suggest that undetected memory errors account for a substantial number of system failures: the 2011 study reported a 1-in-1700 chance per 1.5% of memory tested (extrapolating to an approximately 26% chance for total memory) that a computer would have a memory error every eight months.


title: Dynamic random-access memory

text: Although dynamic memory is only specified and "guaranteed" to retain its contents when supplied with power and refreshed every short period of time (often ), the memory cell capacitors often retain their values for significantly longer time, particularly at low temperatures. Under some conditions most of the data in DRAM can be recovered even if it has not been refreshed for several minutes.


title: Dynamic random-access memory

text: This property can be used to circumvent security and recover data stored in the main memory that is assumed to be destroyed at power-down. The computer could be quickly rebooted, and the contents of the main memory read out; or by removing a computer's memory modules, cooling them to prolong data remanence, then transferring them to a different computer to be read out. Such an attack was demonstrated to circumvent popular disk encryption systems, such as the open source TrueCrypt, Microsoft's BitLocker Drive Encryption, and Apple's FileVault. This type of attack against a computer is often called a cold boot attack.


title: Dynamic random-access memory

text: Dynamic memory, by definition, requires periodic refresh. Furthermore, reading dynamic memory is a destructive operation, requiring a recharge of the storage cells in the row that has been read. If these processes are imperfect, a read operation can cause soft errors. In particular, there is a risk that some charge can leak between nearby cells, causing the refresh or read of one row to cause a "disturbance error" in an adjacent or even nearby row. The awareness of disturbance errors dates back to the first commercially available DRAM in the early 1970s (the Intel 1103). Despite the mitigation techniques employed by manufacturers, commercial researchers proved in a 2014 analysis that commercially available DDR3 DRAM chips manufactured in 2012 and 2013 are susceptible to disturbance errors. The associated side effect that led to observed bit flips has been dubbed "row hammer".


title: Dynamic random-access memory

text: Dynamic RAM ICs are usually packaged in molded epoxy cases, with an internal lead frame for interconnections between the silicon die and the package leads. The original IBM PC design used ICs packaged in dual in-line packages (DIP), soldered directly to the main board or mounted in sockets. As memory density skyrocketed, the DIP package was no longer practical. For convenience in handling, several dynamic RAM integrated circuits may be mounted on a single memory module, allowing installation of 16-bit, 32-bit or 64-bit wide memory in a single unit, without the requirement for the installer to insert multiple individual integrated circuits. Memory modules may include additional devices for parity checking or error correction. Over the evolution of desktop computers, several standardized types of memory module have been developed. Laptop computers, game consoles, and specialized devices may have their own formats of memory modules not interchangeable with standard desktop parts for packaging or proprietary reasons.


title: Dynamic random-access memory

text: DRAM that is integrated into an integrated circuit designed in a logic-optimized process (such as an application-specific integrated circuit, microprocessor, or an entire system on a chip) is called "embedded DRAM" (eDRAM). Embedded DRAM requires DRAM cell designs that can be fabricated without preventing the fabrication of fast-switching transistors used in high-performance logic, and modification of the basic logic-optimized process technology to accommodate the process steps required to build DRAM cell structures.


title: Dynamic random-access memory

text: Since the fundamental DRAM cell and array has maintained the same basic structure for many years, the types of DRAM are mainly distinguished by the many different interfaces for communicating with DRAM chips.


title: Dynamic random-access memory

text: The original DRAM, now known by the retronym ""asynchronous DRAM"" was the first type of DRAM in use. From its origins in the late 1960s, it was commonplace in computing up until around 1997, when it was mostly replaced by "Synchronous DRAM". In the present day, manufacture of asynchronous RAM is relatively rare.


title: Dynamic random-access memory

text: An asynchronous DRAM chip has power connections, some number of address inputs (typically 12), and a few (typically one or four) bidirectional data lines. There are four active-low control signals:


title: Dynamic random-access memory

text: This interface provides direct control of internal timing. When is driven low, a cycle must not be attempted until the sense amplifiers have sensed the memory state, and must not be returned high until the storage cells have been refreshed. When is driven high, it must be held high long enough for precharging to complete.


title: Dynamic random-access memory

text: Although the DRAM is asynchronous, the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle.


title: Dynamic random-access memory

text: The refresh cycles are distributed across the entire refresh interval in such a way that all rows are refreshed within the required interval. To refresh one row of the memory array using only refresh (ROR), the following steps must occur:


title: Dynamic random-access memory

text: This can be done by supplying a row address and pulsing low; it is not necessary to perform any cycles. An external counter is needed to iterate over the row addresses in turn. In some designs, the CPU handled RAM refresh, among these the Zilog Z80 is perhaps the best known example, hosting a row counter in a processor register, R, and including internal timers that would periodically poll the row at R and then increment the value in the register. Refreshes were interleaved with common instructions like memory reads. In other systems, especially home computers, refresh was often handled by the video circuitry as it often had to read from large areas of memory, and performed refreshes as part of these operations.


title: Dynamic random-access memory

text: For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the line is driven low before (normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open. This is known as -before- (CBR) refresh. This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM.


title: Dynamic random-access memory

text: Given support of -before- refresh, it is possible to deassert while holding low to maintain data output. If is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as "hidden refresh".


title: Dynamic random-access memory

text: "Page mode DRAM" is a minor modification to the first-generation DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In Page mode DRAM, after a row was opened by holding low, the row could be kept open, and multiple reads or writes could be performed to any of the columns in the row. Each column access was initiated by asserting and presenting a column address. For reads, after a delay ("t"), valid data would appear on the data out pins, which were held at high-Z before the appearance of valid data. For writes, the write enable signal and write data would be presented along with the column address.


title: Dynamic random-access memory

text: Page mode DRAM was later improved with a small modification which further reduced latency. DRAMs with this improvement were called "fast page mode DRAMs" ("FPM DRAMs"). In page mode DRAM, was asserted before the column address was supplied. In FPM DRAM, the column address could be supplied while was still deasserted. The column address propagated through the column address data path, but did not output data on the data pins until was asserted. Prior to being asserted, the data out pins were held at high-Z. FPM DRAM reduced "t" latency. Fast page mode DRAM was introduced in 1986 and was used with Intel 80486.


title: Dynamic random-access memory

text: "Static column" is a variant of fast page mode in which the column address does not need to be stored in, but rather, the address inputs may be changed with held low, and the data output will be updated accordingly a few nanoseconds later.


title: Dynamic random-access memory

text: "Nibble mode" is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of . The difference from normal page mode is that the address inputs are not used for the second through fourth edges; they are generated internally starting with the address supplied for the first edge.


title: Dynamic random-access memory

text: Extended data out DRAM (EDO DRAM) was invented and patented in the 1990s by Micron Technology who then licensed technology to many other memory manufacturers. EDO RAM, sometimes referred to as "Hyper Page Mode" enabled DRAM, is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance. It is up to 30% faster than FPM DRAM, which it began to replace in 1995 when Intel introduced the 430FX chipset with EDO DRAM support. Irrespective of the performance gains, FPM and EDO SIMMs can be used interchangeably in many (but not all) applications.


title: Dynamic random-access memory

text: To be precise, EDO DRAM begins data output on the falling edge of , but does not stop the output when rises again. It holds the output valid (thus extending the data output time) until either is deasserted, or a new falling edge selects a different column address.


title: Dynamic random-access memory

text: Single-cycle EDO has the ability to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM access within the same page takes two clock cycles instead of three, once the page has been selected. EDO's performance and capabilities created an opportunity to reduce the immense performance loss associated with a lack of L2 cache in low-cost, commodity PCs. This was also good for notebooks due to difficulties with their limited form factor, and battery life limitations. Additionally, for systems with an L2 cache, the availability of EDO memory improved the average memory latency seen by applications over earlier FPM implementations.


title: Dynamic random-access memory

text: Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM.


title: Dynamic random-access memory

text: An evolution of EDO DRAM, burst EDO DRAM (BEDO DRAM), could process four memory addresses in one burst, for a maximum of , saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipeline stage allowing page-access cycle to be divided into two parts. During a memory-read operation, the first part accessed the data from the memory array to the output stage (second latch). The second part drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up to 50% for large blocks of data) than with traditional EDO.


title: Dynamic random-access memory

text: Although BEDO DRAM showed additional optimization over EDO, by the time it was available the market had made a significant investment towards synchronous DRAM, or SDRAM. Even though BEDO RAM was superior to SDRAM in some ways, the latter technology quickly displaced BEDO.


title: Dynamic random-access memory

text: Synchronous dynamic RAM (SDRAM) significantly revises the asynchronous memory interface, adding a clock (and a clock enable) line. All other signals are received on the rising edge of the clock.


title: Dynamic random-access memory

text: The and inputs no longer act as strobes, but are instead, along with , part of a 3-bit command controlled by a new active-low strobe, "chip select" or :


title: Dynamic random-access memory

text: The line's function is extended to a per-byte "DQM" signal, which controls data input (writes) in addition to data output (reads). This allows DRAM chips to be wider than 8 bits while still supporting byte-granularity writes.


title: Dynamic random-access memory

text: Many timing parameters remain under the control of the DRAM controller. For example, a minimum time must elapse between a row being activated and a read or write command. One important parameter must be programmed into the SDRAM chip itself, namely the CAS latency. This is the number of clock cycles allowed for internal operations between a read command and the first data word appearing on the data bus. The "Load mode register" command is used to transfer this value to the SDRAM chip. Other configurable parameters include the length of read and write bursts, i.e. the number of words transferred per read or write command.


title: Dynamic random-access memory

text: The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of "bank address" which accompany each command, a second bank can be activated and begin reading data "while a read from the first bank is in progress". By alternating banks, an SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot.


title: Dynamic random-access memory

text: Single data rate SDRAM (SDR SDRAM or SDR) is the original generation of SDRAM; it made a single transfer of data per clock cycle.


title: Dynamic random-access memory

text: Double data rate SDRAM (DDR SDRAM or DDR) was a later development of SDRAM, used in PC memory beginning in 2000. Subsequent versions are numbered sequentially ("DDR2", "DDR3", etc.). DDR SDRAM internally performs double-width accesses at the clock rate, and uses a double data rate interface to transfer one half on each clock edge. DDR2 and DDR3 increased this factor to 4× and 8×, respectively, delivering 4-word and 8-word bursts over 2 and 4 clock cycles, respectively. The internal access rate is mostly unchanged (200 million per second for DDR-400, DDR2-800 and DDR3-1600 memory), but each access transfers more data.


title: Dynamic random-access memory

text: "Direct RAMBUS DRAM" ("DRDRAM") was developed by Rambus. First supported on motherboards in 1999, it was intended to become an industry standard, but was outcompeted by DDR SDRAM, making it technically obsolete by 2003.


title: Dynamic random-access memory

text: Reduced Latency DRAM (RLDRAM) is a high performance double data rate (DDR) SDRAM that combines fast, random access with high bandwidth, mainly intended for networking and caching applications.


title: Dynamic random-access memory

text: Graphics RAMs are asynchronous and synchronous DRAMs designed for graphics-related tasks such as texture memory and framebuffers, found on video cards.


title: Dynamic random-access memory

text: Video DRAM (VRAM) is a dual-ported variant of DRAM that was once commonly used to store the frame-buffer in some graphics adaptors.


title: Dynamic random-access memory

text: Window DRAM (WRAM) is a variant of VRAM that was once used in graphics adaptors such as the Matrox Millennium and ATI 3D Rage Pro. WRAM was designed to perform better and cost less than VRAM. WRAM offered up to 25% greater bandwidth than VRAM and accelerated commonly used graphical operations such as text drawing and block fills.


title: Dynamic random-access memory

text: Multibank DRAM (MDRAM) is a type of specialized DRAM developed by MoSys. It is constructed from small memory banks of , which are operated in an interleaved fashion, providing bandwidths suitable for graphics cards at a lower cost to memories such as SRAM. MDRAM also allows operations to two banks in a single clock cycle, permitting multiple concurrent accesses to occur if the accesses were independent. MDRAM was primarily used in graphic cards, such as those featuring the Tseng Labs ET6x00 chipsets. Boards based upon this chipset often had the unusual capacity of because of MDRAM's ability to be implemented more easily with such capacities. A graphics card with of MDRAM had enough memory to provide 24-bit color at a resolution of 1024×768—a very popular setting at the time.


title: Dynamic random-access memory

text: Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies.


title: Dynamic random-access memory

text: Graphics double data rate SDRAM is a type of specialized DDR SDRAM designed to be used as the main memory of graphics processing units (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2020, there are seven, successive generations of GDDR: GDDR2, GDDR3, GDDR4, GDDR5, GDDR5X, GDDR6 and GDDR6X.


title: Dynamic random-access memory

text: Pseudostatic RAM (PSRAM or PSDRAM) is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM. PSRAM is used in the Apple iPhone and other embedded systems such as XFlar Platform.


title: Dynamic random-access memory

text: Some DRAM components have a "self-refresh mode". While this involves much of the same logic that is needed for pseudo-static operation, this mode is often equivalent to a standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, rather than to allow operation without a separate DRAM controller as is in the case of mentioned PSRAMs.


title: Dynamic random-access memory

text: An embedded variant of PSRAM was sold by MoSys under the name 1T-SRAM. It is a set of small DRAM banks with an SRAM cache in front to make it behave much like a true SRAM. It is used in Nintendo GameCube and Wii video game consoles.


title: Dynamic random-access memory

text: Cypress Semiconductor's HyperRAM is a type of PSRAM supporting a JEDEC-compliant 8-pin HyperBus or Octal xSPI interface.


title: Izuku Midoriya

text: , also known by his hero name , is a superhero and the main protagonist of the manga series "My Hero Academia", created by Kōhei Horikoshi. In the series, he is a nerdy and ambitious high schooler misfit and the 9th (and current) holder of "One For All" (ワン・フォー・オール, "Wan Fō Ōru"), a superpower which combines eight different individual superpowers, or ""Quirks"", together and creates powerful bursts of energy, and also has the unique ability to be passed off to other people.