Tim Turner, the Reliability Center Business Development Manager at the College of Nanoscale Science and Engineering (CNSE), Albany, NY, blogs about the potential of resistive memory and the reliability challenges the must be overcome.
Resistive Memory, RRAM or Memristors is a hot topic right now. RRAM has the potential for single digit nano parameters (speed as fast as 1 ns, area per bit as small as 5 square nm) and is non-volatile.
The technology is based on the formation of a small conductive filament inside an insulator. The filament is formed the first time using a high voltage. After that, set or reset transformation (conductive to non-conductive or visa versa) is accomplished by moving one or a few atoms an atomic scale distance. This can be done with a low voltage (less than a volt). This small movement gives a repeatable set or reset that can withstand many cycles.
Conduction in the filament appears to be due to oxygen vacancies existing in a percolation path through the insulator. A small electric field in the reverse direction causes the migration of these oxygen vacancies in a mechanism similar to electromigration of Al or Cu atoms in a metal line. Momentum exchange between electrons and the vacancies appears to be the driving force. The vacancies do not have to move far to open the small filament. An oxygen vacancy moves an atomic scale distance and the tiny filament opens, allowing an insulator to exist between points in the filament. Forcing a forward voltage can move the oxygen vacancy back into the area where the filament is conductive. This small movement can give a 100X change in the conduction through the dielectric. This is the state change that can be interpreted as the digital signal stored on the memory cell.
The material set used for RRAM is CMOS compatible. RRAM cells have been made out of Cu/HfOx , Al/AlOx/Pt, TiN/AlOx/Pt or even Al/AlOx/CNT (Carbon Nano Tubes). Most of the work reported to date has been on arrays where the cell is similar to a DRAM, using one transistor and one capacitor . The RRAM cell starts with a capacitor, then forms the filament in the capacitor dielectric. The advantage this technology has is the smaller size of the capacitor. There is no need for deep trenches in the silicon or for thick vertical stacks. The technology is also non-volatile, so there is no need to refresh the charge every few milliseconds.
In polycrystalline materials, the filaments appear to form along grain boundaries between crystals . For amorphous material there are no grain boundaries, but the material is reported to be able to withstand more cycles before failure .
RRAM might also be produced with a simple single resistor cross-point array (no transistor per cell required). Figure 1 shows an array where the each cell is addressed by a row and a column. The conduction in the row/column pair determines if the cell is set or reset (conductive or insulating). This arrangement has the distinct advantage of allowing the memory array to be printed on top of a logic circuit. Active circuits are required only for the address circuitry, allowing a large memory array to be added with little additional silicon area.
|Figure 1: Cross-point RRAM cell|
That is the good news. Now for the bad news. What are the technology challenges that prevent you from enjoying this technology today?
The first issue is one of measurement noise. With atomic spacing causing the difference between a set and a reset state, there is some uncertainty in the answer. Sometimes, a bit will not program. Nimal Ramaswamy of Micron  reported that random bits in a large array failed any given write operation. There was an average number of failures for each write of a large array, but different bits failed each time. Every bit apparently has the same probability of failure.
Random Telegraph Noise (RTN) is another issue. The state of the bit will most likely be read by forcing voltage and measuring current. RTN is caused by trap states in the gate dielectric of a transistor that might address the bit. These traps randomly fill or emit, changing the conduction of the channel. The noise generated by this increases as the transistors are scaled. Originally, this was thought to be just the larger impact of a single trap on a smaller area gate , but Realov and Shepard  showed that shorter L transistors show a greater noise than longer transistors with the same total area (below 40nm). Thus, this is a problem that will increase as the technology is scaled. There is also a chance that RTN will be generated by the movement of oxygen vacancies in the filament itself.
Degraeve et. Al.  reported a highly voltage sensitive disturb in the reset state. Their RRAM cell could withstand 100 thousand disturb pulses (100ns) at -0.5 volts, but at -0.6 volts the cell could only withstand a little over 100 pulses. They also showed that the sensitivity to disturb could be reduced significantly by balancing and optimizing the set and reset pulses.
|Figure 2: Disturb in Reset State|
Optimization of the Set and reset pulses also has a strong impact on the set/reset cycling endurance of the cell. Degraeve was able to show up to 10 G set/reset pulses after optimization.
Wu et. Al  showed the impact of scaling on a cross-point array. According to their model, scaling the technology from 22nm to 5 nm resulted in an increase for the parasitic word and bit line resistance from under 10 ohms to almost 100,000 ohms as the lines width and thickness are reduced. Adding to the significance of this is the variation in resistance between the closest cell in the array and the furthest call in the array. This variation could be over 4 orders of magnitude while the difference between the set and reset resistance is only 2 orders of magnitude. This issue could restrict the size of sub arrays, compromising the potential area savings using this technology.
As the metal lines are scaled to obtain higher memory densities, the filament that generates the conduction in the cell does not scale. That means the set and reset pulse currents remain about the same as the array is scaled. This results in an electromigration issue in the scaled metal lines.
|Figure 3: Oxygen Vacancy Filament Determines Set or Reset State of RRAM Memory Cell|
RRAM is certainly an appealing technology with its ability to scale the cell to tiny dimensions, good speed, CMOS compatible material set and the possibility of mounting the technology above a logic array. Unfortunately, the devil is in the details and the list of advantages is balanced by a list of problems that must be overcome before this technology can carve out a space as a memory solution.
1] Jihan Capulong, Benjamin Briggs, Seann Bishop, Michael Hovish, Richard Matyi, Nathaniel Cady, College of Nanoscale Science and Engineering, “Effect of Crystallinity on Endurance and Switching Behavior of HfOx based Resistive Memory Devices”, Proceedings of the International Integrated Reliability Workshop 2012
2] Yi Wu, Jiale Liang, Shimeng Yu, Ximeng Guan and H. S. Philip Wong, Stanford University, “Resistive Switching Random Access Memory – Materials, Device, Interconnects and Scaling Considerations”, Proceedings of the International Integrated Reliability Workshop, 2012
3] Nirmal Ramaswamy, Micron, “Challenges in Engineering RRAM Technology for High Density Applications”, Proceedings of the International Integrated Reliability Workshop, 2012
4] K.K. Hong, P.K Ko, Chemming Hu and Yiu Cheng, Random Telegraph Noise of Deep Sub-Micrometer MOSFETs, 1990 IEEE 1741-3106/90/0200-0090 http://www.eecs.berkeley.edu/~hu/PUBLICATIONS/Hu_papers/Hu_JNL/HuC_JNL_167.pdf
5] Simeon Realov and Kenneth L. Shepard, “Random telegraph noise in 45nm CMOS: Analysis Using an on-Chip Test and Measurement System, IEDM10-624, 978-1-4244-7419-6/10/$26.00 ©2010 IEEE, http://bioee.ee.columbia.edu/downloads/2010/S28P02.PDF
6] R. Degraeve, A. Fantini, S. Clima, B. Guvoreanu, L. Goux, Y. Y. Chen, D. J. Wouters, Ph. Rousset, G. S. Kar, G. Pourtois, S. Cosemans, J. A. kittl, G. Groeseneken, M. Jurczak, l. Altimime, IMEC, “Reliability of Low Current Filamentary HfO2 RRAM Discussed in the Framework of the Hourglass set/reset Model”, Proceedings of the Integrated Reliability Workshop, 2012.
7] Gennadi Bersuker, SEMATECH, “Origin of Conductive Filaments and Resistive Switching in HfO2 based RRAMS” Proceedings of the International Integrated Reliablity Workshop, 2012, 1.2-1