e718583c_operating_method___Patents_com__Description
[Patent #] US-8,006,068 [Description] 
Processor access to data cache with fixed or low variable latency via instructions to an auxiliary processing unit Access to data storage is described. A general-purpose processor and an auxiliary processing unit (APU) interface coupled to the general-purpose processor are...
Patents filed at Aug 23 2011 | Central processing unit with multiple clock zones and operating method | Patents.com