CMP Fill Synthesis: A Survey of Recent Studies
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paper_title: DFM: linking design and manufacturing

paper_content:

Until the move to the 130nm node, yield was an issue only for product engineers and engineers on the production line. Design engineers did not need to think explicitly about yield, or understand the manufacturing process. Beginning at the 130nm node, yield has become more problematic, and the defect mechanisms that contribute to yield loss are very different. Where random defects used to be dominant, we now have defects due to lithographic issues, and pattern (or design) dependent issues. This paper explains how these latter defect mechanisms differ from random defects and how and why the design engineer needs to become involved to mitigate the problem. On the lithography topic, this paper briefly examines techniques such as OPC (optical proximity correction) and PSM (phase shift masking), and explain their design and yield impact. We also examine issues such as dummy metal fill for CMP, redundant via insertion, as ways to mitigate pattern dependent yield issues.
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paper_title: The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes

paper_content:

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.
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paper_title: Chemical processes in glass polishing

paper_content:

Abstract Chemical processes which occur during glass polishing are reviewed within the context of current mechanical models for the polishing process. The central chemical process which occurs is the interaction of both the glass surface and the polishing particle with water. A detailed mechanico-chemical model for the polishing process is proposed.
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paper_title: Implementation of CMP-based design rules and patterning practices

paper_content:

This paper discusses specific die patterning techniques utilized during the implementation of a CMP-based BEOL within Digital's Alpha technologies. Customary application of inter-level dielectric (ILD) CMP, to eliminate topographically induced defect mechanisms and increase photolithographic focal budget margins for Alpha, indicated the need to strictly control both interand intra-die dielectric capacitance and thickness. To this end, several die patterning strategies were used to minimize the feature size and pattern density dependencies of ILD CMP as well as aid in the fast paced evolution from test vehicle to product chip reticles. Quantification of inter-level and intra-die thickness control with respect to ghost/partial die patterning, zero level (ZL) and perimeter bordering, dummy/filler feature patterning and general CMP-based design rules will be addressed within the context of analysis of variance (ANOVA). Further discussed will be the empirical rules-of-thumb and critical dimension (CD) variance definitions which provided the planarity targets utilized throughout the framework of these experiments.
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paper_title: Using Smart Dummy Fill And Selective Reverse Etchback For Pattern Density Equalization

paper_content:

The techniques of dummy fill and reverse etchback are often used prior to a chemical mechanical polishing (CMP) process to prevent film pattern density mismatches that lead to post-CMP film thickness variation. In this work, we present a methodology that utilizes both techniques in an intelligent fashion, and shows that both techniques can be used together to create a better balance of pattern densities than each technique can do separately. We introduce the idea of a selective reverse etchback method to lower the pattern density in high density regions, and smart dummy fill to raise pattern densities in low density regions. We then verify the methodology on the STI active area layer of a test mask.
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paper_title: Effects of slurry flow rate and pad conditioning temperature on dishing, erosion, and metal loss during copper CMP

paper_content:

Center for USA The effect of slurry flow rate, pad surface temperature, and temperature during the pad conditioning process on surface tribology and pattern-related defects like dishing, erosion, and metal loss was studied. Experimental results suggest that dishing and erosion levels decreased with increase in slurry flow rate. Conditioning experiments at various temperatures revealed a significant impact of temperature on the effectiveness of the conditioning process and also on subsequent polishing performance. The polishing pad was conditioned more aggressively at lower temperatures compared to conditioning at elevated temperatures. The removal rate and coefficient of friction were found to be significantly affected by the pad surface temperature. The amount of dishing increased with increase in pad surface temperature and the uniformity of polishing. The study ascertains a correlation between process parameters and the extent of planarity defects. This study also demonstrates the use of a modified bench-top chemical mechanical polish (CMP) tester and large-stage atomic force microscope with automatic multiscan imaging procedure.
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paper_title: Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

paper_content:

Abstract Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization) and its logic family (which uses four oxide and four tungsten-stud planarization steps). CMP is also used in the planarization of oxide shallow isolation trenches, as in the 16-Mbit DRAM. Reduced sensitivity to many types of defects is possible with CMP. A wafer that is truly flat is easier to clean, eliminates step coverage concerns, provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures. Oxide CMP reduces sensitivity to certain pre-existing defects, such as crystalline inclusions or foreign material in an interlevel dielectric. Metal CMP can reduce the incidence of intralevel shorts relative to conventional RIE processing. Random defects associated with CMP, such as slurry residues and mechanical damage, are controlled by careful optimization of the post-polish clean and of the polish process itself. Systematic defects, such as incomplete planarization over very large structures, are controlled by process optimization and prudent design limitations. These include such things as constraints on the image size, the distance between images, and/or the local pattern density. Since its introduction in the 4-Mbit DRAM, there has been a steady increase in the use of chemical-mechanical polishing in IBM CMOS products. The number of steps, processes and materials polished continue to rise, both in current and planned future products. Individual applications range from the simple removal of back-side films to complex insulator or metal planarization requiring high removal uniformity. The process tolerances delivered by CMP have decreased faster than image size, even in the face of dramatic increases in circuit and layout complexity. CMP tools are installed in IBM semiconductor manufacturing and development sites worldwide. Chemical-mechanical polish processes and applications provide unique leverage to IBM products, and are a crucial part of both current and planned IBM CMOS technologies.
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paper_title: Filling and slotting: analysis and algorithms

paper_content:

In very deep-submicron VLSI, certain manufacturing steps &mdash notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)&mdash have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future place-and-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.
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paper_title: Spin-On Glass: Materials and Applications in Advanced IC Technologies

paper_content:

This thesis deals with the study of shallow PN junction formation by dopant diffusion from Spin-On Glass (SOG) for future deep sub-micron BiCMOS technology. With the advantages of no transient enhanced diffusion and no metal contamination, diffusion from highly doped SOG (also called spin-on dopant - SOD) is a good technology for shallow junction formation. In this thesis, diffusion of impurities from SOD into Si and polysilicon on silicon structure has been studied. This shallow junction formation technique using SOD has been applied in realisation of two important devices, i.e. high frequency bipolar transistor and deep sub-micron elevated source/drain MOSFET.
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paper_title: Handbook of VLSI microlithography : principles, technology, and applications

paper_content:

Issues and Trends Affecting Lithography Tool Selection Strategy Resist Technology u Design, Processing, and Applications Lithography Process Monitoring and Defect Detection Techniques and Tools for Photo Metrology Techniques and Tools for Optical Lithography Microlithography Tool Automation Electron-Beam ULSI Applications Rational Vibration and Structural Dynamics for Lithographic Tool Installations Applications of Ion Microbeams Lithography and Direct Processing X-Ray Lithography Part I Part II Acknowledgment References Index
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paper_title: Arrhenius Characterization of ILD and Copper CMP Processes

paper_content:

To date, chemical mechanical planarization (CMP) models have relied heavily on parameters such as pressure, velocity, slurry, and pad properties to describe material removal rates. One key parameter, temperature, which can impact both the mechanical and chemical facets of the CMP process, is often neglected. Using a modified definition of the generalized Preston's equation with the inclusion of an Arrhenius relationship, thermally controlled polishing experiments are shown to quantify the contribution of temperature to the relative magnitude of the thermally dependent and thermally independent aspects of copper and interlayer dielectric (ILD) CMP. The newly defined Preston's equation includes a modified definition of the activation energy parameter contained in the Arrhenius portion, the combined activation energy, which describes all events (chemical or mechanical) that are impacted by temperature during CMP. Studies indicate that for every consumable set combination (i.e., slurry and polishing pad) a characteristic combined Arrhenius activation energy can be calculated for each substrate material being polished.
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paper_title: Modeling of chemical mechanical polishing for shallow trench isolation

paper_content:

Chemical mechanical polishing (CMP) is a key process enabling shallow trench isolation (STI), which is used in current integrated circuit manufacturing processes to achieve device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This thesis proposes characterization and modeling techniques to address a variety of concerns in STI CMP. Three major contributions of this work are: characterization and modeling of STI CMP processes, both conventional and nonconventional; layout optimization to reduce pattern-dependent dishing and erosion; and modeling of wafer nanotopography impact on STI CMP yield. An STI CMP characterization method is combined with a chip-scale pattern-dependent model to create a methodology that enables tuning of STI CMP process models and prediction of post-CMP dishing, erosion, and clearing times on arbitrary layouts. Model extensions enable characterization of STI CMP processes that use nonconventional consumable sets, including fixed abrasive pads and high-selectivity silica-based and ceria-based slurries. Experimental data validates the accuracy of the model for both conventional and nonconventional processes. Layout optimization techniques are developed that reduce pattern-density dependent dishing and erosion. Layout design modification is achieved through the use of dummy STI active areas and selective reverse etchback structures. Smart algorithms allow for optimal density distributions across the layout. The effect of wafer nanotopography (height variations that exist on unpatterned silicon wafers) is explored, characterized, and modelled. A diagnostic tool for examining the impact of nanotopography on STI device yields is developed, based on contact wear modeling. An aggregate estimator for the combined effect of wafer-scale nanotopography and chip-scale pattern-dependent dishing and erosion is developed. The techniques developed in this thesis can be used both for process optimization and for diagnosis and correction of potential problems due to layout, wafer and CMP process interaction. The characterization and modeling methods create a comprehensive set of tools for process characterization and post-CMP erosion and dishing prediction in STI processes. Thesis Supervisor: Duane S. Boning Title: Associate Professor of Electrical Engineering and Computer Science
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paper_title: Effect of Slurry Flow Rate on Tribological, Thermal, and Removal Rate Attributes of Copper CMP

paper_content:

cFujimi Incorporated, Kagamigahara, Gifu Prefecture 509-0108, Japan Chemical mechanical polishing of copper is examined experimentally and theoretically as a function of slurry flow rate and the product of applied wafer pressure and relative sliding speed ( p 3 V). It is observed that under constant tribological conditions, the removal rate at any fixed value ofp 3 V generally decreases as slurry flow rate increases. The increased cooling of the wafer surface, as a result of increased slurry flow rate, is used to explain this reduction in the reaction rate. At a fixed flow rate, it is further observed that removal rate does not necessarily increase monotonically with p 3 V. The rate instead depends on the particular values of pressure and velocity, regardless of the fact that they may result in the same value of p 3 V. This dependence is shown to be caused by changes in the coefficient for convective heat-transfer between the wafer and the slurry, as well as the heat partition factor, which determines the fraction of the total frictional power that heats the wafer. Results further indicate that trends in copper removal rate can be adequately explained with a Langmuir-Hinshelwood kinetics model with both mechanical and chemical rate components.
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paper_title: Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing

paper_content:

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role.
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paper_title: Filling and slotting: analysis and algorithms

paper_content:

In very deep-submicron VLSI, certain manufacturing steps &mdash notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)&mdash have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future place-and-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.
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paper_title: Study of Floating Fill Impact on Interconnect Capacitance

paper_content:

It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating fill can be reliably extracted by 3D field solvers only. Due to poor understanding of the impact of floating fill on capacitance, designers insert floating fill conservatively. In this paper we study the impact of floating fill insertion on coupling and total capacitance when the fill geometry, and both the interconnects between which the capacitance is measured are on the same layer. We show that the capacitance with same-layer neighboring interconnects is a large fraction of total capacitance, and that it is significantly affected by fill geometries on the same layer. We analyze the effect of fill configuration parameters such as fill size, fill location, interconnect width, interconnect spacing, etc. and consider edge effects and effects occurring due to insertion of several fill geometries in close proximity. Based on our findings, we propose certain guidelines to achieve high metal density while having smaller impact on interconnect capacitance. Finally, we validate the proposed guidelines using representative process parameters and a 3D field solver. On average coupling capacitance increase due to floating-fill insertion decreases by /spl sim/ 53% on using the proposed guidelines.
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paper_title: Variability-driven considerations in the design of integrated-circuit global interconnects

paper_content:

A torch with a turbulized supply of a plasma forming gas comprises an electrode having a high-melting insert and a flat end face, and a nozzle with an internal surface having two mated portions: one cylindrical and one tapering; and the diameter of the electrode flat end face amounts essentially to 0.4-0.5 diameter of the electrode proper and the radius of conjugation of the nozzle cylindrical and tapering portions is equal essentially to the length of its cylindrical portion. Due to such a design, the inventive torch features a long service life of both the electrode and the nozzle.
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paper_title: Dummy filling methods for reducing interconnect capacitance and number of fills

paper_content:

In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: (1) improved floating square fills, (2) floating parallel lines, and (3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.
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paper_title: A novel CBCM method free from charge injection induced errors: investigation into the impact of floating dummy-fills on interconnect capacitance

paper_content:

Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance measurement), a novel CBCM method free from the errors induced by charge-injection is developed. This is used for the first time to investigate the impact of floating dummy-fills on interconnect capacitance, in practice. The impact of floating dummy-fills is confirmed to play an important role on successful circuit design. Besides, a guideline to optimize the chip performance and minimize the crosstalk by dummy pattern design is also proposed in this paper.
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paper_title: Study of Floating Fill Impact on Interconnect Capacitance

paper_content:

It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating fill can be reliably extracted by 3D field solvers only. Due to poor understanding of the impact of floating fill on capacitance, designers insert floating fill conservatively. In this paper we study the impact of floating fill insertion on coupling and total capacitance when the fill geometry, and both the interconnects between which the capacitance is measured are on the same layer. We show that the capacitance with same-layer neighboring interconnects is a large fraction of total capacitance, and that it is significantly affected by fill geometries on the same layer. We analyze the effect of fill configuration parameters such as fill size, fill location, interconnect width, interconnect spacing, etc. and consider edge effects and effects occurring due to insertion of several fill geometries in close proximity. Based on our findings, we propose certain guidelines to achieve high metal density while having smaller impact on interconnect capacitance. Finally, we validate the proposed guidelines using representative process parameters and a 3D field solver. On average coupling capacitance increase due to floating-fill insertion decreases by /spl sim/ 53% on using the proposed guidelines.
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paper_title: Analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip RC extraction

paper_content:

Studies the effects of dummy-fills on the interconnect capacitance and the global planarity of chips in order to provide the design guideline of the dummy-fills. A simple but accurate full-chip RC extraction methodology taking the floating dummy-fills into account is proposed and applied to the analysis of changes in capacitance and signal delay of the global interconnects, for the first time. The results for 0.18 /spl mu/m designs clearly demonstrate the importance of considering floating dummy-fills in the interconnect modeling and the full-chip RC extraction.
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paper_title: A statistical method for fast and accurate capacitance extraction in the presence of floating dummy fills

paper_content:

Dummy fills are being extensively used to enhance CMP planarity. However presence of these fills can have a significant impact on the values of interconnect capacitances. Accurate capacitance extraction accounting for these dummies is CPU intensive and cumbersome. For one, there are typically hundreds to thousands of dummy fills in a small layout region, which stress the general purpose capacitance extractor. Second, since these dummy fills are not introduced by the designers, it is of no interest for them to see the capacitances to dummy fills in the extraction reports; they are interested in equivalent capacitances associated with signal power and ground nets. Hence extracting equivalent capacitances across nets of interest in the presence of large number of dummy fills is an important and challenging problem. We present a novel extension to the widely popular Monte-Carlo capacitance extraction technique. Our extension handles the dummy fills efficiently. We demonstrate the accuracy and scalability of our approach by two methods: (i) classical and golden technique of finding equivalent interconnect capacitances by eliminating dummy fills through the network reduction method and (ii) comparing extracted capacitances with measurement data from a test chip.
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paper_title: An exhaustive method for characterizing the interconnect capacitance considering the floating dummy-fills by employing an efficient field solving algorithm

paper_content:

This paper presents an exhaustive method to characterize the interconnect capacitances while taking the floating dummy-fills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is implemented into the 3D finite-difference solver and its computational efficiency is compared with the industry-standard RAPHAEL. Furthermore, the overall flow for extracting the parasitic capacitance considering the dummy-fills at the full-chip level is discussed and the underlying assumption is examined.
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paper_title: Filling algorithms and analyses for layout density control

paper_content:

In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout. To date, only foundries and special mask data processing tools perform layout post-processing for density control. In the future, better convergence of performance verification flows will depend on such layout manipulations being embedded within the layout synthesis (place-and-route) flow. In this paper, we give the first realistic formulation of the filling problem that arises in layout optimization for manufacturability. Our formulation seeks to add features to a given process layer, such that (1) feature area densities satisfy prescribed upper and lower bounds in all windows of given size and (2) the maximum variation of such densities over all possible window positions in the layout is minimized. We present efficient algorithms for density analysis, notably a multilevel approach that affords user-tunable accuracy. We also develop exact solutions to the problem of fill synthesis, based on a linear programming approach. These include a linear programming (LP) formulation for the fixed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout) and an LP formulation that is automatically generated by our multilevel density analysis. We briefly review criteria for fill pattern synthesis, and the paper then concludes with computational results and directions for future research.
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paper_title: Optimized pattern fill process for improved CMP uniformity and interconnect capacitance

paper_content:

In multilevel IC manufacturing, it's important to have a planar surface preceding the next layer to avoid topographical margin issues. To achieve the local, as well as global, planarity of the wafer surface many innovative technologies have been developed. The development of Chemical-Mechanical Polishing (CMP) has led to dramatic improvement in planarity of dielectrics and later in the development of planar plug-fill and dual damascene copper metallization. It is well known that CMP causes dishing of a layer to be planarized due to uneven distribution of device structures and thus reducing the effectiveness of this technology. One of the solutions for this dishing phenomenon has been the introduction of pattern fill methodology to improve the planarity of a given layer. However, dummy pattern adds capacitive load and thus, parasitic effects on both analog and digital circuits. In this paper a unique fill methodology is presented that reduces the impact on parasitic capacitance while improving the dielectric planarity through the use of irregularly shaped fill features and restrictions to placement of these features.
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paper_title: Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion

paper_content:

Inserting metal fill to improve inter-level dielectric thickness planarity is an essential part of the modern design process. However, the inserted fill shapes impact the performance of signal interconnect by increasing capacitance. In this paper, we analyze and model the impact of the metal dummy on the signal capacitance with various parameters including their electrical characteristic, signal dimensions, and dummy shape and dimensions. Fill has differing impact on interconnects depending on whether the signal of interest is in the same layer as the fill or not. In particular intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has more impact on the ground capacitance component. Based on an analysis of fill impact on capacitance, we propose simple capacitance increment models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider the realistic case with both signals and metal fill in adjacent layers, we apply a weighting function approach in the ground capacitance model. We verify this model using simple test patterns and benchmark circuits and find that the models match well with field solver results (1.2% average error with much faster runtime than commercial extraction tools, the runtime overhead reduced by ~75% for all benchmark circuits).
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paper_title: Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method

paper_content:

Inserting dummy (area fill) metals is necessary to reduce the pattern-dependent variation of dielectric thickness in the chemical-mechanical polishing (CMP) process. Such floating dummy metals affect interconnect capacitance and, therefore, signal delay and crosstalk significantly. To take the floating dummies into account, an efficient method for three-dimensional (3-D) capacitance extraction based on boundary element method is proposed. By introducing a floating condition into the direct boundary integral equation (BIE) and adopting an efficient preconditioning technique, and the quasi-multiple medium (QMM) acceleration, the method achieves very high computational speed. For some typical structures of area fill, the presented algorithm has shown over 1000/spl times/ speedup over the industry-standard Raphael while preserving high accuracy. Compared with the recently proposed PASCAL in the work of Park et al. (2000), the proposed method also has about ten times speedup. Since the dummies are not regarded as normal electrodes in capacitance extraction, the proposed method is much more efficient than the conventional method, especially in cases with a large number of floating dummies.
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paper_title: A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances

paper_content:

Metal fills, which are used to reduce metal thickness variations due to chemical-mechanical polishing (CMP), increase the capacitances in a circuit. Although current extraction tools are accurate in handling grounded fills and regular interconnects, for floating fills, these tools are based on certain approximations, such as assuming that floating fills are grounded or each fill is merged with neighboring ones. To reduce such inaccuracies, the authors provide a design of experiments (DOE), which will be used in addition to what is available in the extraction tools for regular interconnects. Through the proposed DOE set, a design or mask house can generate normalized fill tables to remove the inaccuracies of the extraction tools in the presence of floating fills. The capacitance values are updated using these normalized fill tables. The proposed DOE enables extensive analyses of the fill impacts on coupling capacitances. The authors show through extensive 3D field solver simulations that the assumptions used in extractors result in significant inaccuracies. The authors present analyses of fill impacts for an example technology, and also provide analyses using the normalized fill tables to be used in the extraction flow for three different standard fill algorithms
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paper_title: Efficient capacitance extraction method for interconnects with dummy fills

paper_content:

The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.
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paper_title: Variability-driven considerations in the design of integrated-circuit global interconnects

paper_content:

A torch with a turbulized supply of a plasma forming gas comprises an electrode having a high-melting insert and a flat end face, and a nozzle with an internal surface having two mated portions: one cylindrical and one tapering; and the diameter of the electrode flat end face amounts essentially to 0.4-0.5 diameter of the electrode proper and the radius of conjugation of the nozzle cylindrical and tapering portions is equal essentially to the length of its cylindrical portion. Due to such a design, the inventive torch features a long service life of both the electrode and the nozzle.
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paper_title: Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation

paper_content:

Abstract—This paper presents extensions of the dynamicprogramming (DP) framework to consider buffer insertion and wire-sizing under effects of process variation. We study the effectiveness of this approach to reduce timing impact caused by chemical–mechanical planarization (CMP)-induced systematic variation and random Leff process variation in devices. We first present a quantitative study on the impact of CMP to interconnect parasitics. We then introduce a simple extension to handle CMP effects in the buffer insertion and wire sizing problem by simultaneously considering fill insertion (SBWF).We also tackle the same problem but with random Leff process variation (vSBWF) by incorporating statistical timing into the DP framework. We develop an efficient yet accurate heuristic pruning rule to approximate the computationally expensive statistical problem. Experiments under conservative assumption on process variation show that SBWF algorithm obtains 1.6% timing improvement over the variationunaware solution. Moreover, our statistical vSBWF algorithm results in 43.1% yield improvement on average. We also show that our approaches have polynomial time complexity with respect to the net-size. The proposed extensions on the DP framework is orthogonal to other power/area-constrained problems under the same framework, which has been extensively studied in the literature.
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paper_title: The Emerging JBIG2 Standard

paper_content:

The Joint Bi-Level Image Experts Group (JBIG), an international study group affiliated with ISO/IEC and ITU-T, is in the process of drafting a new standard for lossy and lossless compression of bilevel images. The new standard, informally referred to as JBIG2, will support model-based coding for text and halftones to permit compression ratios up to three times those of existing standards for lossless compression. JBIG2 will also permit lossy preprocessing without specifying how it is to be done, In this case, compression ratios up to eight times those of existing standards may be obtained with imperceptible loss of quality. It is expected that JBIG2 will become an international standard by 2000.
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paper_title: Compressible area fill synthesis

paper_content:

Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low-k dielectrics. To improve manufacturability, and in particular to enable more uniform chemical-mechanical planarization (CMP), it is necessary to insert area fill features into low-density layout regions. Because area fill feature sizes are very small compared to the large empty layout areas that need to be filled, the filling process can increase the size of the resulting layout data file by an order of magnitude or more. To reduce file transfer times, and to accommodate future maskless lithography regimes, data compression becomes a significant requirement for fill synthesis. In this paper, we make the following contributions. First, we define two complementary strategies for fill data volume reduction corresponding to two different points in the design-to-manufacturing flow: compressible filling and post-fill compression . Second, we compare compressible filling methods in the fixed-dissection regime when two different sets of compression operators are used: the traditional GDSII array reference (AREF) construct, and the new Open Artwork System Interchange Standard (OASIS) repetitions. We apply greedy techniques to find practical compressible filling solutions and compare them with optimal integer linear programming solutions. Third, for the post-fill data compression problem, we propose two greedy heuristics, an exhaustive search-based method, and a smart spatial regularity search technique. We utilize an optimal bipartite matching algorithm to apply OASIS repetition operators to irregular fill patterns. Our experimental results indicate that both fill data compression methodologies can achieve significant data compression ratios, and that they outperform industry tools such as Calibre V8.8 from Mentor Graphics. Our experiments also highlight the advantages of the new OASIS compression operators over the GDSII AREF construct.
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paper_title: Filling and slotting: analysis and algorithms

paper_content:

In very deep-submicron VLSI, certain manufacturing steps &mdash notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)&mdash have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future place-and-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.
---
paper_title: Filling algorithms and analyses for layout density control

paper_content:

In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout. To date, only foundries and special mask data processing tools perform layout post-processing for density control. In the future, better convergence of performance verification flows will depend on such layout manipulations being embedded within the layout synthesis (place-and-route) flow. In this paper, we give the first realistic formulation of the filling problem that arises in layout optimization for manufacturability. Our formulation seeks to add features to a given process layer, such that (1) feature area densities satisfy prescribed upper and lower bounds in all windows of given size and (2) the maximum variation of such densities over all possible window positions in the layout is minimized. We present efficient algorithms for density analysis, notably a multilevel approach that affords user-tunable accuracy. We also develop exact solutions to the problem of fill synthesis, based on a linear programming approach. These include a linear programming (LP) formulation for the fixed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout) and an LP formulation that is automatically generated by our multilevel density analysis. We briefly review criteria for fill pattern synthesis, and the paper then concludes with computational results and directions for future research.
---
paper_title: Is your layout density verification exact?: a fast exact algorithm for density calculation

paper_content:

As the device shapes keep shrinking, the designs are more sensitive to manufacturing processes. In order to improve performance predictability and yield, mask layout uniformity/evenness is highly desired, and it is usually measured by the feature density with defined feasible range in manufacture process design rules. To address the density control problem, one fundamental problem is how to calculate density accurately and efficiently. In this paper, we propose a fast exact algorithm to identify the maximum density for a given layout. Compared with the existing exact algorithms, our algorithm reduces the running time from days/hours to a few minutes/seconds. And it is even faster than the existing approximate algorithms in literature.
---
paper_title: Filling and slotting: analysis and algorithms

paper_content:

In very deep-submicron VLSI, certain manufacturing steps &mdash notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)&mdash have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future place-and-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.
---
paper_title: Comments on "Filling algorithms and analyses for layout density control"

paper_content:

Theorem 2 of the title paper (A.B. Kahng et al., ibid. vol. 18, pp.445-462, 1999) presents layout density bounds for any fixed r-dissection w-by-w window given the layout density of at least L and at most U for all w-by-w windows whose bottom left corners are at points (i(w/r), j(w/r)), i, j=0, 1, ..., r((n/w)-1) on an n-by-n layout plane. However, the bounds are not tight for certain combinations of U (L) and r. Here, the authors present an approach to obtaining the tight lower and upper bounds for all possible combinations of U (L) and r.
---
paper_title: New and exact filling algorithms for layout density control

paper_content:

To reduce manufacturing variation due to chemical-mechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add fill geometries, either at the foundry or, for better convergence of performance verification flows, during layout synthesis. This paper proposes a new min-variation objective for the synthesis of fill geometries. Within the so-called fixed dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for fill pattern synthesis, and discuss additional criteria that apply when fill, must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.
---
paper_title: Filling and slotting: analysis and algorithms

paper_content:

In very deep-submicron VLSI, certain manufacturing steps &mdash notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)&mdash have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future place-and-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.
---
paper_title: New multilevel and hierarchical algorithms for layout density control

paper_content:

Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing (CIMP) which has varying effects on device and interconnect features, depending on local layout characteristics. To reduce manufacturing variation due to CMP and to improve yield and performance predictability, the layout needs to be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout. This paper presents an efficient multilevel approach to density analysis that affords user-tunable accuracy. We also develop exact fill synthesis solutions based on combining multilevel analysis with a linear programming approach. Our methods apply to both flat and hierarchical designs.
---
paper_title: Nanotopography Issues in Shallow Trench Isolation CMP

paper_content:

As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical-mechanical planarization (CMP). Previous work has shown that nanotopography-small surface-height variations of 10-100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers-can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies.
---
paper_title: New and exact filling algorithms for layout density control

paper_content:

To reduce manufacturing variation due to chemical-mechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add fill geometries, either at the foundry or, for better convergence of performance verification flows, during layout synthesis. This paper proposes a new min-variation objective for the synthesis of fill geometries. Within the so-called fixed dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for fill pattern synthesis, and discuss additional criteria that apply when fill, must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.
---
paper_title: Computational Geometry: An Introduction

paper_content:

From the reviews: "This book offers a coherent treatment, at the graduate textbook level, of the field that has come to be known in the last decade or so as computational geometry...The book is well organized and lucidly written; a timely contribution by two founders of the field. It clearly demonstrates that computational geometry in the plane is now a fairly well-understood branch of computer science and mathematics. It also points the way to the solution of the more challenging problems in dimensions higher than two."
---
paper_title: Dummy Feature Placement for Oxide Chemical-mechanical PolishingManufacturability

paper_content:

CChemical-mechanical polishing (CMP) is a technique used in very deep-submicron VLSI manufacturing to achieve uniformity in long range oxide planarization. Post-CNIP topography is highly related to local spatial pattern density in layout. To change local pattern density, and thus ensure post-CMP planarization, dummy features are placed in layout. The only known previously published algorithm for dummy feature placement is based oil a very simple and inadequate model. This paper is based on a closed-form analytical model for inter-level dielectric thickness in CMP process by B. Stine et al. and a model for effective local layout pattern density by D. Ouma et al. Those two models accurately describe the relation between local pattern density and post-CMP planarization. This paper uses those two models to solve the dummy feature placement problem of a single layer in the fixed-dissection regime. An experiment, conducted with real industry design data, gives excellent results by reducing post-CMP topography variation from 753A to 169A.
---
paper_title: Filling algorithms and analyses for layout density control

paper_content:

In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout. To date, only foundries and special mask data processing tools perform layout post-processing for density control. In the future, better convergence of performance verification flows will depend on such layout manipulations being embedded within the layout synthesis (place-and-route) flow. In this paper, we give the first realistic formulation of the filling problem that arises in layout optimization for manufacturability. Our formulation seeks to add features to a given process layer, such that (1) feature area densities satisfy prescribed upper and lower bounds in all windows of given size and (2) the maximum variation of such densities over all possible window positions in the layout is minimized. We present efficient algorithms for density analysis, notably a multilevel approach that affords user-tunable accuracy. We also develop exact solutions to the problem of fill synthesis, based on a linear programming approach. These include a linear programming (LP) formulation for the fixed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout) and an LP formulation that is automatically generated by our multilevel density analysis. We briefly review criteria for fill pattern synthesis, and the paper then concludes with computational results and directions for future research.
---
paper_title: Monte-Carlo algorithms for layout density control

paper_content:

Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local characteristics of the layout. To enhance manufacturability and performance predictability, we seek to make the layout uniform with respect to prescribed density criteria, by inserting "fill" geometries into the layout. We propose several new Monte-Carlo based filling methods with fast dynamic data structures and report the tradeoff between runtime and accuracy for the suggested methods. Compared to existing linear programming based approaches, our Monte-Carlo methods seem very promising as they produce nearly-optimal solutions within reasonable runtimes.
---
paper_title: Practical iterated fill synthesis for CMP uniformity

paper_content:

We propose practical iterated methods for layout density control for CMP uniformity, based on linear programming, Monte-Carlo and greedy algorithms. We experimentally study the tradeoffs between two main filling objectives: minimizing density variation, and minimizing the total amount of inserted fill. Comparisons with previous filling methods show the advantages of our new iterated Monte-Carlo and iterated greedy methods. We achieve near-optimal filling with respect to each of the objectives and for both density models ( spatial density [3] and effective density [8]). Our new methods are more efficient in practice than linear programming [3] and more accurate than non-iterated Monte-Carlo approaches [1].
---
paper_title: Hierarchical dummy fill for process uniformity

paper_content:

To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting "fill" geometries into the layout. Previous approaches for flat layout density control are not scalable due to the necessity of solving very large linear programs, the large data volume of the solution, and the impact of hierarchy-breaking on verification. In this paper, we give the first methods for hierarchical layout density control for process uniformity. Our approach trades off naturally between runtime, solution quality, and output data volume. We also allow generation of compressed GDSII of fill geometries. Our experiments show that this hybrid hierarchical filling approach saves data volume and is scalable, while yielding solution quality that is competitive with existing Monte-Carlo and linear programming based approaches.
---
paper_title: Performance-impact limited area fill synthesis

paper_content:

Chemical-mechanical planarization (CMP) and other manufacturing steps in every deep-submicron VLSI have varying effects on device and interconnect features, depending on the local density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PIL-Fill) problem with the objective of either minimizing total delay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. For the MSFC PIL-Fill problem, we describe an iterated greedy method that integrates call to an industry static timing analysis tool. We test our methods on layout testcases obtained from industry. Compared with the normal fill method according to Y. Chen et al.(2002), our ILP-II method for MDFC PIL-Fill problem achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact while maintaining ideal quality of the layout density control and our iterated greedy method for MSFC PIL-II problem also shows significant advantage with respect to the minimum slack of nets on post-fill layout.
---
paper_title: Dummy fill density analysis with coupling constraints

paper_content:

In modern VLSI manufacturing processes, dummy fills are widely used to adjust local metal density in order to improve layout uniformity and yield optimization. However, the introduction of a large amount of dummy features also affects wire electrical properties. In this paper, we propose the first Coupling constrained Dummy Fill (CDF) analysis algorithm which identifies feasible locations for dummy fills such that the fill induced coupling capacitance can be bounded within the given coupling threshold of each wire segment. The algorithm also makes efforts to maximize ground dummy fills, which are more robust and predictable. The output of the algorithm can be treated as the upper bound for dummy fill insertion, and it can be easily adopted in density models to guide dummy fill insertion without disturbing the existing design.
---
paper_title: Energy-Minimization Model for Fill Synthesis

paper_content:

Although fill allocation methods to enable reduced metal height variations and manually applicable design guidelines to reduce coupling capacitances are available, the synthesis of fills according to these allocations or guidelines is not well automated. Current fill insertion algorithms mostly use simple mask operations, which fail to enable the implementation of complex design guidelines. The proposed fill synthesis model not only enables implementation of such guidelines, but is also suitable for insertion of standard fill patterns. The proposed novel model has an intricate analogy to the electrons filling the orbits of an atom. Through the proposed method, the task of designing an optimal fill configuration is carried to the CAD tool designer in terms of designing a suitable energy network or rules, albeit in an easier way through provided insights and models
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paper_title: SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill

paper_content:

This paper presents SPIDER, a novel methodology that advantageously utilizes metal fill to simultaneously fulfil metal density requirements and reduce IR-drop of the power distribution network. This is achieved through the addition of partially redundant connections between metal fills and power meshes. Our technique is especially significant for 90nm process technology or below because (1) metal fill must now be done as part of the IC implementation flow due to its increasing impact on timing, (2) the tolerance for IR drop is tightening due to voltage scaling, and the increasingly conservative power mesh design to address IR-drop is adding significant burden on the available routing resources, (3) IR-drop is getting worse due to increasing design sizes, and (4) the large degree of design uncertainty demands IRdrop repair capabilities that can be applied after routing is completed. SPIDER addresses all these issues practically with little or no cost. Experimental results further demonstrated the robustness and effectiveness of our approach: SPIDER achieves an average IR-drop reduction of 62.2% in 16 designs of various sizes.
---
paper_title: Fill for shallow trench isolation CMP

paper_content:

Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical polishing (CMP) to remove excess of deposited oxide and attain a planar surface for successive process steps. Despite advances in STI CMP technology, pattern dependencies cause large post-CMP topography variation that can result in functional and parametric yield loss. Fill insertion is used to reduce pattern variation and consequently decrease post-CMP topography variation. Traditional fill insertion is rulebased and is used with reverse etchback to attain desired planarization quality. Due to extra costs associated with reverse etchback, "single-step" STI CMP in which fill insertion suffices is desirable. To alleviate the failures caused by imperfect CMP, we focus on two objectives for fill insertion: oxide density variation minimization and nitride density maximization. A linear programming based optimization is used to calculate oxide densities that minimize oxide density variation. Next a fill insertion methodology is presented that attains the calculated oxide density while maximizing the nitride density. Averaged over the two large testcases, the oxide density variation is reduced by 63% and minimum nitride density increased by 79% compared to tiling-based fill insertion. To assess post-CMP planarization, we run CMP simulation on the layout filled with our approach and find the planarization window (time window in which polishing can be stopped) to increase by 17% and maximum final step height (maximum difference in post-CMP oxide thickness) to decrease by 9%.
---
paper_title: Modeling of chemical mechanical polishing for shallow trench isolation

paper_content:

Chemical mechanical polishing (CMP) is a key process enabling shallow trench isolation (STI), which is used in current integrated circuit manufacturing processes to achieve device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This thesis proposes characterization and modeling techniques to address a variety of concerns in STI CMP. Three major contributions of this work are: characterization and modeling of STI CMP processes, both conventional and nonconventional; layout optimization to reduce pattern-dependent dishing and erosion; and modeling of wafer nanotopography impact on STI CMP yield. An STI CMP characterization method is combined with a chip-scale pattern-dependent model to create a methodology that enables tuning of STI CMP process models and prediction of post-CMP dishing, erosion, and clearing times on arbitrary layouts. Model extensions enable characterization of STI CMP processes that use nonconventional consumable sets, including fixed abrasive pads and high-selectivity silica-based and ceria-based slurries. Experimental data validates the accuracy of the model for both conventional and nonconventional processes. Layout optimization techniques are developed that reduce pattern-density dependent dishing and erosion. Layout design modification is achieved through the use of dummy STI active areas and selective reverse etchback structures. Smart algorithms allow for optimal density distributions across the layout. The effect of wafer nanotopography (height variations that exist on unpatterned silicon wafers) is explored, characterized, and modelled. A diagnostic tool for examining the impact of nanotopography on STI device yields is developed, based on contact wear modeling. An aggregate estimator for the combined effect of wafer-scale nanotopography and chip-scale pattern-dependent dishing and erosion is developed. The techniques developed in this thesis can be used both for process optimization and for diagnosis and correction of potential problems due to layout, wafer and CMP process interaction. The characterization and modeling methods create a comprehensive set of tools for process characterization and post-CMP erosion and dishing prediction in STI processes. Thesis Supervisor: Duane S. Boning Title: Associate Professor of Electrical Engineering and Computer Science
---
paper_title: Fill for shallow trench isolation CMP

paper_content:

Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical polishing (CMP) to remove excess of deposited oxide and attain a planar surface for successive process steps. Despite advances in STI CMP technology, pattern dependencies cause large post-CMP topography variation that can result in functional and parametric yield loss. Fill insertion is used to reduce pattern variation and consequently decrease post-CMP topography variation. Traditional fill insertion is rulebased and is used with reverse etchback to attain desired planarization quality. Due to extra costs associated with reverse etchback, "single-step" STI CMP in which fill insertion suffices is desirable. To alleviate the failures caused by imperfect CMP, we focus on two objectives for fill insertion: oxide density variation minimization and nitride density maximization. A linear programming based optimization is used to calculate oxide densities that minimize oxide density variation. Next a fill insertion methodology is presented that attains the calculated oxide density while maximizing the nitride density. Averaged over the two large testcases, the oxide density variation is reduced by 63% and minimum nitride density increased by 79% compared to tiling-based fill insertion. To assess post-CMP planarization, we run CMP simulation on the layout filled with our approach and find the planarization window (time window in which polishing can be stopped) to increase by 17% and maximum final step height (maximum difference in post-CMP oxide thickness) to decrease by 9%.
---
paper_title: Characterizing STI CMP Processes with an STI Test Mask Having Realistic Geometric Shapes

paper_content:

Chemical mechanical polishing (CMP) has become the enabling planarization method for shallow trench isolation (STI) of sub 0.25µm technology. CMP is able to reduce topography over longer lateral distances than earlier techniques; however, CMP still suffers from pattern dependencies that result in large variation in the post-polish profile across a chip. In the STI process, insufficient polish will leave residue nitride and cause device failure, while excess dishing and erosion degrade device performance. Our group has proposed several chip-scale CMP pattern density models [1], and a methodology using designed dielectric CMP test mask to characterize CMP processes [2]. The methodology has proven helpful in understanding STI CMP; however, it has several limitations as the existing test mask primarily consists of arrays of lines and spaces of large feature size varying from 10 to 100 µm. In this paper, we present a new STI characterization mask, which consists of various rectangular, L-shape, and X-shape structures of feature sizes down to submicron. The mask is designed to study advanced STI CMP processes better, as it is more representative of real STI structures. The small feature size amplifies the effects of edge acceleration and oxide deposition bias, and thus enables us to study their impact better. Experimental data from an STI CMP process is shown to verify the methodology, and these secondary effects are explored. The new mask and data guide ongoing development of improved pattern dependent STI CMP models.
---
paper_title: Nanotopography Issues in Shallow Trench Isolation CMP

paper_content:

As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical-mechanical planarization (CMP). Previous work has shown that nanotopography-small surface-height variations of 10-100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers-can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies.
---
paper_title: Planarization And Integration Of Shallow Trench Isolation

paper_content:

STI process flow and planarization requirements are reviewed. An STI planarization mask was designed and utilized for test wafer patterning to investigate STI CMP planarization. Test wafers were processed through a typical STI process sequence, including trench etch, trench liner oxidation, trench-fill, and CMP. Two different CVD techniques, ozone TEOS thermal CVD and HDPCVD, were investigated for trench-fill. CMP experiments were carried out with different process parameters and consumables. Extensive CMP characterization was carried out utilizing multiple metrology techniques. The results fit the previously reported “CMP dielectric planarization” model [1, 2] quite well.
---
paper_title: New and exact filling algorithms for layout density control

paper_content:

To reduce manufacturing variation due to chemical-mechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add fill geometries, either at the foundry or, for better convergence of performance verification flows, during layout synthesis. This paper proposes a new min-variation objective for the synthesis of fill geometries. Within the so-called fixed dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for fill pattern synthesis, and discuss additional criteria that apply when fill, must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.
---
paper_title: Fill for shallow trench isolation CMP

paper_content:

Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical polishing (CMP) to remove excess of deposited oxide and attain a planar surface for successive process steps. Despite advances in STI CMP technology, pattern dependencies cause large post-CMP topography variation that can result in functional and parametric yield loss. Fill insertion is used to reduce pattern variation and consequently decrease post-CMP topography variation. Traditional fill insertion is rulebased and is used with reverse etchback to attain desired planarization quality. Due to extra costs associated with reverse etchback, "single-step" STI CMP in which fill insertion suffices is desirable. To alleviate the failures caused by imperfect CMP, we focus on two objectives for fill insertion: oxide density variation minimization and nitride density maximization. A linear programming based optimization is used to calculate oxide densities that minimize oxide density variation. Next a fill insertion methodology is presented that attains the calculated oxide density while maximizing the nitride density. Averaged over the two large testcases, the oxide density variation is reduced by 63% and minimum nitride density increased by 79% compared to tiling-based fill insertion. To assess post-CMP planarization, we run CMP simulation on the layout filled with our approach and find the planarization window (time window in which polishing can be stopped) to increase by 17% and maximum final step height (maximum difference in post-CMP oxide thickness) to decrease by 9%.
---
paper_title: Filling algorithms and analyses for layout density control

paper_content:

In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout. To date, only foundries and special mask data processing tools perform layout post-processing for density control. In the future, better convergence of performance verification flows will depend on such layout manipulations being embedded within the layout synthesis (place-and-route) flow. In this paper, we give the first realistic formulation of the filling problem that arises in layout optimization for manufacturability. Our formulation seeks to add features to a given process layer, such that (1) feature area densities satisfy prescribed upper and lower bounds in all windows of given size and (2) the maximum variation of such densities over all possible window positions in the layout is minimized. We present efficient algorithms for density analysis, notably a multilevel approach that affords user-tunable accuracy. We also develop exact solutions to the problem of fill synthesis, based on a linear programming approach. These include a linear programming (LP) formulation for the fixed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout) and an LP formulation that is automatically generated by our multilevel density analysis. We briefly review criteria for fill pattern synthesis, and the paper then concludes with computational results and directions for future research.
---
paper_title: Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process

paper_content:

Manufacturability of a design that is processed with shallow trench isolation (STI) depends on the uniformity of the chemical-mechanical polishing (CMP) step in STI. The CMP step in STI is a dual-material polish, for which all previous studies on dummy feature placement for single-material polish [3, 11, 1] are not applicable. Based on recent semi-physical models of polish pad bending [5], local polish pad compression [2, 10], and different polish rates for materials present in a dual-material polish [2, 13], this paper derives a time-dependent relation between post-CMP topography and layout pattern density for CMP in STI. Using the dependencies derived, the first formulation of dummy feature placement for CMP in STI is given as a nonlinear programming problem. An iterative approach is proposed to solve the dummy feature placement problem. Computational experience on four layouts from Motorola is given.
---
paper_title: A novel CBCM method free from charge injection induced errors: investigation into the impact of floating dummy-fills on interconnect capacitance

paper_content:

Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance measurement), a novel CBCM method free from the errors induced by charge-injection is developed. This is used for the first time to investigate the impact of floating dummy-fills on interconnect capacitance, in practice. The impact of floating dummy-fills is confirmed to play an important role on successful circuit design. Besides, a guideline to optimize the chip performance and minimize the crosstalk by dummy pattern design is also proposed in this paper.
---
paper_title: Performance-impact limited area fill synthesis

paper_content:

Chemical-mechanical planarization (CMP) and other manufacturing steps in every deep-submicron VLSI have varying effects on device and interconnect features, depending on the local density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PIL-Fill) problem with the objective of either minimizing total delay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. For the MSFC PIL-Fill problem, we describe an iterated greedy method that integrates call to an industry static timing analysis tool. We test our methods on layout testcases obtained from industry. Compared with the normal fill method according to Y. Chen et al.(2002), our ILP-II method for MDFC PIL-Fill problem achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact while maintaining ideal quality of the layout density control and our iterated greedy method for MSFC PIL-II problem also shows significant advantage with respect to the minimum slack of nets on post-fill layout.
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paper_title: Intelligent Fill Pattern and Extraction Methodology for SoC

paper_content:

Uniform pattern density of physical layers of the die, such as diffusion, poly, or metals, has significant impact on electrical parameters of the product. At active level, variations in pattern density across the die translate into wide distributions of punch-through or breakdown voltages. At poly and metal levels, a non-uniform pattern density would result in poor planarity and give rise to high via resistances and poor control of the inter-layer capacitive coupling. However, at design stage, the complex functions of SoC functional blocks do not give designers enough freedom to strictly observe a predefined set of pattern density rules. Instead, the die pattern has to be made more uniform at die integration level, by global addition of fill features (waffles). While conceptually simple, this presents significant technical challenge, as the criteria for this addition are often difficult to meet. The simple but time consuming way of making pattern density uniform is based on manual drawing of dummy features over the electrical database (intellectual property, IP) of the die. A simplistic, automated approach is to add fill pattern of fixed density until it becomes close to target pattern density of the die. However, it may not be possible to equalize out all the regions even with changes in the die architecture. In addition, this approach tends to add dummy features even if unnecessary, driving towards very high pattern density. This solution is disadvantageous for RF/analog products the performance of which can be compromised by the capacitive coupling through the waffles. The methodology proposed that the initial die pattern density is first evaluated followed by the adjustable, intelligent fill of dynamic density at the block level. This way, it is possible to keep the original pattern density and work only on the areas of small density. The authors propose that the standard cell methodology should enable pre-die level modifications of pattern density and its extraction, to ensure that all the required blocks could be placed on the product and that their parasitics are properly extracted
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Title: CMP Fill Synthesis: A Survey of Recent Studies

Section 1: INTRODUCTION
Description 1: Introduce the concept of Chemical-Mechanical Polishing (CMP), its significance in planarization, and the challenges it addresses in modern lithography processes.

Section 2: CMP FILL TAXONOMY, BENEFITS, AND TRADEOFFS
Description 2: Discuss the taxonomy of CMP fills, their benefits, tradeoffs, and different approaches like grounded versus floating fills and their impacts on resistance and capacitance (RC) parasitics.

Section 3: LAYOUT DENSITY-ANALYSIS METHODS
Description 3: Review methods for analyzing layout density, both fixed and continuous dissections, and their implications for density uniformity in CMP processes.

Section 4: CHARACTERIZATION AND MODELING APPROACHES FOR BACK-END-OF-LINE (BEOL) CMP PROCESSES AND CORRESPONDING FILL SYNTHESIS APPROACHES
Description 4: Explore various methods for characterizing and modeling BEOL CMP processes as well as different fill-synthesis methodologies, along with their problem formulations and solutions.

Section 5: CHARACTERIZATION AND MODELING TECHNIQUES FOR FRONT-END-OF-LINE (FEOL) CMP PROCESSES AND SHALLOW-TRENCH-ISOLATION (STI) FILL-INSERTION PROBLEM
Description 5: Explain techniques used for FEOL CMP characterization and modeling, specifically focusing on the STI fill-insertion problems and their impact on manufacturing processes.

Section 6: DESIGN-DRIVEN FILL SYNTHESIS
Description 6: Introduce the concept of design-driven fill synthesis, highlighting how it attempts to optimize CMP fill insertion by considering design performance and density constraints.

Section 7: SUMMARY AND FUTURE CMP-FILL-SYNTHESIS FLOWS
Description 7: Provide a summary of the survey and discuss potential future directions for CMP fill synthesis methods, including integration with CMP simulation, RC extraction, and multilayer fill synthesis.