Flash memory cells—An overview
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paper_title: Non Volatile Memories: Issues, Challenges and Trends for the 2000's Scenario

paper_content:

Main issues regarding actual Non Volatile Memory are presented, considering the market growth and the application requirements. The focus is on the evolution of the Flash memory technology, oriented to both reducing cell size and upgrading product functions. Flash will be the DRAM challenger in the next decade: the cost per bit and the performance improvements in term of access time and write transfer rate will be the main trends.
---
paper_title: Non Volatile Memories: Issues, Challenges and Trends for the 2000's Scenario

paper_content:

Main issues regarding actual Non Volatile Memory are presented, considering the market growth and the application requirements. The focus is on the evolution of the Flash memory technology, oriented to both reducing cell size and upgrading product functions. Flash will be the DRAM challenger in the next decade: the cost per bit and the performance improvements in term of access time and write transfer rate will be the main trends.
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paper_title: Hole and electron current transport in metal-oxide-nitride-oxide-silicon memory structures

paper_content:

The carrier transport properties in metal-oxide (top oxide) nitride-oxide (tunnel oxide) silicon (MONOS) memory structures have been investigated in steady-state conditions under negative gate bias voltage. Carriers were separated into holes and electrons utilizing an induced junction of the p-channel MONOS transistors. Two-carrier transport is confirmed in the structure at negative gate polarity. It is found that the relatively thick top oxide acts as a potential barrier to the holes injected from the Si into the thin nitride. It is also found that a portion of the electrons injected from the gate at negative gate polarity recombine with the holes injected from the Si even in such a thin nitride and/or at the top-oxide/nitride interface. >
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paper_title: New method for the extraction of the coupling ratios in FLOTOX EEPROM cells

paper_content:

A method for the extraction of the control gate and drain coupling ratios directly from FLOTOX EEPROM cells is proposed. The method is based on the dependence of the high state threshold voltage on the hold time of the write pulses. The principal advantages of the technique are its accuracy, simplicity, and rapidity, the fact that the so-called dummy cell is not required, and the fact that the coupling ratios obtained correspond to effective values which characterize the actual memory cell operation. >
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paper_title: Analysis of the subthreshold slope and the linear transconductance techniques for the extraction of the capacitance coupling coefficients of floating-gate devices

paper_content:

A critical investigation of the relationship between the floating gate and the accessible terminal voltages reveals that the gate coupling coefficient is overestimated by the traditional expressions obtained from the approximate analysis of the subthreshold slope and the linear transconductance techniques. The investigation further indicates that the subthreshold slope technique is preferred, because the corrections can be easily estimated using the results of auxiliary measurements involving the source and drain coupling coefficients. >
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paper_title: Limiting factors for programming EPROM of reduced dimensions

paper_content:

In order to realize high density EPROM's it is necessary to reduce the dimensions of EPROM cells. In this paper the programming characteristics of the floating gate EPROM's are discussed in relation to the limiting factors for device parameters and the programming conditions. Some problems which arise from the arrayed cell configuration are clarified. The programming speed of an EPROM is remarkably lowered by the voltage drop in a bit line due to an excess current flow through deselected cells which is induced by pulling up of the floating gate potential due to capacitance coupling between the bit line and the floating gate. A punch-through current in memory cells has the same effect on the programming characteristics. The feasibility of higher density EPROM's are also discussed by taking these problems into account.
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paper_title: Hole and electron current transport in metal-oxide-nitride-oxide-silicon memory structures

paper_content:

The carrier transport properties in metal-oxide (top oxide) nitride-oxide (tunnel oxide) silicon (MONOS) memory structures have been investigated in steady-state conditions under negative gate bias voltage. Carriers were separated into holes and electrons utilizing an induced junction of the p-channel MONOS transistors. Two-carrier transport is confirmed in the structure at negative gate polarity. It is found that the relatively thick top oxide acts as a potential barrier to the holes injected from the Si into the thin nitride. It is also found that a portion of the electrons injected from the gate at negative gate polarity recombine with the holes injected from the Si even in such a thin nitride and/or at the top-oxide/nitride interface. >
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paper_title: A new technique for determining the capacitive coupling coefficients in flash EPROMs

paper_content:

A method for determining the capacitive coupling coefficients of flash erasable programmable read only memories (EPROMs) is introduced. This technique relies on the Fowler-Nordheim erase measurements and source/drain junction leakage characteristics of the device to extract the control gate, source, and drain coupling coefficients. An advantage offered by this method is its use of an actual flash EPROM cell without requiring additional test structures. >
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paper_title: On the I-V characteristics of floating-gate MOS transistors

paper_content:

The effects of capacitive coupling on the I-V characteristics of floating-gate MOS transistors are described. A set of modified IV equations for these devices is presented and compared with experimental results.
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paper_title: Characterization and suppression of drain coupling in submicrometer EPROM cells

paper_content:

The EPROM transistor suffers from a capacitive-coupling-based short-channel effect called drain turn-on or V dto that limits the maximum drain voltage. Several measurement techniques are demonstrated to characterize the V dto effect. An analytical model is applied to the problem to estimate the effects of process variations to suppress the phenomenon. The effect of V dto on scaling is discussed, and circuit and device design techiques to reduce or eliminate this problem are discussed.
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paper_title: A novel method for the experimental determination of the coupling ratios in submicron EPROM and flash EEPROM cells

paper_content:

A novel method for evaluating the coupling ratios alpha /sub G/ and alpha /sub D/ of hot-electron programmable memory cells has been developed. The evaluation is based only on measurements performed on the cell and does not rely on the comparison of the cell with the equivalent MOS transistor. The sensitivity to slight differences between the two structures, which becomes more severe as the scaling-down continues, is thus eliminated. The method allows the coupling ratios to be determined also in those new high-density memory array designs in which it is impossible to obtain the equivalent transistor. The method has been validated on a 0.8 mu m technology EPROM and on a 1.0 mu m technology flash-EEPROM. >
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paper_title: Limiting factors for programming EPROM of reduced dimensions

paper_content:

In order to realize high density EPROM's it is necessary to reduce the dimensions of EPROM cells. In this paper the programming characteristics of the floating gate EPROM's are discussed in relation to the limiting factors for device parameters and the programming conditions. Some problems which arise from the arrayed cell configuration are clarified. The programming speed of an EPROM is remarkably lowered by the voltage drop in a bit line due to an excess current flow through deselected cells which is induced by pulling up of the floating gate potential due to capacitance coupling between the bit line and the floating gate. A punch-through current in memory cells has the same effect on the programming characteristics. The feasibility of higher density EPROM's are also discussed by taking these problems into account.
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paper_title: Hot-electron injection into the oxide in n-channel MOS devices

paper_content:

In recent years the interest in hot-electron injection currents in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses problems of trapping and local heating, allowing full characterization of parameter, voltage and temperature dependence down to gate current levels of 10-16A. Based on this characterization a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot-electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinch off region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.
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paper_title: Hot-electron emission in N-channel IGFET's

paper_content:

This paper discusses the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFET's. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.
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paper_title: Distribution Functions and Ionization Rates for Hot Electrons in Semiconductors

paper_content:

The distribution of electrons in a semiconductor at high electric field is governed by a Boltzmann equation which describes the effects of the field, the phonons, and the ionization processes on the electrons. This equation can be converted to an integral equation for the space and energy dependent collision density by performing the angular integrations. The integral equation is solved numerically to obtain alpha, the ionization rate per unit path length. The resulting alpha shows a dependence on field strength $\mathcal{E}$ which is roughly $\mathrm{exp}(\ensuremath{-}\frac{b}{\mathcal{E}})$ at low fields and $\mathrm{exp}(\ensuremath{-}\frac{c}{{\mathcal{E}}^{2}})$ at high fields, but there are significant differences from the earlier calculations of Wolff and Shockley. These differences result from the approximations used by the earlier workers to treat the angular dependence. We present graphs of $log\ensuremath{\alpha}$ vs ($\frac{1}{\mathcal{E}}$) for a wide range of material parameters. These graphs are useful in interpreting measurements of charge multiplication in terms of the properties of the material supporting the transport process.
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paper_title: Characterization of silicon-on-sapphire IGFET transistors

paper_content:

Under dynamic operation conditions, the potential of the floating substrate in a silicon-on-sapphire (SOS) device is primarily controlled by the capacitive coupling of the substrate to other device terminals. However, a key parameter that plays a major role in defining that potential during switching is the avalanche multiplication current produced by the channel current carriers in the surface space charge region adjacent to the drain. A closed form expression is derived for the avalanche current, enabling the development of a nonlinear equivalent circuit model of the device. Comparison of measurements with device terminal characteristics, as well as the switching behavior of the device, shows good agreement.
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paper_title: Correlation between substrate and gate currents in MOSFET's

paper_content:

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.
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paper_title: Photoinjection into SiO2: Electron Scattering in the Image Force Potential Well

paper_content:

The voltage dependence of photoinjected currents in SiO2 films for electric fields less than about 106 V/cm exhibits anomalous behavior. It is shown that the physical mechanism responsible for this behavior is the scattering of photoinjected electrons in the SiO2 image force potential well between the emitter and the potential maximum. A previously published model attributing the effect to electron trapping in SiO2 is shown to be inconsistent with the experimental results. A theoretical model is presented and the voltage dependence of photocurrents is derived including the effects of scattering and barrier lowering. Experimental results from MIS structures using thermally grown SiO2 are found to be in excellent agreement with theoretical predictions when a 34 A mean free path for scattering in SiO2 is used in the model.
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paper_title: Hot-electron injection into the oxide in n-channel MOS devices

paper_content:

In recent years the interest in hot-electron injection currents in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses problems of trapping and local heating, allowing full characterization of parameter, voltage and temperature dependence down to gate current levels of 10-16A. Based on this characterization a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot-electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinch off region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.
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paper_title: Hot-electron emission in N-channel IGFET's

paper_content:

This paper discusses the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFET's. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.
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paper_title: Oxide-field dependence of electron injection from silicon into silicon dioxide

paper_content:

The problem of electron injection from silicon into silicon dioxide is considered by means of a physical approach based on a simple model that provides good agreement with experimental data for MOS structures. The model implements the calculation of the electron energy distribution at the Si-SiO/sub 2/ interface by means of an efficient nonlocal algorithm, thus making possible a consistent treatment of the tunneling of hot electrons across the oxide. The oxide-field dependence of electron injection is addressed and the relationship between barrier lowering and electron energy distributions is discussed. >
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paper_title: Hot carriers in silicon surface inversion layers

paper_content:

Calculations of the carrier mobility of electrons and holes vs the electrical field strength E are presented. The calculations have been performed based on a Maxwellian distribution and taking into account a repopulation of carriers among different valleys in the case of n‐channel silicon inversion layers. The energy loss of the carriers to the lattice and the drift velocity or mobility are treated as two dimensional. Formulas for the energy loss are presented for both high and very low temperatures considering scattering by optical and acoustical phonons. The calculations are compared with experimental values given by Fang and Fowler and by Sato et al. Good agreement is found for the high‐temperature case using coupling constants as given by Sah et al. Quite large differences between theory and experiment appear at very low temperatures. The origin of these differences is discussed in a final section.
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paper_title: Submicrometer MOSFET structure for minimizing hot-carrier generation

paper_content:

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.
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paper_title: Correlation between substrate and gate currents in MOSFET's

paper_content:

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.
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paper_title: Theory of hot electron emission from silicon into silicon dioxide

paper_content:

We present Monte Carlo simulations of the hot electron emission from silicon into the oxide of metal oxide silicon transistors. The calculations include the pseudopotential band structure and quantum effects such as collision broadening due to the electron–phonon interaction. As a result, we present a set of transport parameters which well describes all hot electron effects in silicon (including saturation velocity and impact ionization). We also show that the collision broadening effect leads to an effective barrier lowering and may require that voltages be scaled down far below the interface barrier height of ∼3.1 V in order to avoid hot electron emission.
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paper_title: Long Journey into Tunneling

paper_content:

I am, of course, deeply aware of important contributions made by many colleagues and my friends throughout this long journey. The subject of the second section was carried out when I was in Japan and all the rest ( 35 ) has been performed in the United States of America. Since my journey into tunneling is still continuing, I do not come to any conclusions in this talk. However, I would like to point out that many high barriers exist in this world: barriers between nations, races, and creeds. Unfortunately, some barriers are thick and strong. But I hope, with determination, we will find a way to tunnel through these barriers easily and freely, to bring the world together so that everyone can share in the legacy of Alfred Nobel.
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paper_title: Quantum-mechanical modeling of accumulation layers in MOS structure

paper_content:

An original method is used for the quantum-mechanical modeling of n-type silicon accumulation layers. Unlike previous methods, which were only valid near 4.2 K, the approach is valid up to room temperature and beyond. The self-consistent results obtained are compared with those of the standard classical model for the accumulation layer, and the differences between them are found to be relevant for the modeling of important device applications. The dependences of the accumulation voltage drop and effective F-N (Fowler-Nordheim) barrier height on oxide electric field and substrate dopine are reported. Experimental F-N current-voltage characteristics of production-quality MOS capacitors are used to validate the quantum results and to show that the standard classical model is not adequate even if the barrier height is considered as a fitting parameter. Approximate analytical expressions giving the semiconductor voltage drop and the effective F-N barrier height as a function of oxide field and substrate doping are derived for and n-type silicon at 77 and 300 K. >
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paper_title: Reliability performance of ETOX based flash memories

paper_content:

The reliability performance of a 64 K flash memory based on a single-transistor, floating-gate memory cell is considered. The reliability performance of these memories, before program/erase cycling, matches that of UV EPROMs. Cycling generally does not introduce defect-related failures common to some EEPROMs. However, it may aggravate two intrinsic instabilities found in the UV EPROM (intrinsic charge loss and the DC program disturb mechanism). Experience shows that these are related effects caused by injection of holes during the erase step of the cycle. High source-to-substrate electric fields, during erase, generate these holes. Channel hot electron injection, for programming, plays no significant role in the observed degradation. These cycling effects can be addressed through incorporation of additional margin into the flash cell. Through such cell optimization, the reliability of these memories is made equivalent to that of conventional UV EPROMs, even after hundreds of program/erase cycles. >
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paper_title: An electrically alterable nonvolatile memory cell using a floating-gate structure

paper_content:

An electrically alterable, floating-gate, nonvolatile memory transistor has been developed, with a cell area of under 500 µm2, and using an advanced n-channel, polysilicon gate process. Cell programming occurs via hot-electron injection, exhibiting three distinct operating regimes. Erase, on the other hand, is based on field emission from floating gate to control gate. The magnitude of electrical erase is determined by applied bias, device parameters, and processing history, particularly the interlevel oxidation temperature. Analysis of experimental data shows that electrical erase does change programming characteristics significantly, and must be accounted for in circuit design. Memory retention, determined by thermal stress, is comparable to commercially available EPROM's. The memory cell exhibits better than 1000-cycle write/erase capability, with degradation in interlevel conduction being the principal factor limiting endurance. A 5-V, 16K high-speed EAROM has been developed which shows successful programming and erase behavior at nominal voltages of 25 and 35 V, respectively.
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paper_title: Multilevel flash cells and their trade-offs

paper_content:

In this paper we compare six different multilevel flash cells, viz., common ground, DINOR, AND, AMG, split gate and NAND. The key conclusions are that the hot electron effect lends itself better than tunneling as the multilevel programming mechanism. The common ground cell is the most suitable for multilevel flash cells. The NAND architecture is the least favorable.
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paper_title: Non Volatile Memories: Issues, Challenges and Trends for the 2000's Scenario

paper_content:

Main issues regarding actual Non Volatile Memory are presented, considering the market growth and the application requirements. The focus is on the evolution of the Flash memory technology, oriented to both reducing cell size and upgrading product functions. Flash will be the DRAM challenger in the next decade: the cost per bit and the performance improvements in term of access time and write transfer rate will be the main trends.
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paper_title: Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

paper_content:

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.
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paper_title: Hot-electron injection into the oxide in n-channel MOS devices

paper_content:

In recent years the interest in hot-electron injection currents in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses problems of trapping and local heating, allowing full characterization of parameter, voltage and temperature dependence down to gate current levels of 10-16A. Based on this characterization a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot-electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinch off region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.
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paper_title: Complete transient simulation of flash EEPROM devices

paper_content:

A two-dimensional device simulator which allows the complete transient simulation of nonvolatile memories is presented. The simulator has been derived from HFIELDS and incorporates models to account for Fowler-Nordheim tunneling, hot electron injection through silicon dioxide, and band-to-band tunneling in silicon. The physical models have been verified by comparing simulations with measurements performed on suitable test structures where good agreement has been obtained. The tool has been used to investigate flash EEPROM device scaling and to evaluate a published scaling scenario. >
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paper_title: Comparison of current flash EEPROM erasing methods: stability and how to control

paper_content:

The effects of process and device parameter fluctuations of flash EEPROM cells on the flash-erasing instabilities are systematically investigated using a simple analytical model and numerical simulation. Among various erase methods, the High voltage Source with grounded Erase (HSE) method is the most stable scheme for the control of erasing speed and erased threshold voltage distribution. The stability of HSE is caused by the reduced electric field fluctuations associated with cell parameter variations, due to the source bias effect, especially at the final stage of erasing. It is also found that the recently proposed self-convergence scheme is an effective tool for suppressing the erased-V/sub t/ distribution width, and that negative gate erase designs equipped with this method will be a powerful vehicle for the next generation scaled flash devices. >
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paper_title: Failure mechanisms of flash cell in program/erase cycling

paper_content:

The impact of program/erase cycling on flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented. >
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paper_title: High‐field‐induced voltage‐dependent oxide charge

paper_content:

In this work, we investigate the effects of nondisruptive high‐field stress on the tunneling characteristics of thin SiO2 films (<100 A) and show that after the stress the charge trapped within the oxide reversibly depends on the applied voltage. This is explained with a model where electrons tunnel in and out of trap states located near the injecting interface. Consequently, the trap occupation, hence oxide charge, is determined by transmission coefficients that strongly depend on the actual oxide potential.
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paper_title: Reliability issues of flash memory cells

paper_content:

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current. >
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paper_title: Failure mechanisms of flash cell in program/erase cycling

paper_content:

The impact of program/erase cycling on flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented. >
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paper_title: Degradation mechanism of flash EEPROM programming after program/erase cycles

paper_content:

The mechanism of degradation of flash EEPROM cell characteristics caused by program operation with the channel hot electron injection after program/erase (P/E) cycles are investigated. To clarify the relation between the degradation and oxide damage such as interface-states and oxide charges, the charge-pumping (CP) technique, transconductance (G/sub m/) measurements and cell endurance measurements are performed. In the degradation, a reduction of electron injection into the floating gate and a reduction of the G/sub m/ should be considered separately. The reduction of electron injection into the floating gate is found to be caused mainly by the interface-states located in the drain overlap region, not by charges trapped in the oxide. These interface-states are created during the initial step of program operation. On the contrary, a reduction of G/sub m/ is caused mainly by interface-states located around the drain edge. These are created during the final step of program operation. >
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paper_title: Submicrometer MOSFET structure for minimizing hot-carrier generation

paper_content:

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.
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paper_title: New EPROM Data-Loss Mechanisms

paper_content:

Data-loss mechanisms in present-generation EPROMs have been studied. Defect-related data loss is primarily due to interpoly-oxide defects. This is a change from the previous generation and introduces a new EPROM failure mode--column data loss. Contamination-compensation is found to be due as much to field-driven motion as to diffusion, and one result is that contaminated regions can exhibit charge gain as well as charge loss. Intrinsic charge loss is attributed to detrapping of electrons from the oxide layers rather than to loss of stored charge, suggesting that with proper screening of defects EPROM data retention is effectively unlimited.
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paper_title: A novel erasing technology for 3.3 V flash memory with 64 Mb capacity and beyond

paper_content:

A novel erasing scheme has been developed to suppress the distribution of the erased cell threshold voltage (erased-V). The new 2-step erasing scheme consists of two steps of the cell gate bias conditions, that is to apply 1) negative high voltage on the control gate to erase the cell data, and successive 2) positive high voltage to inject a few electrons from the substrate back to the floating gate. The suppressing effect of the erased-V distribution was also confirmed using a 16 Kbit flash memory cell array, the erased-V/sub /distribution drastically decreases from 2.0 V by the conventional erasing scheme to 0.9 V using the 2-step erasing scheme. >
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paper_title: Failure mechanisms of flash cell in program/erase cycling

paper_content:

The impact of program/erase cycling on flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented. >
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paper_title: Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET's

paper_content:

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO/sub 2/ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 /spl mu/m n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V/sub dg/). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression /spl Delta/I/sub d/=Aexp(B/sub it//F). The value of B/sub it/ about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V/sub dg/ decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V/sub dg/, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant. >
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paper_title: Interface trap-enhanced gate-induced leakage current in MOSFET

paper_content:

Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p/sup +/-gated diode can increase by two orders of magnitude when the interface trap density is increased from 10/sup 11/ to 10/sup 12/ cm/sup -2/-eV/sup -1/. The fact that thermal annealing at 300 degrees C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p/sup +/-gated diode is found to be more susceptible to this interface-trap related leakage current than the n/sup +/-device, which can be explained qualitatively by an interface-trap-assisted tunneling model. >
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paper_title: A self-convergence erasing scheme for a simple stacked gate flash EEPROM

paper_content:

A novel erasing method for simple stacked gate flash EEPROMs is described. The method makes use of avalanche hot carrier injection after erasure by Fowler-Nordheim tunneling. The threshold voltages converge to a certain 'steady-state' as a result of the injection. The steady-state is caused by a balance between avalanche hot electron injection into the floating gate and avalanche hot hole injection into the floating gate, and can be controlled easily by the channel doping. Tight distribution of threshold voltages and stable erasure without over-erased cells are demonstrated by applying cells using 0.6- mu m CMOS technology. In addition, short erase time is realized using the novel erase sequence. >
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paper_title: Flash EPROM disturb mechanisms

paper_content:

Analyses have been performed on floating-gate avalanche-injection MOS transistor (FAMOS) devices which have been subjected to write/erase cycling, resulting in hole injection into the tunnel dielectric. Theoretical and experimental analysis of these devices have shown that the bits which exhibit fast erase due to these trapped holes are highly modulated by the field across the tunnel dielectric. Two distinct disturb mechanisms, one of which is heavily impacted by write/erase cycling, have been evaluated with regards to their field and temperature dependencies and empirical models have been developed for both mechanisms. >
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paper_title: Non Volatile Memories: Issues, Challenges and Trends for the 2000's Scenario

paper_content:

Main issues regarding actual Non Volatile Memory are presented, considering the market growth and the application requirements. The focus is on the evolution of the Flash memory technology, oriented to both reducing cell size and upgrading product functions. Flash will be the DRAM challenger in the next decade: the cost per bit and the performance improvements in term of access time and write transfer rate will be the main trends.
---
paper_title: Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices

paper_content:

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.
---
paper_title: Alternate metal virtual ground EPROM array implemented in a 0.8 mu m process for very high density applications

paper_content:

The alternate metal virtual ground EPROM array (AMG) is introduced as a new scaling concept. This array dramatically reduces cell size by making poly pitch the only limitation in both X and Y directions. The AMG concept scales cell size by sharing one metal line per two diffusion bit lines and relies on a segmentation scheme and fieldless array to achieve the poly pitch limited cell. The cell size in 0.8- mu m technology is 2.56 mu m/sup 2/, which is considerably smaller than the standard EPROM cell in 0.6- mu m technology. A major advantage of this array is reduction of drain turn-on induced punch-through. This reduction allows scaling of effective channel length to as low as 0.25 mu m, resulting in high read current and fast programming time. >
---
paper_title: A new flash-erase EEPROM cell with a sidewall select-gate on its source side

paper_content:

A novel flash-erase EEPROM (electrically erasable PROM) cell is described. It consists of a stacked-gate MOSFET with a sidewall select gate on the source side of the FET (SISOS cell). Three layers of polysilicon are used. The cell has a self-aligned structure which makes it possible to realize a small cell area of 4.0*3.5 mu m/sup 2/ with 1.0- mu m technology. It also has a select gate which prevents undesirable leakage current due to overerasing. The cell is programmed by channel hot electron injection at the source side and erased by Fowler-Nordheim tunneling of electrons from the floating gate to the drain. The programming by source-side injection makes it possible for the drain junction to be optimized independently of hot electron generation and for the erasure to be achieved with no degradation in programmability. >
---
paper_title: A new flash-erase EEPROM cell with a sidewall select-gate on its source side

paper_content:

A novel flash-erase EEPROM (electrically erasable PROM) cell is described. It consists of a stacked-gate MOSFET with a sidewall select gate on the source side of the FET (SISOS cell). Three layers of polysilicon are used. The cell has a self-aligned structure which makes it possible to realize a small cell area of 4.0*3.5 mu m/sup 2/ with 1.0- mu m technology. It also has a select gate which prevents undesirable leakage current due to overerasing. The cell is programmed by channel hot electron injection at the source side and erased by Fowler-Nordheim tunneling of electrons from the floating gate to the drain. The programming by source-side injection makes it possible for the drain junction to be optimized independently of hot electron generation and for the erasure to be achieved with no degradation in programmability. >
---
paper_title: A dual-bit split-gate EEPROM (DSG) cell in contactless array for single-Vcc high density flash memories

paper_content:

A new source-side injection Dual-bit Split-Gate (DSG) flash EEPROM cell is designed and characterized. With a 0.6 /spl mu/m process, the cell-size of 1.95 /spl mu/m/sup /spl and//2 per bit in a contactless array is achieved. With a shared select-gate, the cell consists of three directly jointed channels. Taking advantage of the split-gate structure, the threshold voltage of the floating-gate transistor is allowed to move from enhancement-mode to depletion-mode between write and erase operations. Only moderate voltages (less than 10 V) are required the for the cell operations, which relax the high-voltage device requirements on peripheral circuitry and thus simplify the process with less masking steps. With on-chip charge pumps, this cell is suitable for very high density and low power mass-storage applications with single-Vcc power supply. >
---
paper_title: A new cell structure for sub-quarter micron high density flash memory

paper_content:

A new cell structure named ACT (Asymmetrical Contactless Transistor) is proposed for high density data storage applications which require low voltage, low power consumption and fast program/erase. The ACT cell with a lightly doped source and heavily doped drain realizes a simple virtual ground array using the Fowler-Nordheim (FN) tunneling mechanism for both program and erase. A self-aligned floating-gate wing technology is introduced to increase gate coupling ratio in word-line direction without sacrificing cell area. A cell area as small as 0.39 /spl mu/m/sup 2/ with a coupling ratio of 0.55 is obtained using 0.3 /spl mu/m process technology. The low programming current of the ACT cell enables multiple programming to be used and thus it is possible to achieve fast programming (<1 /spl mu/s/byte) with a low single supply voltage (<3 V). A good disturb immunity in program, erase and read modes is also obtained.
---
paper_title: A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories

paper_content:

A novel contactless cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim tunneling, has been developed for 3 V-only 64 Mbit and future flash memories. A 1.50 /spl mu/m/sup 2/ cell area is obtained by using a 0.4 /spl mu/m technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) advanced rapid thermal process for 7.5-nm thick tunnel oxynitride. The internal voltages used for program and erase are +8 V and +12 V, respectively. The total process-step numbers can be reduced to 85% compared to reported memory cells so far. >
---
paper_title: Non Volatile Memories: Issues, Challenges and Trends for the 2000's Scenario

paper_content:

Main issues regarding actual Non Volatile Memory are presented, considering the market growth and the application requirements. The focus is on the evolution of the Flash memory technology, oriented to both reducing cell size and upgrading product functions. Flash will be the DRAM challenger in the next decade: the cost per bit and the performance improvements in term of access time and write transfer rate will be the main trends.
---
paper_title: Single-electron-memory integrated circuit for giga-to-tera bit storage

paper_content:

A single-electron-based integrated circuit is presented. An 8/spl times/8 b memory-cell array demonstrates read/write, ushering in a new phase of research on single-electron devices.
---

Title: Flash Memory Cells—An Overview

Section 1: INTRODUCTION
Description 1: Discuss the evolution, market trends, and overall significance of Flash memory cells in the semiconductor industry.

Section 2: NONVOLATILE MEMORIES
Description 2: Outline the different types of nonvolatile memories, including their characteristics and applications.

Section 3: PROGRAMMABLE ROM-INFORMATION STORAGE AND ACCESS
Description 3: Explain the principles of programmable ROM, covering information storage, programming, and erasing techniques.

Section 4: FG DEVICE
Description 4: Describe the basic concepts, functionality, and electrical behavior of a floating-gate (FG) device.

Section 5: THE READING OPERATION
Description 5: Detail the process of reading stored information from Flash memory cells.

Section 6: CHARGE INJECTION MECHANISMS
Description 6: Discuss the methods of transferring electric charge in and out of the FG, including hotelectron injection and Fowler-Nordheim tunneling.

Section 7: INDUSTRY-STANDARD FLASH CELLS
Description 7: Provide an overview of the structure, basic operations, and development of industry-standard Flash memory cells.

Section 8: RELIABILITY
Description 8: Examine the reliability issues related to Flash memory cells, including programming disturbs, retention, endurance, and erase distribution.

Section 9: SCALING ISSUES
Description 9: Address scaling concerns in the development of Flash memory technology, including the challenges and future outlook.

Section 10: FLASH ARRAY ARCHITECTURES
Description 10: Explore various Flash array architectures and their applicative differences, including alternate metal ground (AMG) cells, split-gate cells, source-injection cells, DINOR cells, asymmetrical contactless transistors (ACT), AND cells, high capacitive coupling ratio (HiCR) cells, and NAND architecture.

Section 11: CONCLUSION
Description 11: Summarize the key points covered in the paper and provide insights into the future prospects of Flash memory technology.