A Survey of Media Processing Approaches
---
paper_title: AMD's 3DNow!/sup TM/ vectorization for signal processing applications

paper_content:

AMD's 3DNow!/sup TM/ technology provides substantial speedup for digital signal processing applications. A set of DSP routines is vectorized with the 3DNow!/sup TM/ technology. The simplicity of the vector unit makes it easier to convert the conventional DSP programs into vector operations, and thus reduces the learning curve. The performance gain from typical DSP routines such as FIR, IIR and FFT indicates that the speedup can reach up to 1.5 compared to the conventional host-based signal processing units. 3D games and multimedia applications benefit from the technology. The vectorization can be integrated into compilers for the ease of use in increasing the performance of the signal processing applications.
---
paper_title: The M-PIRE MPEG-4 codec DSP and its macroblock engine

paper_content:

M-PIRE is a programmable MPEG-4 multimedia codec VLSI for mobile and stationary applications. It integrates a RISC core, two separate DSPs, a 64-bit dual-issue VLIW macroblock engine, and an autonomous I/O processor on a single chip to cope with the high flexibility and processing demands of the MPEG-4 standard. The first M-PIRE implementation will consume 90 mm/sup 2/ in 0.25 /spl mu/ CMOS technology. It will support real-time video and audio processing of MPEG-4 simple profile or ITU H.26x standards; future designs of M-PIRE will add support for higher MPEG-4 profiles. This paper focuses on the architecture, instruction set, and performance of M-PIRE's macroblock engine, which carries most of the workload in MPEG-4 video processing.
---
paper_title: A 0.8 /spl mu/ 100-MHz 2-D DCT core processor

paper_content:

The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 /spl mu/ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG. >
---
paper_title: AltiVec extension to PowerPC accelerates media processing

paper_content:

There is a clear trend in personal computing toward multimedia-rich applications. These applications will incorporate a wide variety of multimedia technologies, including audio and video compression, 2D image processing, 3D graphics, speech and handwriting recognition, media mining, and narrow/broadband signal processing for communication. In response to this demand, major microprocessor vendors have announced architectural extensions to their general-purpose processors in an effort to improve their multimedia performance. Intel extended IA-32 with MMX and SSE (alias KNI), Sun enhanced Sparc with VIS, Hewlett-Packard added MAX to its PA-RISC architecture, Silicon Graphics extended the MIPS architecture with MDMX, and Digital (now Compaq) added MVI to Alpha. This article describes the most recent, and what we believe to be the most comprehensive, addition to this list: PowerPC's AltiVec, AltiVec speeds not only media processing but also nearly any application in which data parallelism exists, as demonstrated by a cycle-accurate simulation of Motorola's MPC 7400, the heart of Apple G4 systems.
---
paper_title: The Garp architecture and C compiler

paper_content:

Various projects and products have been built using off-the-shelf field-programmable gate arrays (FPGAs) as computation accelerators for specific tasks. Such systems typically connect one or more FPGAs to the host computer via an I/O bus. Some have shown remarkable speedups, albeit limited to specific application domains. Many factors limit the general usefulness of such systems. Long reconfiguration times prevent the acceleration of applications that spread their time over many different tasks. Low-bandwidth paths for data transfer limit the usefulness of such systems to tasks that have a high computation-to-memory-bandwidth ratio. In addition, standard FPGA tools require hardware design expertise which is beyond the knowledge of most programmers. To help investigate the viability of connected FPGA systems, the authors designed their own architecture called Garp and experimented with running applications on it. They are also investigating whether Garp's design enables automatic, fast, effective compilation across a broad range of applications. They present their results in this article.
---
paper_title: A 600 MHz 2D-DCT processor for MPEG applications

paper_content:

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.
---
paper_title: Video Image Processing with the Sonic Architecture

paper_content:

Current industrial video-processing systems use a mixture of high-performance workstations and application-specific integrated circuits. However, video image processing in the professional broadcast environment requires more computational power and data throughput than most of today's general-purpose computers can provide. In addition, using ASICs for video image processing is both inflexible and expensive. Configurable computing offers an appropriate alternative for broadcast video image editing and manipulation by combining the flexibility, programmability, and economy of general-purpose processors with the performance of dedicated ASICs. Sonic is a configurable computing system that performs real-time video image processing. The authors describe how it implements algorithms for two-dimensional linear transforms, fractal image generation, filters, and other video effects. Sonic's flexible and scalable architecture contains configurable processing elements that accelerate software applications and support the use of plug-in software.
---
paper_title: AMD 3DNow! technology: architecture and implementations

paper_content:

The AMD-K6-2 microprocessor is the first implementation of AMD 3DNow!, a technology innovation for the x86 architecture that drives today's personal computers. 3DNow! technology is a set of 21 new instructions designed to open the traditional processing bottlenecks for floating-point-intensive and multimedia applications. Using these instructions, applications can implement more powerful solutions to create a more entertaining and productive PC platform. Examples of the type of improvements that 3DNow! technology enables are faster frame rates on high-resolution scenes, better physical modeling of real-world environments, sharper and more detailed 3D imaging, smoother video playback, and near theater-quality audio. Future AMD processors such as the AMD-K7, designed to operate at frequencies greater than 500 MHz, should provide even higher performance implementations of 3DNow! technology.
---
paper_title: UltraSparc I: a four-issue processor supporting multimedia

paper_content:

UItraSpare I is a second-generation superscalar processor. It is a high performance, highly integrated, four issue superscalar processor based on the Spare Version 9 64-bit RISC architecture. We have extended the core instruction set to include graphics instructions that provide the most common operations related to two dimensional image processing; two- and three-dimensional graphics and image compression algorithms; and parallel operations on pixel data with 8-, 16-, and 32-bit components. Additional, new memory access instructions support the very high bandwidth requirements typical of graphics and multimedia applications.
---
paper_title: A 0.8 /spl mu/ 100-MHz 2-D DCT core processor

paper_content:

The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 /spl mu/ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG. >
---
paper_title: The MAP1000A VLIM mediaprocessor

paper_content:

Presents the MAP1000A, an alternative to using custom ASICs for each multimedia-processing task. It is a single-chip, programmable mediaprocessor that also makes use of general-purpose RISC processing and a view framework. It provides a new programmable infrastructure with the cost, performance, and power characteristics suitable for replacing RISCs and ASICs in consumer electronics, communications, and imaging applications while, retaining a completely high-level-language programming approach. This single-chip mediaprocessor handles all digital functions in high-level-language software with significantly improved performance and without increased system cost or development complexity.
---
paper_title: Use IRAM for rasterization

paper_content:

A new intelligent RAM (IRAM) architecture based on embedding DRAM memory and many simple processors on a chip is introduced. The architecture has the advantage of being able to perform massive parallel computing and of being usable as plain DRAM. Some key parts of the architecture are described. We also show that the architecture can be used in graphics applications where high rasterizer performance is required.
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paper_title: Multimedia Enhanced General-Purpose Processors

paper_content:

This paper gives an overview of the multimedia instructions that have been added to the instruction set architectures of general-purpose microprocessors to accelerate media processing. Examples are MAX, MMX and VIS, the multimedia extensions for PA-RISC, ix86, and SPARC processor architectures. We describe subword parallelism, a low overhead form of SIMD parallelism, and the classes of instructions needed to support subword parallel computations efficiently. Features described include arithmetic operations with saturation, averaging, multiply alternatives, data rearrangement primitives like Permute and Mix, formatting instructions, conditional execution, and complex instructions.
---
paper_title: UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor

paper_content:

UltraSPARC-III (US-III) is a 64 b 800 MHz 4-instruction-issue superscalar microprocessor for high-performance desktop workstation, work group server, and enterprise server platforms. On-chip caches include a 64 kB 4-way associative for data, 32 kB 4-way associative for instructions, a 2 k B 4-way associative data prefetch cache, and a 2 kB 4-way associative write. A 90 kB on-chip tag array supports the off-chip 8 MB unified second-level cache. The 23 M-transistor chip in a 0.15 /spl mu/m, 7-layer metal process consumes 60 W from a 1.5 V supply.
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paper_title: 64-bit and multimedia extensions in the PA-RISC 2.0 architecture

paper_content:

This paper describes the architectural extensions to the PA-RISC 1.1 architecture to enable 64-bit processing of integers and pointers. It also describes MAX, the Multi-media Acceleration eXtensions which speed up the processing of multimedia and other applications with parallelism at the intra instruction, or subword, level. Other additions to the PA-RISC 2.0 architecture include performance enhancements with respect to memory hierarchy management, branch penalty reduction, and floating-point performance.
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paper_title: An X86 microprocessor with multimedia extensions

paper_content:

This sixth-generation X86 instruction-set compatible microprocessor implements a set of multimedia extensions. Instruction predecoding to identify instruction boundaries begins during filling of the 32 kB two-way set associative instruction cache after which the predecode bits are stored in the 20 kB predecode cache. The processor decodes up to two X86 instructions per clock, most of which are decoded by hardware into one to four RISC-like operations, called RISC86 Ops, whereas the uncommon instructions are mapped into ROM-resident RISC sequences. The instruction scheduler buffers up to 24 RISC86 operations, using register renaming with a total of 48 registers. Up to six RISC86 instructions are issued out-of-order to seven parallel execution units, speculatively executed and retired in order. The branch algorithm uses two-level branch prediction based on an 8192-entry branch history table, a 16-entry branch target cache and a 16-entry return address stack. The 10.18/spl times/15.38 mm/sup 2/ die contains 8.8M transistors. The chip is in 0.35 /spl mu/m CMOS using five layers of metal, shallow trench isolation, and tungsten local interconnect.
---
paper_title: VIS speeds new media processing

paper_content:

UltraSparc's Visual Instruction Set, described here in detail, accelerates some widely used media-processing algorithms by as much as seven times. Today's new media, increasingly sophisticated 3D graphics environments, videoconferencing, MPEG video playback, 3D visualization, image processing, and so on, demand enhancements to conventional RISC instruction sets, which were not originally designed to handle such applications. The Visual Instruction Set (VIS) is a comprehensive set of RISC-style instructions targeted at accelerating this new media processing.
---
paper_title: UltraSparc I: a four-issue processor supporting multimedia

paper_content:

UItraSpare I is a second-generation superscalar processor. It is a high performance, highly integrated, four issue superscalar processor based on the Spare Version 9 64-bit RISC architecture. We have extended the core instruction set to include graphics instructions that provide the most common operations related to two dimensional image processing; two- and three-dimensional graphics and image compression algorithms; and parallel operations on pixel data with 8-, 16-, and 32-bit components. Additional, new memory access instructions support the very high bandwidth requirements typical of graphics and multimedia applications.
---
paper_title: The Internet Streaming SIMD Extensions

paper_content:

Because floating-point computation is the heart of 3D geometry, speeding up floating-point computation is vital to overall 3D performance. To produce a visually perceptible difference in graphics applications, Intel's 32-bit processors-based on the IA-32 architecture-required an increase of 1.5 to 2 times the native floating-point performance. One path to better performance involves studying how the system uses data. Today's 3D applications can execute a lot faster by differentiating between data used repeatedly and streaming data-data used only once and then discarded. The Pentium III's new floating-point extension lets programmers designate data as streaming and provides instructions that handle this data efficiently. The authors designed the Internet Streaming SIMD Extensions (ISSE) to enable a new level of visual computing on the volume PC platform. They discuss their results in terms of boosting the performance of 3D and video applications.
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paper_title: A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding

paper_content:

In multimedia applications, various video encoding/decoding standards such as MPEG2, MPEG1 and emerging algorithms call for a DSP solution of the extremely computation-intensive tasks. Several DSPs have been developed based on intensive pipeline processing at the macro-block level. In these DSPs, macroblock-based pipeline memory slices are needed for each pipeline stage. Programmability is limited by the hard-wired macros to be incorporated such as DCT and Quantizer. A microprocessor or a media-processor with multimedia-enhanced instructions has not yet been applied to MPEG2 encoding. This DSP for real-time codec applications has the following features: (a) extensive use of data parallelism inside the macro-block data structure, (b) flexible data path for coding algorithms to enhance gate utilization and to reduce the use of macro-block pipeline memory, (c) data path design suitable for (but not limited to) fast DCT/IDCT algorithms.
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paper_title: A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

paper_content:

A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-/spl mu/m CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm/spl times/10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 /spl mu/A, which is only 17% of that for the conventional CMOS design.
---
paper_title: The MAP1000A VLIM mediaprocessor

paper_content:

Presents the MAP1000A, an alternative to using custom ASICs for each multimedia-processing task. It is a single-chip, programmable mediaprocessor that also makes use of general-purpose RISC processing and a view framework. It provides a new programmable infrastructure with the cost, performance, and power characteristics suitable for replacing RISCs and ASICs in consumer electronics, communications, and imaging applications while, retaining a completely high-level-language programming approach. This single-chip mediaprocessor handles all digital functions in high-level-language software with significantly improved performance and without increased system cost or development complexity.
---
paper_title: SH4 RISC multimedia microprocessor

paper_content:

Unique, floating-point length-4 vector instructions prove more effective than conventional SIMD architecture for 3D graphics processing.
---
paper_title: A high performance DSP architecture "MSPM" for digital image processing using embedded DRAM ASIC technologies

paper_content:

This paper describes the architecture of the "MSPM: Multimedia Signal Processor with embedded Memory". It has been developed to evaluate the architectural effects of 0.35-micron embedded DRAM technologies on the performance. The chip has achieved 24 times the performance of an ordinary RISC processor at the same frequency, and also ten times the performance of an ordinary 16 bit DSP. The improvement has been made possible by the following architectural characteristics: direct-memory-referring instruction sets; SIMD-type-parallel-executing features; byte-aligned-word-access features; and multi-instruction migrating features. The MSPM achieved 800 MOPS@66 MHz with 1.1 Gbyte/s bandwidth. Integration of a 16 Mb DRAM with 128 bit data bus is also reported.
---
paper_title: An area efficient video/audio codec for portable multimedia application

paper_content:

In this paper, we present an area efficient video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as VASP (Video Audio Signal Processor) consists of a video signal processing block and an audio signal processing block. This chip has a mixed hardware/software architecture to combine performance and flexibility. The video signal processing block was designed to implement hardwired solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bit RISC type internal controller. The audio signal processing block is implemented with a software solution using 16 bit fixed point DSP. This chip contains 142,300 gates, 22 kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size was 9.02 mm/spl times/9.06 mm which was fabricated using 0.5 micron 3-layers metal CMOS technology.
---
paper_title: A media processor for multimedia signal processing applications

paper_content:

A multimedia system requires processing capabilities that include controlling functions as well as high throughput. For the consumer market, this processor must also satisfy low cost constraints. An efficient solution is the use of a dual-issue RISC architecture with key enhancements to target the high computation needs of multimedia applications. The RISC design methodology ensures its ease of programming and efficient controlling functions while its dual-issue approach lead to a high resource utilization. Key enhancements to this architecture include flexibility in the issuing control of the dual instructions; special instructions to implement SIMD parallelism; and full flexibility of half-word precision and double-word precision arithmetic instructions.
---
paper_title: A 2000-MOPS embedded RISC processor with a Rambus DRAM controller

paper_content:

We have developed a 0.25-/spl mu/m, 200-MHz embedded RISC processor for multimedia applications. This processor has a dual-issue superscalar datapath that consists of a 32-bit integer unit and a 64-bit single-instruction multiple-data (SIMD) function unit that together have a total of five multiply-adders. An on-chip concurrent Rambus DRAM (C-RDRAM) controller uses interleaved transactions to increase the memory bandwidth of the Rambus channel to 533 Mb/s. The controller also reduces latency by using the transaction interleaving and instruction prefetching. A 64-bit, 200-MHz internal bus transfers data among the CPU core, the C-RDRAM, and the peripherals. These high-data-rate channels improve CPU performance because they eliminate a bottleneck in the data supply. The datapath part of this chip was designed using a functional macrocell library that included placement information for leaf cells and resulted in the SIMD function unit of this chip's having 68000 transistors per square millimeter.
---
paper_title: The D30V/MPEG multimedia processor

paper_content:

MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation are the main design considerations for these systems. Due to the high computational requirements of real-time applications, multimedia systems typically use special-purpose processors to handle data. However, due to the inherent inflexibility of their designs, these dedicated processors are of little use in various application environments-digital videocassette recorders, for example. This article introduces Mitsubishi's D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. This approach is advantageous because of the small chip area it requires and the flexibility of the easy-to-program RISC processor for multimedia applications.
---
paper_title: High-speed and low-power real-time programmable video multi-processor for MPEG-2 multimedia chip on 0.6 /spl mu/m TLM CMOS technology

paper_content:

We developed a Video Multi Processor (VMP) for image compression and decompression schemes of MPEG (especially MPEG-2) in this study. The VMP would apply to programmable architecture, various flexibilities to implement real-time image compression algorithm, and other many applications such as DVD-CD ROM authoring tool and videophone/teleconferencing systems. IO architecture of the VMP is designed for the multi-processor functionality in which uses many VMPs according to required arithmetic quantities of the system. Further, the architecture of the VMP system is simplified by processing the necessary peripheral IO system operations within the processor.
---
paper_title: Design space exploration for future TriMedia CPUs

paper_content:

It is widely recognized that fine-grain parallelism can greatly enhance a processor's performance for signal processing applications. For this reason, future generation TriMedias will combine VLIW and subword parallelism in a single CPU. We present a snapshot of the new CPUs design process: the outlines are clear but fine tuning is still ongoing. We present the design flow and 'workbench' that the designers use for further tuning.
---
paper_title: The MAP1000A VLIM mediaprocessor

paper_content:

Presents the MAP1000A, an alternative to using custom ASICs for each multimedia-processing task. It is a single-chip, programmable mediaprocessor that also makes use of general-purpose RISC processing and a view framework. It provides a new programmable infrastructure with the cost, performance, and power characteristics suitable for replacing RISCs and ASICs in consumer electronics, communications, and imaging applications while, retaining a completely high-level-language programming approach. This single-chip mediaprocessor handles all digital functions in high-level-language software with significantly improved performance and without increased system cost or development complexity.
---
paper_title: A 600 MHz 2D-DCT processor for MPEG applications

paper_content:

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.
---
paper_title: Architecture and design of a Talisman-compatible multimedia processor

paper_content:

This paper describes the architecture, functionality, and design of a Talisman-compatible multimedia processor (TM-PC) from Philips Semiconductors. "Talisman" is the code name of a new graphics and multimedia hardware architecture (from Microsoft Corp.) that aims at achieving the performance of high-end three-dimensional graphics workstations at consumer price points. The TM-PC is a programmable processor with a high-performance, very long instruction word central processing unit (CPU) core. The CPU core, aided by an array of peripheral devices (multimedia coprocessors and input-output units), facilitates concurrent processing of audio, video, graphics, and communication data. Designed specifically for the Microsoft Talisman project, TM-PC is a derivative of Philips' TM-1 media processor and is tailored to be used in a variety of PC-based functions as a plug-in board on the peripheral component interconnect (PCI) bus. In the design of the TM-PC, the functionality of most of the blocks from the TM-1 has been kept unchanged; the primary changes in the existing blocks have been in the main memory and the PCI interfaces, and a new block, called VPB, has been added to support virtual frame buffer functionality as well as video graphics adapter and Soundblaster emulation capability. The major emphasis of this paper is on the design details of the new VPB module and an explanation of how it fits with the rest of the TM-1 design.
---
paper_title: The D30V/MPEG multimedia processor

paper_content:

MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation are the main design considerations for these systems. Due to the high computational requirements of real-time applications, multimedia systems typically use special-purpose processors to handle data. However, due to the inherent inflexibility of their designs, these dedicated processors are of little use in various application environments-digital videocassette recorders, for example. This article introduces Mitsubishi's D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. This approach is advantageous because of the small chip area it requires and the flexibility of the easy-to-program RISC processor for multimedia applications.
---
paper_title: Exploiting Java instruction/thread level parallelism with horizontal multithreading

paper_content:

Java bytecodes can be executed with the following three methods: a Java interpreter running on a particular machine interprets bytecodes; a Just-in-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the machine executes the translated codes; and a Java processor executes bytecodes directly. The first two methods require no special hardware support for the execution of Java bytecodes and are widely used currently. The last method requires an embedded Java processor, picoJavaI or picoJavaII for instance. The picoJavaI and picoJavaII are simple pipelined processors with no ILP (instruction level parallelism) and TLP (thread level parallelism) supports. A so-called MAJC (microprocessor architecture for Java computing) design can exploit ILP and TLP by using a modified VLIW (very long instruction word) architecture and vertical multithreading technique, but it has its own instruction set and cannot execute Java bytecodes directly. In this paper, we investigate a processor architecture which can directly execute Java bytecodes meanwhile can exploit Java ILP and TLP simultaneously. The proposed processor consists of multiple slots implementing horizontal multithreading and multiple functional units shared by all threads executed in parallel. Our architectural simulation results show that the Java processor could achieve an average 20 IPC (instructions per cycle), or 7.33 EIPC (effective IPC), with 8 slots and a 4-instruction scheduling window for each slot. We also check other configurations and give the utilization of functional units as well as the performance improvement with various kinds of working loads.
---
paper_title: A 0.8 /spl mu/ 100-MHz 2-D DCT core processor

paper_content:

The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 /spl mu/ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG. >
---
paper_title: A 600 MHz 2D-DCT processor for MPEG applications

paper_content:

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.
---
paper_title: The D30V/MPEG multimedia processor

paper_content:

MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation are the main design considerations for these systems. Due to the high computational requirements of real-time applications, multimedia systems typically use special-purpose processors to handle data. However, due to the inherent inflexibility of their designs, these dedicated processors are of little use in various application environments-digital videocassette recorders, for example. This article introduces Mitsubishi's D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. This approach is advantageous because of the small chip area it requires and the flexibility of the easy-to-program RISC processor for multimedia applications.
---
paper_title: A flexible processor architecture for MPEG-4 image compositing

paper_content:

This paper proposes a new array architecture for MPEG-4 image compositing. The emerging MPEG4 standard for multimedia applications allows script-based compositing of audiovisual scenes from multiple audio and visual objects. MPEG-4 supports both, natural (video) and synthetic (3D) visual objects or a combination of both. Objects can be manipulated, e.g. positioned, rotated, warped or duplicated by user interaction. A coprocessor architecture is presented, that works in parallel to an MPEG-4 video- and audio-decoder, and performs computation and bandwidth intensive low-level tasks for image compositing. The processor consists of an SIMD array of 16 DSPs to reach the required processing power for real-time image warping, alpha-blending and 3D rendering tasks. A programmable architecture allows one to adapt the processing resources to the specific needs of different tasks and applications. The processor has an object-oriented cache architecture with 2D virtual address space (e.g. textures), that allows concurrent and conflict-free access to shared data objects for all 16 DSPs. Especially I/O intensive tasks like texture-mapping, alpha-blending, image warping, z-buffer and shading algorithms benefit from shared memory caches and the possibility to preload data before it is accessed.
---
paper_title: The D30V/MPEG multimedia processor

paper_content:

MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation are the main design considerations for these systems. Due to the high computational requirements of real-time applications, multimedia systems typically use special-purpose processors to handle data. However, due to the inherent inflexibility of their designs, these dedicated processors are of little use in various application environments-digital videocassette recorders, for example. This article introduces Mitsubishi's D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. This approach is advantageous because of the small chip area it requires and the flexibility of the easy-to-program RISC processor for multimedia applications.
---
paper_title: Reconfigurable media processing

paper_content:

Multimedia processing is becoming increasingly important with a range of applications. Existing approaches for processing multimedia data can be broadly classified into two categories, namely: (i) microprocessors with extended media processing capabilities; and (ii) dedicated implementations (ASICs). The complexity, variety of techniques and tools associated with multimedia processing points to the opportunities for reconfigurable computing devices which will be able to adapt the underlying hardware dynamically in response to changes in the input data or processing environment. The paper proposes a novel approach to design a dynamically reconfigurable processor by performing hardware software co-design for a media processing application. As an example, the analysis of the shape coding module of MPEG-4 is chosen to demonstrate the potential for reconfigurability.
---

Title: A Survey of Media Processing Approaches

Section 1: INTRODUCTION
Description 1: Provide an overview of the various media processing techniques, highlight the challenges presented by multimedia computing, and introduce the need for reconfigurable processing in multimedia environments.

Section 2: MEDIA PROCESSING APPROACHES
Description 2: Discuss the factors influencing the design of cost-effective media processing solutions and provide a classification of existing media processing strategies and solutions.

Section 3: GENERAL-PURPOSE PROGRAMMABLE PROCESSORS
Description 3: Detail the architecture and features of CISC-and RISC-based processors, explore their implementation of media processing functionalities, and compare their effectiveness in handling multimedia applications.

Section 4: SPECIAL-PURPOSE PROGRAMMABLE PROCESSORS
Description 4: Examine the architectures and functionalities of special-purpose programmable processors, focusing on how they exploit redundancies and parallelism at various levels in media processing algorithms.

Section 5: DEDICATED IMPLEMENTATIONS
Description 5: Analyze the dedicated hardware implementations for media processing, including monolithic and distributed approaches, and discuss their application in real-world scenarios.

Section 6: CONCLUSION
Description 6: Summarize the findings of the survey, highlight the gaps in existing media processing solutions, and justify the need to explore reconfigurable computing for mobile multimedia applications.