A Review of PVT Compensation Circuits for Advanced CMOS Technologies
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paper_title: A PVT-insensitive CMOS output driver with constant slew rate

paper_content:

In this paper, we propose an output driver which has constant slew rate over PVT variation. To make output driver's slew rate to be constant, rising and failing time of pre-driving node of output driver is kept constant by predriver, which has constant pull-up and pull-down path resistance. To make output voltage swing level to be constant, another replica bias circuit was used with CMOS push-pull output driver. HSPICE simulations show that the slew rate is 3.21 V/nS on fast condition and 3.12V/nS on slow condition with 1.4K pre-driver's path resistance. This circuit was implemented with 0.18 /spl mu/m CMOS process.
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paper_title: Fast frequency acquisition all-digital PLL using PVT calibration

paper_content:

Fast frequency acquisition is crucial for phase-locked loops (PLLs) used in portable devices, as on-chip clocks are frequently scaled down or up in order to manage power consumption. This paper describes a new frequency acquisition method that is effective in all-digital PLLs (ADPLLs). To achieve fast frequency acquisition, the codeword of the digitally controlled oscillator (DCO) is predicted by measuring the variations of process, supply voltage and temperature (PVT). A PVT sensor implemented with a ring oscillator is employed to monitor the variations. As the sensor frequency at the current operating condition is directly related to the PVT variations, the sensor frequency is taken into account to compensate such variations in predicting the DCO codeword. The proposed method enables one-cycle frequency acquisition, and the frequency error is less than 1.5%. The proposed ADPLL implemented in a 0.18 mum CMOS process operates from 150 MHz to 500 MHz and occupies 0.075 mm2.
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paper_title: On-chip PVT compensation techniques for low-voltage CMOS digital LSIs

paper_content:

An on-chip process, supply voltage, and temperature (PVT) compensation technique for a low-voltage CMOS digital circuit is proposed. Because the degradation of circuit performance originates from the variation of the saturation current, a compensation technique that uses a reference current that is independent of PVT variations was developed. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Moreover, Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs showed the effectiveness of the proposed technique and achieved performance improvement of 74%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.
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paper_title: On-chip PVT compensation techniques for low-voltage CMOS digital LSIs

paper_content:

An on-chip process, supply voltage, and temperature (PVT) compensation technique for a low-voltage CMOS digital circuit is proposed. Because the degradation of circuit performance originates from the variation of the saturation current, a compensation technique that uses a reference current that is independent of PVT variations was developed. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Moreover, Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs showed the effectiveness of the proposed technique and achieved performance improvement of 74%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.
---
paper_title: A PVT-insensitive CMOS output driver with constant slew rate

paper_content:

In this paper, we propose an output driver which has constant slew rate over PVT variation. To make output driver's slew rate to be constant, rising and failing time of pre-driving node of output driver is kept constant by predriver, which has constant pull-up and pull-down path resistance. To make output voltage swing level to be constant, another replica bias circuit was used with CMOS push-pull output driver. HSPICE simulations show that the slew rate is 3.21 V/nS on fast condition and 3.12V/nS on slow condition with 1.4K pre-driver's path resistance. This circuit was implemented with 0.18 /spl mu/m CMOS process.
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Title: A Review of PVT Compensation Circuits for Advanced CMOS Technologies

Section 1: Introduction
Description 1: This section introduces the importance of PVT compensation circuits in maintaining high performance and signal integrity in ICs, especially for high-speed interfaces.

Section 2: Scope of the Problem
Description 2: This section describes the challenges posed by PVT variations and the necessity of compensation circuits for impedance matching and reducing signal reflection.

Section 3: Analog Compensation: General Background
Description 3: This section provides an overview of different implementations of analog PVT compensation circuits and their operational principles.

Section 4: Digital Compensation: General Background
Description 4: This section outlines the digital compensation techniques, highlighting their advantages over analog methods in terms of noise sensitivity and implementation ease.

Section 5: Digital Compensation: Implementation in CMOS065 nm Bulk Technology
Description 5: This section details the practical implementations of digital PVT compensation techniques for DDR2 and DDR3 I/O circuits in CMOS065 nm technology.

Section 6: Analog Compensation: Implementation in CMOS045nm SOI Technology
Description 6: This section explains the analog compensation method for maintaining constant output driver transconductance in CMOS045nm SOI technology.

Section 7: Conclusions
Description 7: This section summarizes the advantages and disadvantages of the discussed PVT compensation circuits, comparing analog and digital approaches and their suitability for different applications.