High-performance interconnects: an integration overview
---
paper_title: Interconnect scaling-the real limiter to high performance ULSI

paper_content:

Reducing interconnect pitch improves layout density, but degrades interconnect RC delay. Increasing metal aspect ratio (thickness/width) improves RC delay, but maximum benefits are achieved at an aspect ratio of /spl sim/2. Adding more interconnect layers improves density and performance, but practical limits are reached in just a few generations. New conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements.
---
paper_title: Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections

paper_content:

Experimental high-speed characterization and electrical modeling and simulation are presented for a six-layer Cu/SiO/sub 2/ on-chip wiring structure with 12.4-mm-long lines. Testing is performed over the temperature range -160/spl deg/C to +100/spl deg/C and across a 200-mm-diameter wafer. Very good agreement is reported between measured and simulated signal propagation and crosstalk waveforms. Modeling is done using a three-dimensional field solver and the R(f), L(f), and C matrices are used in a synthesized distributed network to simulate the signal behavior. Such a broadband analysis comprises the first comprehensive functional testing of a multi-layer Cu/SiO/sub 2/ wiring structure. The Cu interconnections are shown to be able to sustain 5.39 GHz microprocessor frequencies at T=+25/spl deg/C operation at a scaled wiring density increase of 17.5%, while comparable Al(Cu) wiring can achieve only 4.44 GHz (21.4% improvement).
---
paper_title: A scaling scheme for interconnect in deep-submicron processes

paper_content:

In this paper, we study the requirements for interconnect in deep-submicron technologies and identify critical factors that will require innovations in process technology, process integration and circuit-and-system design techniques. We also propose a scaling scheme for global lines to optimize the interconnect for a given application domain such as microprocessors, ASICs or memory. For local interconnect we demonstrate that cross-talk is the major challenge which can be addressed by selectively using larger drivers to reduce cross-talk noise when necessary.
---
paper_title: The test of time. Clock-cycle estimation and test challenges for future microprocessors

paper_content:

Even with aggressive new technology, the complex high-performance processor will require special design techniques and architectures to take advantage of new interconnect and transistor technology. Microprocessor on-chip clock frequencies of multiple GHz are predicted for future generations. However, significant development is necessary in technology, manufacturing, and design CAD tools in order to achieve the performance, manufacturability, and reliability desired for these future products. Design must own the test function. The ability of test to continue supporting at-speed testing has reached physical limits as well as cost impacts that will make testing a very high design priority.
---
paper_title: Impact of crosstalk on delay time and a hierarchy of interconnects

paper_content:

Impact of crosstalk on delay time and a hierarchy of interconnects is clarified. The delay time increase is induced by the almost same phenomenon as the crosstalk noise in short interconnects. For global interconnects, the delay time increase by crosstalk is enhanced and hence the delay time improvement trades off between the reduction of the lateral capacitance and the increase of wiring resistance. A multilevel interconnect scheme at each technology generation is further investigated considering the crosstalk effect. Delay time improvements by circuit techniques are discussed to reduce the delay time increase by crosstalk.
---
paper_title: Damascene integration of copper and ultra-low-k xerogel for high performance interconnects

paper_content:

Copper has been successfully integrated in ultra-low k xerogel in a damascene structure. Resistance was shown to decrease by 30% with lower capacitance, relative to an aluminum/oxide baseline. For an equivalent resistance, an aluminum/oxide architecture would have 29% higher capacitance than that demonstrated here. Copper in xerogel trenches shows great promise as the next generation metallization system.
---
paper_title: Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections

paper_content:

Experimental high-speed characterization and electrical modeling and simulation are presented for a six-layer Cu/SiO/sub 2/ on-chip wiring structure with 12.4-mm-long lines. Testing is performed over the temperature range -160/spl deg/C to +100/spl deg/C and across a 200-mm-diameter wafer. Very good agreement is reported between measured and simulated signal propagation and crosstalk waveforms. Modeling is done using a three-dimensional field solver and the R(f), L(f), and C matrices are used in a synthesized distributed network to simulate the signal behavior. Such a broadband analysis comprises the first comprehensive functional testing of a multi-layer Cu/SiO/sub 2/ wiring structure. The Cu interconnections are shown to be able to sustain 5.39 GHz microprocessor frequencies at T=+25/spl deg/C operation at a scaled wiring density increase of 17.5%, while comparable Al(Cu) wiring can achieve only 4.44 GHz (21.4% improvement).
---
paper_title: Rationale and challenges for optical interconnects to electronic chips

paper_content:

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.
---
paper_title: 3-D integration of MQW modulators over active submicron CMOS circuits: 375 Mb/s transimpedance receiver-transmitter circuit

paper_content:

We accomplish the integration of GaAs-AlGaAs multiple quantum well modulators directly on top of active silicon CMOS circuits. This enables optoelectronic VLSI circuits to be achieved and also allows the design and optimization of the CMOS circuits to proceed independently of the placement and the bonding of surface-normal optical modulators to the circuit. Using this technique, we demonstrate operation of a 0.8 micron CMOS transimpedance receiver-transmitter circuit at 375 Mb/s. >
---
paper_title: The projected power consumption of a wireless clock distribution system and comparison to conventional distribution systems

paper_content:

A wireless interconnect system has been proposed for global clock signal distribution. The system transmits and receives signals at 20 GHz or higher. The received signal is then amplified, frequency divided to 4 GHz or lower, and buffered to provide a clock signal to the local clock distribution system. An analysis comparing the projected power dissipation of a wireless clock distribution system to conventional grid-based and H-tree based distribution systems for 0.1 /spl mu/m generation microprocessors is performed, based on the total capacitive loading of the global distribution system. The results show that in terms of power dissipation, the wireless clock distribution system should be comparable to conventional systems.
---
paper_title: Multi-I/O and reconfigurable RF/wireless interconnect based on near field capacitive coupling and multiple access techniques

paper_content:

Future ULSI interconnect system demands extremely high data transmission rate, multi-I/O service, reconfigurable and fault-tolerant computing/processing architecture and full compatibility with mainstream silicon CMOS and MCM technologies. In this paper, we present a novel RF/wireless interconnect system that provides a unique solution to those system needs. Unlike the traditional "passive" metal interconnect, the "active" RF/wireless interconnect is based on near-field capacitive coupling, low loss and dispersion-free microwave signal transmission and modern multiple-access algorithms. The proposed RF/wireless interconnect promises ultra-broad bandwidth (up to 100 GHz), simultaneous multi-I/O communications (up to 50/50 I/O sub-channels per shared microwave transmission medium) and reconfigurable network (programmable based on Frequency and/or Code Division Multiple Access). As the first step to prove the feasibility, we have realized a 2/spl times/2 CDMA transceivers based on 0.35 /spl mu/m MOSIS CMOS process, which demonstrates the desired functions of capacitive coupling, guided wave transmission and reconfigurable multiple access.
---
paper_title: Wireless interconnection in a CMOS IC with integrated antennas

paper_content:

Improved RF capability and projected increase in die size [1] for CMOS circuits lead to the concept of wireless communications within and between chips. A potential application is wireless clock distribution, proposed as an alternative interconnect system capable of distributing high frequency clock signals at the speed of light using microwaves [2]. The wireless clock distribution system consists of a clock transmitter, located on or off chip, broadcasting a microwave global clock signal at frequencies greater than 15GHz, and a grid of integrated clock receivers. Figure 19.6.1 shows a block diagram of a clock receiver. The global clock signal is received using an integrated dipole antenna. The signal is then amplified using a low-noise amplifier (LNA), frequency divided down to the local clock frequency, buffered, and distributed to provide local clock signals. This IC operating at 7.4GHz, which integrates antennas and necessary receiver circuits in 0.25μm CMOS with five metal layers on p-substrates, is a first step towards realizing such a system.
---
paper_title: Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

paper_content:

This paper presents for the first time, multiple layers of silicon-on-insulator (MLSOI) device islands fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) techniques. MLSOI has the potential for ultra dense device integration. SOI device islands as small as 150 nm/spl times/150 nm, with thickness down to 40 nm have been fabricated. SOI device islands (5 /spl mu/m/spl times/500 /spl mu/m) in the second layer have shown no stacking faults in the 1290 islands inspected. To demonstrate the device quality material, fully depleted SOI (FD-SOI) P-MOSFET's were fabricated in the first layer SOI islands with gate lengths down to less than 170 nm. Typically they had low subthreshold leakage, below 0.2 pA//spl mu/m, and a subthreshold swing of 76 mV/dec was measured.
---
paper_title: Semiconductor wafer bonding : science and technology

paper_content:

Basics of Interactions Between Flat Surfaces. Influence of Particles, Surface Steps, and Cavities. Surface Preparation and Room-Temperature Wafer Bonding. Thermal Treatment of Bonded Wafer Pairs. Thinning Procedures. Electrical Properties of Bonding Interfaces. Stresses in Bonded Wafers. Bonding of Dissimilar Materials. Bonding of Structured Wafers. Mainstream Applications. Emerging and Future Applications. Index.
---
paper_title: Wafer bonding and layer splitting for microsystems

paper_content:

In advanced microsystems various types of devices (metal-oxide semiconductor field-effect transistors, bipolar transistors, sensors, actuators, microelectromechanical systems, lasers) may be on the same chip, some of which are 3D structures in nature. Therefore, not only materials combinations (integrated materials) are required for optimal device performance of each type but also process technologies for 3D device fabrication are essential. Wafer bonding and layer transfer are two of the fundamental technologies for the fabrication of advanced microsystems. In this review, the generic nature of both wafer bonding and hydrogen-implantation-induced layer splitting are discussed. The basic processes underlying wafer bonding and the layer splitting process are presented. Examples of bonding and layer splitting of bare or processed semiconductor and oxide wafers are described.
---
paper_title: Multiple layers of silicon-on-insulator for nanostructure devices

paper_content:

A new method for silicon-on-insulator (SOI) is presented that has very few stacking fault defects and produces multiple layers of single crystal silicon surrounded by thermal SiO2. The technique requires selective epitaxial growth, epitaxial lateral overgrowth, and chemical mechanical planarization to form SOI islands stacked in multiple layers. Islands of silicon as small as 150×150×40 nm thick were fabricated. Larger SOI islands in two SOI layers, with grown vertical interconnections between layers, were 5×500×0.1 μm. Only one stacking fault was observed in 85 000 μm2 of the first layer and none in the second layer. P-channel metal–oxide–semiconductor field effect transistors with gate lengths of less than ∼100 nm were fabricated in the thin SOI islands. They had normal current–voltage plot characteristics with less than 0.2 pA/μm of leakage current, illustrating the quality of the material in both SOI layers and at the silicon to thermal-oxide interfaces. The devices had measured subthreshold slopes of...
---
paper_title: System-level performance evaluation of three-dimensional integrated circuits

paper_content:

In this paper, the wire (interconnect)-length distribution of three-dimensional (3-D) integrated circuits (ICs) is derived using Rent's rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution). Two limiting cases of connectivity between logic gates on different device layers are examined by comparing the wire-length distribution and average and total wire-length. System performance metrics such as clock frequency, chip area, etc., are estimated using wire-length distribution, interconnect delay criteria, and simple models representing the cost or complexity for manufacturing 3-D ICs. The technology requirement for interconnects in 3-D integration is also discussed.
---
paper_title: Rationale and challenges for optical interconnects to electronic chips

paper_content:

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.
---
paper_title: Multi-I/O and reconfigurable RF/wireless interconnect based on near field capacitive coupling and multiple access techniques

paper_content:

Future ULSI interconnect system demands extremely high data transmission rate, multi-I/O service, reconfigurable and fault-tolerant computing/processing architecture and full compatibility with mainstream silicon CMOS and MCM technologies. In this paper, we present a novel RF/wireless interconnect system that provides a unique solution to those system needs. Unlike the traditional "passive" metal interconnect, the "active" RF/wireless interconnect is based on near-field capacitive coupling, low loss and dispersion-free microwave signal transmission and modern multiple-access algorithms. The proposed RF/wireless interconnect promises ultra-broad bandwidth (up to 100 GHz), simultaneous multi-I/O communications (up to 50/50 I/O sub-channels per shared microwave transmission medium) and reconfigurable network (programmable based on Frequency and/or Code Division Multiple Access). As the first step to prove the feasibility, we have realized a 2/spl times/2 CDMA transceivers based on 0.35 /spl mu/m MOSIS CMOS process, which demonstrates the desired functions of capacitive coupling, guided wave transmission and reconfigurable multiple access.
---

Title: High-Performance Interconnects: An Integration Overview

Section 1: Introduction
Description 1: This section provides an overview of the significance of interconnects in chips, the challenges posed by scaling, and the motivation behind high-performance interconnect development.

Section 2: High-Performance Interconnects
Description 2: This section discusses the evolution of interconnect technology, focusing on new materials and processes introduced to improve interconnect performance and reliability.

Section 3: Dual Damascene Copper
Description 3: This section details the process and advantages of dual damascene copper interconnects, including integration schemes and associated challenges.

Section 4: Low-Dielectrics
Description 4: This section explores various low-dielectric materials used in interconnect systems, their integration issues, and performance benefits.

Section 5: Copper Reliability
Description 5: This section addresses the reliability concerns associated with copper metallization and the strategies to mitigate these challenges.

Section 6: Alternative Interconnect Approaches
Description 6: This section introduces several alternative interconnect technologies such as optical, RF, and 3-D integration, and discusses their potential to overcome the limitations of traditional interconnects.

Section 7: Optical Interconnects
Description 7: This section elaborates on the advantages, challenges, and potential applications of optical interconnect technology in both interchip and intrachip contexts.

Section 8: RF Interconnects
Description 8: This section examines the viability, methods, and benefits of implementing RF interconnects as replacements for traditional global wires.

Section 9: 3-D Integration
Description 9: This section covers the concept and benefits of 3-D integration for reducing global wire lengths and enhancing system performance by adding vertical paths for connections.

Section 10: Migration to Alternate Interconnect Technologies
Description 10: This section discusses the scalability and readiness of alternative interconnect technologies and proposes a migration path for their implementation.

Section 11: Conclusion
Description 11: This section summarizes the ongoing challenges and potential solutions for interconnect systems in ULSI circuits, highlighting the importance of exploring novel interconnect technologies to meet future performance demands.