A Survey on Static Power Reduction Techniques in Asynchronous Circuits
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paper_title: Sleep Transistor Design and Implementation - Simple Concepts Yet Challenges To Be Optimum

paper_content:

Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency.
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paper_title: Circuit-level techniques to control gate leakage for sub-100nm CMOS

paper_content:

Although still negligible for state-of-the-art CMOS, gate leakage will become significant in the future for sub-100 nm technologies, due to the scaling of oxide thickness. We propose several circuit techniques to control gate leakage based on the fact that PMOS transistors with SiO/sub 2/ gate oxide have an order of magnitude smaller gate leakage than NMOS transistors in the same technology. First, we compare n-type domino with p-type domino circuits in terms of performance, leakage and switching power, and explore the different trade-offs between performance and power. Second, we compare n-type with p-type gating for MTCMOS to control the leakage during sleep. The proposed circuits are simulated for a predictive 70 nm CMOS technology with 10 /spl Aring/ gate oxide thickness and 1.2 V supply voltage.
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paper_title: Intrinsic leakage in low power deep submicron CMOS ICs

paper_content:

The large leakage currents in deep submicron transistors threaten future products and established quality manufacturing techniques. These include the ability to manufacture low power and battery operated products, and the ability to perform I/sub DDQ/ sensitive measurements with the significant ensuing benefits to test, reliability, and failure analysis. This paper reports transistor intrinsic leakage reduction as functions of bias point, temperature, source-well backbiasing, and lowered power supply (V/sub DD/). These device properties are applied to a test application that combines I/sub DDQ/ and F/sub MAX/ to establish a 2-parameter limit for distinguishing intrinsic and extrinsic (defect) leakages in microprocessors with high background I/sub DDQ/ leakage.
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paper_title: Activity-driven clock design for low power circuits

paper_content:

In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle times of the clocked elements. We propose a method of obtaining the switching activity patterns of the clocked circuits during the high level design process. We formulate three novel activity-driven problems. The objective of these problems is to minimize system's dynamic power consumption. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We solve the gate insertion problems with an exact algorithm employing the dynamic programming paradigm. Finally, we present experimental results that verify the effectiveness of our approach. Our work in this paper is a step in understanding how high level decisions (e.g. behavioral design) can affect a low level design (e.g. clock design).
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paper_title: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits

paper_content:

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
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paper_title: Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic

paper_content:

In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. The proposed power gating technique is implemented with minimal control overheads (one additional inverter per pipeline stage for driving PMOS Gating) and delay overheads (within 15% more than the conventional asynchronous-logic pipeline stage). Different types of gating configurations using only PMOS transistor (PMOS Gating), only NMOS transistor (NMOS Gating), and both types of transistors (Dual Gating) are examined and compared. The effectiveness of the proposed power gating technique to the Combinational Block therein with different data input rates is investigated. Based on the computer simulation results, we have found that ≫70% wasted power reduction (including both short-circuit and leakage powers) as compared to the conventional asynchronous-logic pipeline stage can be achieved with all gating configurations. In particular, Dual Gating achieves the best wasted power reduction of 86% for short-circuit power and 99% for leakage power @ 10Mbps input rate.
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paper_title: Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors

paper_content:

Asynchronous self-timed circuits which tolerate any delay variations are a feasible solution to timing-related problems while they suffer large energy dissipation due to large amount of their circuits. In future process technologies, it has been recognized that leakage power is a large factor in the total power dissipation. In this paper, we propose two leakage power reduction methods for m-out-of-n encoded circuits which operate based on the four-phase handshake protocol using multi-threshold-voltage transistors. One method is based on the traditional power gating technique which reduces leakage power by shutting off the power of idle circuits. Another method is to apply high-threshold-voltage transistors into the off-state transistors whose gate input signals are inactive in the idle phase. The evaluation results show that about 94% and 81% of the leakage power in the idle phase can be reduced.
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paper_title: Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic

paper_content:

In this paper, a fine-grained power gating technique for an asynchronous-logic pipeline stage is proposed using locally controlled gating transistors. The proposed power gating technique is implemented with minimal control overheads (one additional inverter per pipeline stage for driving PMOS Gating) and delay overheads (within 15% more than the conventional asynchronous-logic pipeline stage). Different types of gating configurations using only PMOS transistor (PMOS Gating), only NMOS transistor (NMOS Gating), and both types of transistors (Dual Gating) are examined and compared. The effectiveness of the proposed power gating technique to the Combinational Block therein with different data input rates is investigated. Based on the computer simulation results, we have found that ≫70% wasted power reduction (including both short-circuit and leakage powers) as compared to the conventional asynchronous-logic pipeline stage can be achieved with all gating configurations. In particular, Dual Gating achieves the best wasted power reduction of 86% for short-circuit power and 99% for leakage power @ 10Mbps input rate.
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paper_title: Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction

paper_content:

Asynchronous circuits are well-known for their benefits in terms of dynamic power savings, because asynchronous logic does not switch when inactive. Nevertheless, in deep-submicron technologies, leakage currents have become an increasing issue, and thus asynchronous circuits need to focus on static power consumption reduction. In this paper, we propose an innovative way to detect incoming asynchronous activity. Associated to an automatic power regulation, it efficiently reduces the supply voltage and thus both energy per op. and leakage currents. The proposed technique has been applied to an asynchronous network-on-chip node, and successfully implemented in a STM 65 nm technology.
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paper_title: Static Power Reduction Techniques for Asynchronous Circuits

paper_content:

Power gating techniques are effective in mitigatingleakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two representative techniques, Cut-Off and Zig-Zag Cut-Off [1], and find that they offer an average of 80% and 20% in power savings, respectively, for asynchronous circuit families. We also present a new zero-delay (ZDRTO) wakeup technique for power gated asynchronous pipelines, which leverages the robustness of asynchronous circuits to delays and supply voltage variations.Our ZDRTO technique offers a tradeoff between wakeup timeand static power reduction, making it suitable for power gating pipelines with low-duty cycle, bursty usage patterns.
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paper_title: Sleep Transistor Design and Implementation - Simple Concepts Yet Challenges To Be Optimum

paper_content:

Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency.
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Title: A Survey on Static Power Reduction Techniques in Asynchronous Circuits

Section 1: Introduction
Description 1: This section introduces the importance of reducing power consumption in chips, distinguishing between static and dynamic power, and highlights the role of asynchronous circuits in power gating.

Section 2: The Conventional Asynchronous Logic Pipeline
Description 2: This section discusses the conventional asynchronous logic pipeline and how sleep transistors are used to manage power by turning them on and off based on data processing.

Section 3: Automatic Power Regulation Based On Asynchronous Activity Detection
Description 3: This section presents an innovative solution for detecting incoming asynchronous activity and automatically regulating power to reduce leakage power.

Section 4: Zero-Delay Ripple Turn On Power Gating (ZDRTO)
Description 4: This section describes the ZDRTO power gating technique, which utilizes a zero-delay wakeup scheme in pipelined computation to efficiently manage power gating in asynchronous circuits.

Section 5: Asynchronous Adiabatic Logic
Description 5: This section explains the concept of asynchronous adiabatic logic (AAL) and its implementation, focusing on techniques to enhance power efficiency in the circuit.

Section 6: Asynchronous Fine-Grained Power Gated Logic With PCR
Description 6: This section discusses the AFPL approach, which uses fine-grain power gating combined with PCR to reduce leakage power during idle times and improve power efficiency.

Section 7: Comparative Study
Description 7: This section provides a comparative study of different static power reduction techniques discussed earlier, examining their effectiveness and limitations.

Section 8: Conclusion
Description 8: This section summarizes the survey, emphasizing the importance of reducing static power in sub-micron and nano technologies and the effectiveness of power gating techniques.