Hardware Engines for Bus Encryption: A Survey of Existing Techniques
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paper_title: Enhancing security in the memory management unit

paper_content:

We propose an hardware solution to several security problems that are difficult to solve on classical processor architectures, like licensing, electronic commerce, or software privacy. The memory management unit which provides multitasking and virtual memory support is extended and given a third purpose: to supply strong hardware security support for the software layer. The principle of this enhanced device, that we call a Security Management Unit (or SMU), is based on ciphered program execution and access control. It is composed of a pipelined block ciphering/deciphering unit, an infernal permanent memory and logic control, whose interaction is explained in this paper.
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paper_title: Tamper resistance mechanisms for secure embedded systems

paper_content:

Security is a concern in the design of a wide range of embedded systems. Extensive research has been devoted to the development of cryptographic algorithms that provide the theoretical underpinnings of information security. Functional security mechanisms, such as security protocols, suitably employ these mathematical primitives in order to achieve the desired security objectives. However, functional security mechanisms alone cannot ensure security, since most embedded systems present attackers with an abundance of opportunities to observe or interfere with their implementation, and hence to compromise their theoretical strength. This paper surveys various tamper or attack techniques, and explains how they can be used to undermine or weaken security functions in embedded systems. Tamper-resistant design refers to the process of designing a system architecture and implementation that is resistant to such attacks. We outline approaches that have been proposed to design tamper-resistant embedded systems, with examples drawn from recent commercial products.
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paper_title: Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP

paper_content:

A widely used bus-encryption microprocessor is vulnerable to a new practical attack. This type of processor decrypts on-the-fly while fetching code and data, which are stored in RAM only in encrypted form. The attack allows easy, unauthorized access to the decrypted memory content.
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paper_title: AEGIS: architecture for tamper-evident and tamper-resistant processing

paper_content:

We describe the architecture for a single-chip AEGIS processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all components external to the processor, such as memory, are untrusted. We show two different implementations. In the first case, the core functionality of the operating system is trusted and implemented in a security kernel. We also describe a variant implementation assuming an untrusted operating system. AEGIS provides users with tamper-evident, authenticated environments in which any physical or software tampering by an adversary is guaranteed to be detected, and private and authenticated tamper-resistant environments where additionally the adversary is unable to obtain any information about software or data by tampering with, or otherwise observing, system operation. AEGIS enables many applications, such as commercial grid computing, secure mobile agents, software licensing, and digital rights management.Preliminary simulation results indicate that the overhead of security mechanisms in AEGIS is reasonable.
---
paper_title: Enhancing security in the memory management unit

paper_content:

We propose an hardware solution to several security problems that are difficult to solve on classical processor architectures, like licensing, electronic commerce, or software privacy. The memory management unit which provides multitasking and virtual memory support is extended and given a third purpose: to supply strong hardware security support for the software layer. The principle of this enhanced device, that we call a Security Management Unit (or SMU), is based on ciphered program execution and access control. It is composed of a pipelined block ciphering/deciphering unit, an infernal permanent memory and logic control, whose interaction is explained in this paper.
---
paper_title: Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP

paper_content:

A widely used bus-encryption microprocessor is vulnerable to a new practical attack. This type of processor decrypts on-the-fly while fetching code and data, which are stored in RAM only in encrypted form. The attack allows easy, unauthorized access to the decrypted memory content.
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Title: Hardware Engines for Bus Encryption: A Survey of Existing Techniques

Section 1: Introduction
Description 1: Write about the increasing range of services provided by embedded systems and the need for confidentiality, particularly focusing on the security of processor-memory buses and cryptographic measures.

Section 2: Software confidentiality
Description 2: Discuss the issues of content protection for on-demand software downloading services and the secure channel establishment over non-secure networks, elaborating on session key encryption and potential risks.

Section 3: Cryptosystem SOC context
Description 3: Explain the importance of selecting a cryptosystem based on system specifications, exploring the tradeoff between security and performance.

Section 4: Asymmetric vs Symmetric cryptography
Description 4: Compare asymmetric and symmetric cryptography, detailing their operations, performance requirements, and suitability for different contexts within embedded systems.

Section 5: Attack classification
Description 5: Classify different types of attacks on secure embedded systems, particularly focusing on non-invasive attacks and bus probing, and discuss case studies involving these types of attacks.

Section 6: State of the art
Description 6: Present an overview of existing solutions for bus encryption, including both industrial and academic proposals, highlighting their approaches, strengths, and weaknesses.

Section 7: Various solutions considered
Description 7: Explore alternative solutions for encryption units, including potential performance enhancements through compression, and discuss their implications for security and system performance.

Section 8: Conclusion and perspectives
Description 8: Summarize the feasibility of designing secure systems with minimal performance loss, and propose future directions for integrating compression with encryption and addressing data integrity issues.