Reconfigurable Instruction Set Processors: A survey
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paper_title: Computer Architecture: A Quantitative Approach

paper_content:

This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high-performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and Web technologies, and high-performance computing.
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paper_title: Memory interfacing and instruction specification for reconfigurable processors

paper_content:

As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory. This paper describes the architecture of a custom computing machine that overcomes the interconnection bottleneck by closely integrating a fixed-logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip-98. The OneChip-98 system has a seamless programming model that enables the programmer to easily specify instructions without additional complex instruction decoding hardware. As well, there is a simple scheme for mapping instructions to the corresponding programming bits. To allow the processor and the reconfigurable array to execute concurrently, the programming model utilizes a novel memory-consistency scheme implemented in the hardware. To evaluate the feasibility of the OneChip-98 architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system. For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over 30 times that of a stand-alone state-of-the-art processor.
---
paper_title: Processor reconfiguration through instruction-set metamorphosis

paper_content:

The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described. The PRISM approach adapts the configuration and fundamental operations of a core processing system to the computationally intensive portions of a targeted application. PRISM-1, an initial prototype system, is described, and experimental results that demonstrate the benefits of the PRISM concept are presented. >
---
paper_title: OneChip: an FPGA processor with reconfigurable logic

paper_content:

This paper describes a processor architecture called OneChip, which combines a fixed-logic processor core with reconfigurable logic resources. Using the programmable components of this the performance of speed-critical can be improved by customizing OneChip's execution units, or flexibility can be added to the glue logic interfaces of embedded controller applications. OneChip eliminates the shortcomings of other custom compute machines by tightly integrating its reconfigurable resources into a MIPS-like processor. Speedups of close to 50 over strict software implementations on a MIPS R4400 are achievable for computing the DCT.
---
paper_title: Garp: a MIPS processor with a reconfigurable coprocessor

paper_content:

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.
---
paper_title: PipeRench: a coprocessor for streaming multimedia acceleration

paper_content:

Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup.
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paper_title: The NAPA adaptive processing architecture

paper_content:

The National Adaptive Processing Architecture (NAPA) is a major effort to integrate the resources needed to develop teraops class computing systems based on the principles of adaptive computing. The primary goals for this effort include: (1) the development of an example NAPA component which achieves an order of magnitude cost/performance improvement compared to traditional FPGA based systems, (2) the creation of a rich but effective application development environment for NAPA systems based on the ideas of compile time functional partitioning and (3) significantly improve the base infrastructure for effective research in reconfigurable computing. This paper emphasizes the technical aspects of the architecture to achieve the first goal while illustrating key architectural concepts motivated by the second and third goals.
---
paper_title: PipeRench: a coprocessor for streaming multimedia acceleration

paper_content:

Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup.
---
paper_title: Memory interfacing and instruction specification for reconfigurable processors

paper_content:

As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory. This paper describes the architecture of a custom computing machine that overcomes the interconnection bottleneck by closely integrating a fixed-logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip-98. The OneChip-98 system has a seamless programming model that enables the programmer to easily specify instructions without additional complex instruction decoding hardware. As well, there is a simple scheme for mapping instructions to the corresponding programming bits. To allow the processor and the reconfigurable array to execute concurrently, the programming model utilizes a novel memory-consistency scheme implemented in the hardware. To evaluate the feasibility of the OneChip-98 architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system. For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over 30 times that of a stand-alone state-of-the-art processor.
---
paper_title: A dynamic instruction set computer

paper_content:

A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space.
---
paper_title: Memory interfacing and instruction specification for reconfigurable processors

paper_content:

As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory. This paper describes the architecture of a custom computing machine that overcomes the interconnection bottleneck by closely integrating a fixed-logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip-98. The OneChip-98 system has a seamless programming model that enables the programmer to easily specify instructions without additional complex instruction decoding hardware. As well, there is a simple scheme for mapping instructions to the corresponding programming bits. To allow the processor and the reconfigurable array to execute concurrently, the programming model utilizes a novel memory-consistency scheme implemented in the hardware. To evaluate the feasibility of the OneChip-98 architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system. For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over 30 times that of a stand-alone state-of-the-art processor.
---
paper_title: The Chimaera reconfigurable functional unit

paper_content:

By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself with direct access to the host processor's register file, the system enables the creation of multi-operand instruction and a speculative execution model key to high performance, general-purpose reconfigurable computing. It also supports multi-output functions, and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, this system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.
---
paper_title: A dynamic instruction set computer

paper_content:

A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space.
---
paper_title: Memory interfacing and instruction specification for reconfigurable processors

paper_content:

As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory. This paper describes the architecture of a custom computing machine that overcomes the interconnection bottleneck by closely integrating a fixed-logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip-98. The OneChip-98 system has a seamless programming model that enables the programmer to easily specify instructions without additional complex instruction decoding hardware. As well, there is a simple scheme for mapping instructions to the corresponding programming bits. To allow the processor and the reconfigurable array to execute concurrently, the programming model utilizes a novel memory-consistency scheme implemented in the hardware. To evaluate the feasibility of the OneChip-98 architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system. For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over 30 times that of a stand-alone state-of-the-art processor.
---
paper_title: Address calculation for retargetable compilation and exploration of instruction-set architectures

paper_content:

The advent of parallel executing address calculation units (ACUs) in digital signal processor (DSP) and application specific instruction-set processor (ASIP) architectures has made a strong impact on an application's ability to efficiently access memories. Unfortunately, successful compiler techniques which map high-level language data constructs to the addressing units of the architecture have lagged far behind. Since access to data is often the most demanding task in DSP, this mapping can be the most crucial function of the compiler. This paper introduces a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. The ArrSyn utility is designed to be used either as an enhancement to an existing dedicated compiler or as an aid for architecture exploration.
---
paper_title: Specifying and Compiling Applications for RAPID

paper_content:

Efficient, deeply pipelined implementations exist for a wide variety of important computation-intensive applications, and many special-purpose hardware machines have been built that take advantage of these pipelined computation structures. While these implementations achieve high performance, this comes at the expense of flexibility. On the other hand, flexible architectures proposed thus far have not been very efficient. RaPiD is a reconfigurable pipelined datapath architecture designed to provide a combination of performance and flexibility for a variety of applications. It uses a combination of static and dynamic control to efficiently implement pipelined computations. This control, however, is very complicated; specifying a computation's control circuitry directly would be prohibitively difficult. This paper describes how specifications of a pipelined computation in a suitably high-level language are compiled into the control required to implement that computation in the RaPiD architecture. The compiler extracts a statically configured datapath from this description, identifies the dynamic control signals required to execute the computation, and then produces the control program and decoding structure that generates these dynamic control signals.
---
paper_title: The Chimaera reconfigurable functional unit

paper_content:

By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself with direct access to the host processor's register file, the system enables the creation of multi-operand instruction and a speculative execution model key to high performance, general-purpose reconfigurable computing. It also supports multi-output functions, and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, this system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.
---
paper_title: Rapid System Prototyping for High Performance Reconfigurable Computing

paper_content:

This paper proposes a soft-reconfigurable coarse grain platform, called J-platform, based on a very few types of computational cells, and shows how a range of advanced applications can be mapped for achieving high performance. Two very flexible cells are proposed that account for the versatility of the approach. These are the MA_PLUS, which is an enhanced Multiply-Add cell, and the UNL, a Universal NonLinear cell. These two cells, together, provide an unprecedented capability for ‘coarse-grain reconfigurable computing,’ as discussed in the paper. Although the applications of the platform range from FIR filtering of images to large-scale inverse problems, the paper demonstrates mapping of two specific advanced problems, namely (1) Reconstruction of Computerized Tomography images from fan beam projections, and (2) Color Conversion of Video from the RGB to HSI domains. Speed-up by factors of 20 or more over today's work stations is estimated.
---
paper_title: OneChip: an FPGA processor with reconfigurable logic

paper_content:

This paper describes a processor architecture called OneChip, which combines a fixed-logic processor core with reconfigurable logic resources. Using the programmable components of this the performance of speed-critical can be improved by customizing OneChip's execution units, or flexibility can be added to the glue logic interfaces of embedded controller applications. OneChip eliminates the shortcomings of other custom compute machines by tightly integrating its reconfigurable resources into a MIPS-like processor. Speedups of close to 50 over strict software implementations on a MIPS R4400 are achievable for computing the DCT.
---
paper_title: Garp: a MIPS processor with a reconfigurable coprocessor

paper_content:

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.
---
paper_title: A dynamic instruction set computer

paper_content:

A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space.
---
paper_title: PipeRench: a coprocessor for streaming multimedia acceleration

paper_content:

Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup.
---
paper_title: Architecture of FPGAs and CPLDs: A Tutorial

paper_content:

This paper provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs). We first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips, and give examples of applications of each type of device.
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paper_title: DPGA-coupled microprocessors: commodity ICs for the early 21st Century

paper_content:

During the past decade, the microprocessor has become a key commodity component for building all kinds of computational systems. During this time frame, large reconfigurable logic arrays have exploited the same advances in IC fabrication technology to emerge as viable system building blocks. Looking at both the technology prospects and application requirements, there is compelling evidence that microprocessors with integrated reconfigurable logic arrays will be a primary building block for future computing systems. In this paper, we look at the role such components can play in building high-performance and economical systems, as well as the ripe technological outlook. We note how the tight integration of reconfigurable logic into the processor can overcome some of the major limitations of contemporary attached reconfigurable computer engines. We specifically consider the use of integrated dynamically programmable gate array (DPGA) structures for the configurable logic, and examine the advantages that rapid reconfiguration provides in this application. >
---
paper_title: Architecture of FPGAs and CPLDs: A Tutorial

paper_content:

This paper provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs). We first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips, and give examples of applications of each type of device.
---
paper_title: A high-performance microarchitecture with hardware-programmable functional units

paper_content:

This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC—a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language compilation techniques that are needed to successfully build PRISC and, we present performance results from a proof-of-concept study. With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor performance on the SPECint92 benchmarks.
---
paper_title: A dynamic instruction set computer

paper_content:

A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space.
---
paper_title: Safe and protected execution for the Morph/AMRM reconfigurable processor

paper_content:

Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase performance. In the Morph/AMRM system we are exploring the addition of reconfigurable logic, deeply integrated with the processor core, employing the reconfigurability to manage the cache, datapath, and pipeline resources more effectively. However, integration of reconfigurable logic introduces significant protection and safety challenges for microprocess execution. We analyze the protection structures in a state of the art microprocessor core (R10000), identifying the few critical logic blocks and demonstrating that the majority of the logic in the processor core can be safely reconfigured. Subsequently, we propose a protection architecture for the Morph/AMRM reconfigurable processor which enable nearly the full range of power of reconfigurability in the processor core while requiring only a small number of fixed logic features which to ensure safe, protected multiprocess execution.
---
paper_title: Processor reconfiguration through instruction-set metamorphosis

paper_content:

The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described. The PRISM approach adapts the configuration and fundamental operations of a core processing system to the computationally intensive portions of a targeted application. PRISM-1, an initial prototype system, is described, and experimental results that demonstrate the benefits of the PRISM concept are presented. >
---
paper_title: Instruction-Level Parallelism for Reconfigurable Computing

paper_content:

Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor. This paper will review these techniques in their original context, describe how we have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language.
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paper_title: A C compiler for a processor with a reconfigurable functional unit

paper_content:

This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that can extract computations from applications to put into the RFU. The results show that large instruction sequences can be created and extracted by these techniques. An average speedup of 2.6 is achieved over a set of benchmarks.
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paper_title: Mapping Methods for the Chimaera Reconfigurable Functional Unit

paper_content:

In this paper we examine how the Chimaera Reconfigurable Functional Unit can be used to speed up program execution. We investigate a graphical skeletonization (object thinning) algorithm for this purpose. First, we will show how an assembly language post-processor or very primitive compiler could automate the use of the Chimaera system. Second, we will demonstrate how a more sophisticated compiler can achieve superior performance though more complicated hardware mappings. Last, we will present the results of an implementation of the algorithm designed specifically for Chimaera to obtain the greatest speedups.
---
paper_title: Processor reconfiguration through instruction-set metamorphosis

paper_content:

The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described. The PRISM approach adapts the configuration and fundamental operations of a core processing system to the computationally intensive portions of a targeted application. PRISM-1, an initial prototype system, is described, and experimental results that demonstrate the benefits of the PRISM concept are presented. >
---
paper_title: Instruction-Level Parallelism for Reconfigurable Computing

paper_content:

Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor. This paper will review these techniques in their original context, describe how we have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language.
---
paper_title: A C compiler for a processor with a reconfigurable functional unit

paper_content:

This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that can extract computations from applications to put into the RFU. The results show that large instruction sequences can be created and extracted by these techniques. An average speedup of 2.6 is achieved over a set of benchmarks.
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paper_title: 3-D Floorplanning : Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems

paper_content:

Advances in programmable hardware have led to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are still many challenging problems to be solved before any practical general-purpose reconfigurable system is built. One fundamental problem is the placement of the modules on the reconfigurable functional unit (RFU). In reconfigurable systems, we are interested both in online placement, where the arrival time of tasks is determined at run time and is not known a priori, and in offline placement, in which the schedule is known at compile time. In the case of offline placement, we are willing to spend more time during compile time to find a compact floorplan for the RFU modules and utilize the RFU area more efficiently. In this paper, we present offline placement algorithms based on simulated annealing and greedy methods, and show the superiority of their placements over the ones generated by an online algorithm.
---
paper_title: A C compiler for a processor with a reconfigurable functional unit

paper_content:

This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that can extract computations from applications to put into the RFU. The results show that large instruction sequences can be created and extracted by these techniques. An average speedup of 2.6 is achieved over a set of benchmarks.
---
paper_title: Fast compilation for pipelined reconfigurable fabrics

paper_content:

In this paper we describe a compiler which quickly synthesizes high quality pipelined datapaths for pipelined reconfigurable devices. The compiler uses the same internal representation to perform synthesis, module generation, optimization, and place and route. The core of the compiler is a linear time place and route algorithm more than two orders of magnitude faster than traditional CAD tools. The key behind our approach is that we never backtrack, rip-up, or re-route. Instead, the graph representing the computation is preprocessed to guarantee routability by inserting lazy noops. The preprocessing steps provides enough information to make a greedy strategy feasible. The compilation speed is approximately 3000 bit-operations/second (on a PII/400Mhz) for a wide range of applications. The hardware utilization averages 60% on the target device, PipeRench.
---
paper_title: Specifying and Compiling Applications for RAPID

paper_content:

Efficient, deeply pipelined implementations exist for a wide variety of important computation-intensive applications, and many special-purpose hardware machines have been built that take advantage of these pipelined computation structures. While these implementations achieve high performance, this comes at the expense of flexibility. On the other hand, flexible architectures proposed thus far have not been very efficient. RaPiD is a reconfigurable pipelined datapath architecture designed to provide a combination of performance and flexibility for a variety of applications. It uses a combination of static and dynamic control to efficiently implement pipelined computations. This control, however, is very complicated; specifying a computation's control circuitry directly would be prohibitively difficult. This paper describes how specifications of a pipelined computation in a suitably high-level language are compiled into the control required to implement that computation in the RaPiD architecture. The compiler extracts a statically configured datapath from this description, identifies the dynamic control signals required to execute the computation, and then produces the control program and decoding structure that generates these dynamic control signals.
---
paper_title: Embedded Software in Real-Time Signal Processing Systems: Design Technologies

paper_content:

The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multimedia, and consumer electronics industries. A companion paper (Paulin et al., 1997) presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of suitable design technology remains a significant obstacle in the development of such systems. One of the key requirements is more efficient software compilation technology. Especially in the case of fixed-point digital signal processor (DSP) cores, it is often cited that commercially available compilers are unable to take full advantage of the architectural features of the processor. Moreover, due to the shorter lifetimes and the architectural specialization of many processor cores, processor designers are often compelled to neglect the issue of compiler support. This situation has resulted in an increased research activity in the area of design tool support for embedded processors. This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors.
---
paper_title: The Garp architecture and C compiler

paper_content:

Various projects and products have been built using off-the-shelf field-programmable gate arrays (FPGAs) as computation accelerators for specific tasks. Such systems typically connect one or more FPGAs to the host computer via an I/O bus. Some have shown remarkable speedups, albeit limited to specific application domains. Many factors limit the general usefulness of such systems. Long reconfiguration times prevent the acceleration of applications that spread their time over many different tasks. Low-bandwidth paths for data transfer limit the usefulness of such systems to tasks that have a high computation-to-memory-bandwidth ratio. In addition, standard FPGA tools require hardware design expertise which is beyond the knowledge of most programmers. To help investigate the viability of connected FPGA systems, the authors designed their own architecture called Garp and experimented with running applications on it. They are also investigating whether Garp's design enables automatic, fast, effective compilation across a broad range of applications. They present their results in this article.
---

Title: Reconfigurable Instruction Set Processors: A Survey

Section 1: INTRODUCTION
Description 1: This section introduces the concept of embedded systems, discusses the balance between hardware and software components, and provides a detailed overview of Application Specific Instruction Set Processors (ASIPs) and Reconfigurable Instruction Set Processors (RISPs).

Section 2: HARDWARE DESIGN
Description 2: This section covers the hardware design aspects of RISPs, focusing on interfacing, coupling of reconfigurable logic, instruction types, coding, operands, memory access, and the design of reconfigurable logic itself.

Section 3: Interfacing of the Reconfigurable Unit
Description 3: In this section, the different methods in which the processor communicates with the reconfigurable logic are discussed, detailing the internal structure and coupling mechanisms.

Section 4: Coupling the Processor to the Reconfigurable Logic
Description 4: This section provides a taxonomy of reconfigurable processors and discusses the performance impact based on the positioning of the reconfigurable logic relative to the microprocessor.

Section 5: Instruction Types
Description 5: This section explains the different types of instructions that can be implemented on RFUs, highlighting stream-based and custom instructions.

Section 6: Instruction Coding
Description 6: This section describes how reconfigurable instructions are identified and specified in instruction words, including memory address and instruction identifiers.

Section 7: Operands
Description 7: This section details how operands are specified and passed to the RFU, covering hardwired, flexible, and shared access methods.

Section 8: Memory Access
Description 8: This section covers the techniques for providing memory access to the RFU, including address generation and direct memory bus connections.

Section 9: Reconfigurable Logic Design
Description 9: This section focuses on the design of the reconfigurable logic, discussing processing, configuration, and interconnect layers.

Section 10: Processing Layer
Description 10: This section describes the elements that perform calculations in the reconfigurable logic, highlighting the granularity of logic blocks.

Section 11: Configuration Layer
Description 11: This section discusses the configuration layer in the RFU, detailing the types of configurability and techniques to minimize reconfiguration time.

Section 12: Interconnect Layer
Description 12: This section explains the interconnect layer, detailing intrasegment and intersegment interconnects and their impact on performance.

Section 13: Configuration Controller
Description 13: This section describes the configuration controller's role in managing and loading instructions, including techniques to reduce reconfiguration times and improve performance.

Section 14: Interrupts
Description 14: This section addresses the issue of interrupt processing with reconfigurable instructions, ensuring precise handling and maintaining execution behavior.

Section 15: SOFTWARE TOOLS
Description 15: This section discusses software tools needed to generate code for RISPs, covering high-level language compilers, optimization focusing, instruction creation, selection/assignment, synthesis/compilation, retargetable backend, and code transformations.

Section 16: Optimization Focusing
Description 16: This section covers techniques for filtering parts of the code to optimize compilation times by manual, static, or dynamic identification.

Section 17: Instruction Creation
Description 17: This section describes the process of creating new instructions for RISPs on a per block basis, covering identification, parameter estimation, and performance check.

Section 18: Identification
Description 18: This section focuses on techniques for identifying instruction candidates using data flow and customized techniques, often involving code transformations.

Section 19: Parameter Estimation (Instruction Characterization)
Description 19: This section explains the process of estimating instruction parameters such as latency and size without full synthesis.

Section 20: Performance Check
Description 20: This section details the process of verifying if new instructions improve performance by comparing compiled block results.

Section 21: Simplifications to Instruction Creation
Description 21: This section discusses simplified methods for instruction creation, including library programming and programmer identification.

Section 22: Instruction Selection/Assignment (Configuration Scheduling)
Description 22: This section explains how the compiler selects and schedules instructions for execution, optimizing globally or locally based on reconfiguration capabilities.

Section 23: Instruction Synthesis/Compilation
Description 23: This section describes synthesizing the configuration string for the RFU, detailing techniques used for different granularities of reconfigurable logic.

Section 24: Retargetable Backend
Description 24: This section covers the need for a retargetable backend in the compiler to adapt to changing instruction sets.

Section 25: Code Transformations
Description 25: This section discusses various code transformations that improve performance by reducing reconfiguration times and optimizing instruction locality.

Section 26: CONCLUSIONS
Description 26: This section summarizes the paper, reflecting on the challenges and potential of RISP design and the crucial role of software tools in maximizing their performance and viability.