Wave-pipelining: A tutorial and research survey
---
paper_title: Synchronization of pipelines

paper_content:

A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pipeline circuits is defined as a function of the clock schedule and degree of wave pipelining. The authors then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. It is shown that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking is derived. The authors compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization. >
---
paper_title: A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency

paper_content:

A bipolar LSI chip which achieves 2.5 times the normal clock frequency by means of wave pipelining without the use of additional storage elements is described. In wave pipelining, multiple coherent waves of data are placed between storage elements by clocking the circuit faster than the propagation delay of the combinational logic. If all the propagation paths from the combinational circuit inputs to outputs have approximately the same delay, each wave propagates uniformly to the outputs without interfering with adjacent waves. The wave pipelining concept has been tested using a demonstration chip. Compared to an implementation using ordinary pipelining, a wave-pipelined circuit reduces the latency, area, and clock distribution required by pipeline registers or latches.<<ETX>>
---
paper_title: Comparative Studies of Pipelined Circuits

paper_content:

Wave pipelining is an attractive technique used in high-speed computer systems to speed-up pipeline rate without partitioning a system into pipeline stages. Although recent implemetations have reported very high-speed operation rates, a real evaluation of the advantages and disadvantages of wave pipelining requires a comparative study with other techniques, in particular the understanding of the trade-offs between conventional and wave pipelining is very important. This study is an attempt to provide approximate models which can be used as first-order tools for comparative study or sensitivity analysis of conventional and wave pipelined systems with different overheads. The models presented here are for subsystem-level pipelines. The product Latency x Cycle-Time is used as a measure of performance and is evaluated as a function of all the parameters of a design, such as the propagation delay of the combinational logic, the data skew resulting from the difference between maximum and minimum propagation delays through various logic paths, rise and fall time, the setup time, hold time, and propagation delay through registers, and the uncontrollable clock skew. In this way, an analytical basis is provided for a comparison between different approaches and for optimizations.
---
paper_title: Inserting active delay elements to achieve wave pipelining

paper_content:

Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. Due to limits and variations in fabrication, the clock frequency can be increased by a factor of 2 to 3 by using the best available design methods. The authors present algorithms that will equalize delays automatically by inserting a minimal number of active delay elements to lengthen short paths. This method can be combined with delay balancing by adjusting gate speeds to design wave-pipelined circuits. >
---
paper_title: Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences

paper_content:

Algorithms to automatically realize delays in combinational logic circuits to achieve wave pipelining are presented. The algorithms adjust gate speeds and insert a minimal number of active delay elements to balance input-output path lengths in a circuit. For both normal and wave-pipelined circuits, the algorithms also optimally minimize power under delay constraints. The authors analyze the algorithms and comment on their implementation. They report experimental results, including the design and testing of a 63-bit population counter in CML bipolar technology. A brief analysis of circuit technologies shows that CML and super-buffered ECL without stacked structures are well suited for wave pipelining because they have uniform delay. Static CMOS and ordinary ECL including stacked structures and emitter-followers do have some delay variations. A high degree of wave pipelining is still possible in those technologies if special design techniques are followed. >
---
paper_title: Clock period minimization with wave pipelining

paper_content:

A method using a linear program for adjusting clock delays in individual flip-flops to minimize the clock period through the use of wave pipelining is discussed. Edge-triggered flip-flops are used as the circuit memory elements, and controlled delays are introduced in the time of clock signal arrivals at these elements. Constraints that relate the logic path delays from pairs of input flip-flops are derived. These constraints, in addition to known constraints relating input and output flip-flops, prevent destructive logic signal propagation interference. It is shown that in circuits without feedback the clock period reduction is limited by the shortest paths in the logic and the required signal separation between signals of distinct cycles. Application of this technique to logic with feedback is discussed. >
---
paper_title: Wave-domino logic: theory and applications

paper_content:

Wave-pipelining has been investigated extensively as a design method to increase clock frequencies of digital systems. Data are clocked into a combinational circuit with a clock period smaller than the latency of the combinational block. To achieve the minimal period, collisions among waves must be avoided by balancing the delay paths from inputs to all intermediate nodes and outputs. Process variation and environmental influences have also to be taken into account in the design. While previous research has explored wave-pipelining of ECL and static CMOS circuits, we concentrate on CMOS domino circuits because of their compact layouts and shorter delay time. A timing model and constraints are given for deriving the minimal period. Special partitioning and delay assignment problems are discussed. Process variation is modeled by characterizing the current drive capabilities of N and P devices. A test chip has been designed, fabricated, and tested which uses a novel form of domino-logic to implement a wave-domino multiplier, sum of product trees, and a parity checker. >
---
paper_title: Minimum padding to satisfy short path constraints

paper_content:

Combinational circuits are often embedded in synchronous designs with memory elements at the input and output ports. A performance metric for a circuit is the cycle time of the clock signal. Correct circuit operation requires that all paths have a delay that lies between an upper bound and a lower bound. Traditional approaches in delay optimization for combinational circuits have dealt with methods to decrease the delay of the longest path. We address the issue of satisfying the lower bound constraints. Such a problem also arises in wave pipelining of circuits. We propose to handle short path constraints as a post processing step after traditional delay optimization techniques. There are two issues presented in this paper. We first discuss necessary and sufficient conditions for successful delay insertion without increasing delays of any long paths. In the second part, we present a naive approach to padding delays (greedy heuristic) and an algorithm based on linear programming. We describe an application of the theory to wave pipelining of circuits. Results are presented on a set of benchmark circuits, using two delay models.
---
paper_title: Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences

paper_content:

Algorithms to automatically realize delays in combinational logic circuits to achieve wave pipelining are presented. The algorithms adjust gate speeds and insert a minimal number of active delay elements to balance input-output path lengths in a circuit. For both normal and wave-pipelined circuits, the algorithms also optimally minimize power under delay constraints. The authors analyze the algorithms and comment on their implementation. They report experimental results, including the design and testing of a 63-bit population counter in CML bipolar technology. A brief analysis of circuit technologies shows that CML and super-buffered ECL without stacked structures are well suited for wave pipelining because they have uniform delay. Static CMOS and ordinary ECL including stacked structures and emitter-followers do have some delay variations. A high degree of wave pipelining is still possible in those technologies if special design techniques are followed. >
---
paper_title: Clock period minimization with wave pipelining

paper_content:

A method using a linear program for adjusting clock delays in individual flip-flops to minimize the clock period through the use of wave pipelining is discussed. Edge-triggered flip-flops are used as the circuit memory elements, and controlled delays are introduced in the time of clock signal arrivals at these elements. Constraints that relate the logic path delays from pairs of input flip-flops are derived. These constraints, in addition to known constraints relating input and output flip-flops, prevent destructive logic signal propagation interference. It is shown that in circuits without feedback the clock period reduction is limited by the shortest paths in the logic and the required signal separation between signals of distinct cycles. Application of this technique to logic with feedback is discussed. >
---
paper_title: Clock period minimization with wave pipelining

paper_content:

A method using a linear program for adjusting clock delays in individual flip-flops to minimize the clock period through the use of wave pipelining is discussed. Edge-triggered flip-flops are used as the circuit memory elements, and controlled delays are introduced in the time of clock signal arrivals at these elements. Constraints that relate the logic path delays from pairs of input flip-flops are derived. These constraints, in addition to known constraints relating input and output flip-flops, prevent destructive logic signal propagation interference. It is shown that in circuits without feedback the clock period reduction is limited by the shortest paths in the logic and the required signal separation between signals of distinct cycles. Application of this technique to logic with feedback is discussed. >
---
paper_title: A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution

paper_content:

This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 /spl mu/m CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution. >
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paper_title: A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL

paper_content:

This 4 Mb (64 k/spl times/64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25 /spl mu/m CMOS for cache memories. It achieves fully-random 300 MHz operation at a 2.5 V supply. The bandwidth is 2.4 GB/s; the highest value reported. This frequency is achieved through multi-phase active pulse control (MPAC), in which active pulse signals generated by a multi-phase PLL control the SRAM data path. The longest data path delay is shortened by dynamic decoders and current sense amplifiers.
---
paper_title: Synchronization of pipelines

paper_content:

A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pipeline circuits is defined as a function of the clock schedule and degree of wave pipelining. The authors then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. It is shown that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking is derived. The authors compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization. >
---
paper_title: A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency

paper_content:

A bipolar LSI chip which achieves 2.5 times the normal clock frequency by means of wave pipelining without the use of additional storage elements is described. In wave pipelining, multiple coherent waves of data are placed between storage elements by clocking the circuit faster than the propagation delay of the combinational logic. If all the propagation paths from the combinational circuit inputs to outputs have approximately the same delay, each wave propagates uniformly to the outputs without interfering with adjacent waves. The wave pipelining concept has been tested using a demonstration chip. Compared to an implementation using ordinary pipelining, a wave-pipelined circuit reduces the latency, area, and clock distribution required by pipeline registers or latches.<<ETX>>
---
paper_title: Sequential circuit design using synthesis and optimization

paper_content:

A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits. >
---
paper_title: Inserting active delay elements to achieve wave pipelining

paper_content:

Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. Due to limits and variations in fabrication, the clock frequency can be increased by a factor of 2 to 3 by using the best available design methods. The authors present algorithms that will equalize delays automatically by inserting a minimal number of active delay elements to lengthen short paths. This method can be combined with delay balancing by adjusting gate speeds to design wave-pipelined circuits. >
---
paper_title: Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences

paper_content:

Algorithms to automatically realize delays in combinational logic circuits to achieve wave pipelining are presented. The algorithms adjust gate speeds and insert a minimal number of active delay elements to balance input-output path lengths in a circuit. For both normal and wave-pipelined circuits, the algorithms also optimally minimize power under delay constraints. The authors analyze the algorithms and comment on their implementation. They report experimental results, including the design and testing of a 63-bit population counter in CML bipolar technology. A brief analysis of circuit technologies shows that CML and super-buffered ECL without stacked structures are well suited for wave pipelining because they have uniform delay. Static CMOS and ordinary ECL including stacked structures and emitter-followers do have some delay variations. A high degree of wave pipelining is still possible in those technologies if special design techniques are followed. >
---
paper_title: Minimum padding to satisfy short path constraints

paper_content:

Combinational circuits are often embedded in synchronous designs with memory elements at the input and output ports. A performance metric for a circuit is the cycle time of the clock signal. Correct circuit operation requires that all paths have a delay that lies between an upper bound and a lower bound. Traditional approaches in delay optimization for combinational circuits have dealt with methods to decrease the delay of the longest path. We address the issue of satisfying the lower bound constraints. Such a problem also arises in wave pipelining of circuits. We propose to handle short path constraints as a post processing step after traditional delay optimization techniques. There are two issues presented in this paper. We first discuss necessary and sufficient conditions for successful delay insertion without increasing delays of any long paths. In the second part, we present a naive approach to padding delays (greedy heuristic) and an algorithm based on linear programming. We describe an application of the theory to wave pipelining of circuits. Results are presented on a set of benchmark circuits, using two delay models.
---
paper_title: Sequential circuit design using synthesis and optimization

paper_content:

A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits. >
---
paper_title: CAzM: A circuit analyzer with macromodeling

paper_content:

A prototype circuit simulator, based on a revised formulation of the circuit equations, is described. The formulation is based on functional models of active elements, which can be derived from either equivalent-circuit or black-box models. The implementation is oriented towards the simulation of digital MOS circuits and takes advantage of the special form of such circuits. Some of the implementation issues are discussed, particularly the hierarchical structuring of the circuit equations and the use of splines to facilitate macromodeling; continuation methods for computing transfer curves are also discussed. Finally, the results of computational experiments are presented.
---
paper_title: A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency

paper_content:

A bipolar LSI chip which achieves 2.5 times the normal clock frequency by means of wave pipelining without the use of additional storage elements is described. In wave pipelining, multiple coherent waves of data are placed between storage elements by clocking the circuit faster than the propagation delay of the combinational logic. If all the propagation paths from the combinational circuit inputs to outputs have approximately the same delay, each wave propagates uniformly to the outputs without interfering with adjacent waves. The wave pipelining concept has been tested using a demonstration chip. Compared to an implementation using ordinary pipelining, a wave-pipelined circuit reduces the latency, area, and clock distribution required by pipeline registers or latches.<<ETX>>
---
paper_title: The IBM system/360 model 91: floating-point execution unit

paper_content:

The principal requirement for the Model 91 floating-point execution unit was that it be designed to support the instructionissuing rate of the processor. The chosen solution was to develop separate, instruction-oriented algorithms for the add, multiply, and divide functions. Linked together by the floating-point instruction unit, the multiple execution units provide concurrent instruction execution at the burst rate of one instruction per cycle.
---
paper_title: A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

paper_content:

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >
---
paper_title: A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency

paper_content:

A bipolar LSI chip which achieves 2.5 times the normal clock frequency by means of wave pipelining without the use of additional storage elements is described. In wave pipelining, multiple coherent waves of data are placed between storage elements by clocking the circuit faster than the propagation delay of the combinational logic. If all the propagation paths from the combinational circuit inputs to outputs have approximately the same delay, each wave propagates uniformly to the outputs without interfering with adjacent waves. The wave pipelining concept has been tested using a demonstration chip. Compared to an implementation using ordinary pipelining, a wave-pipelined circuit reduces the latency, area, and clock distribution required by pipeline registers or latches.<<ETX>>
---
paper_title: System design using wave-pipelining: a CMOS VLSI vector unit

paper_content:

Wave-pipelining, or maximum rate pipelining, is a circuit design technique which allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques by relying on the predictable finite delay through combinational logic for virtual data storage. Digital system design with ubiquitous use of wave-pipelining faces significant obstacles, including: synthesis and optimization of large wave-pipelined logic structures, synchronization of multiple wave-pipelines with feedback, designing for variation in IC fabrication characteristics, and register and wave-based logic codesign. We have developed analytical models, circuit techniques, and a CMOS wave-pipelining design environment to address these obstacles. These techniques and tools were employed in the design of a CMOS vector processor unit. Wave-pipelining is used in its vector registers and multiplier and adder functional units. This VLSI design is being fabricated in a 1 micron CMOS process and has been simulated at greater than 300 MHz.
---
paper_title: Wave-domino logic: theory and applications

paper_content:

Wave-pipelining has been investigated extensively as a design method to increase clock frequencies of digital systems. Data are clocked into a combinational circuit with a clock period smaller than the latency of the combinational block. To achieve the minimal period, collisions among waves must be avoided by balancing the delay paths from inputs to all intermediate nodes and outputs. Process variation and environmental influences have also to be taken into account in the design. While previous research has explored wave-pipelining of ECL and static CMOS circuits, we concentrate on CMOS domino circuits because of their compact layouts and shorter delay time. A timing model and constraints are given for deriving the minimal period. Special partitioning and delay assignment problems are discussed. Process variation is modeled by characterizing the current drive capabilities of N and P devices. A test chip has been designed, fabricated, and tested which uses a novel form of domino-logic to implement a wave-domino multiplier, sum of product trees, and a parity checker. >
---
paper_title: A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

paper_content:

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >
---
paper_title: A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator

paper_content:

This 512 kw/spl times/8 b/spl times/4 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator, and a 0.4 /spl mu/m BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Circuit approaches include 1) zigzag double word-line, 2) centralized bit-line load layout, and 3) phase-locked-loop (PLL) with a multi-stage-tapped (MST) ring oscillator that generates not only a de-skewed internal clock, but also a clock-cycle-proportional pulse and a clock-edge-lookahead pulse. >
---
paper_title: A 150 MHz 8-banks 256 Mb synchronous DRAM with wave pipelining methods

paper_content:

A 256 Mb synchronous DRAM with 8 banks of 32 Mb arrays introduces (1) post charge logic in the critical timing paths, (2) a wave pipelining in the data path and (3) hierarchical I/O architecture. This simplifies the latency control and leads to a fully-synchronous operation to the external clock at 150 MHz.
---
paper_title: A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL

paper_content:

This 4 Mb (64 k/spl times/64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25 /spl mu/m CMOS for cache memories. It achieves fully-random 300 MHz operation at a 2.5 V supply. The bandwidth is 2.4 GB/s; the highest value reported. This frequency is achieved through multi-phase active pulse control (MPAC), in which active pulse signals generated by a multi-phase PLL control the SRAM data path. The longest data path delay is shortened by dynamic decoders and current sense amplifiers.
---
paper_title: System design using wave-pipelining: a CMOS VLSI vector unit

paper_content:

Wave-pipelining, or maximum rate pipelining, is a circuit design technique which allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques by relying on the predictable finite delay through combinational logic for virtual data storage. Digital system design with ubiquitous use of wave-pipelining faces significant obstacles, including: synthesis and optimization of large wave-pipelined logic structures, synchronization of multiple wave-pipelines with feedback, designing for variation in IC fabrication characteristics, and register and wave-based logic codesign. We have developed analytical models, circuit techniques, and a CMOS wave-pipelining design environment to address these obstacles. These techniques and tools were employed in the design of a CMOS vector processor unit. Wave-pipelining is used in its vector registers and multiplier and adder functional units. This VLSI design is being fabricated in a 1 micron CMOS process and has been simulated at greater than 300 MHz.
---

Title: Wave-pipelining: A Tutorial and Research Survey

Section 1: INTRODUCTION
Description 1: This section introduces the concept of wave-pipelining and its significance in VLSI design, providing an overview of its benefits, historical context, and the primary research areas.

Section 2: CLOCKING OF WAVE-PIPELINED CIRCUITS
Description 2: This section defines the timing requirements and models for wave-pipelined circuits, including the derivation of timing constraints, internal node constraints, and valid clocking intervals.

Section 3: SOURCES OF DELAY VARIATIONS
Description 3: This section discusses the critical factors affecting delay variations in wave-pipelining, such as data dependencies, process, and environmental variations, and their implications on design.

Section 4: CAD TOOLS FOR WAVE-PIPELINING
Description 4: This section reviews available CAD tools and techniques for timing analysis, optimization, and synthesis of wave-pipelined circuits, highlighting practical approaches and examples.

Section 5: REAL DESIGNS WITH WAVE-PIPELINING
Description 5: This section showcases several real-world wave-pipelining implementations in both industrial and academic settings, including dedicated processors and dynamic/static RAM designs.

Section 6: CONCLUSIONS AND OPEN PROBLEMS
Description 6: This section concludes with a discussion on the current state of wave-pipelining and identifies open research problems and challenges in areas such as testing, low-power designs, and high-level synthesis.