Overview of PUF-based hardware security solutions for the internet of things
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paper_title: Low-Energy Security: Limits and Opportunities in the Internet of Things

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Many new "networkable" devices, which constitute the Internet of Things, are low energy and lightweight. These devices must devote most of their available energy and computation to executing core application functionality, making the task of affordably supporting security and privacy quite challenging.
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paper_title: Security analysis and complexity comparison of some recent lightweight RFID protocols

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Using RFID tags can simplify many applications and provide many benefits, but the privacy of the customers should be taken into account. A potential threat for the privacy of a user is that anonymous readers can obtain information about the tags in the system. In order to address the security issues of RFID systems, various schemes have been proposed. Among the various solutions, lightweight protocols have attracted much attention as they are more appropriate for the limited architecture of RFID tags. In this paper, we perform the security analysis of five lightweight protocols proposed in [1-4] and discuss their advantages and security issues. The computational complexity of these lightweight protocols are also compared in this work.
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paper_title: Maximalist Cryptography and Computation on the WISP UHF RFID Tag

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With continuous improvements in the ef?ciency of microelectronics, it is now possible to power a general-purpose microcontroller wirelessly at a reasonable range. Our implementation of RC5-32/18/16 on the WISP UHF RFID tag shows that conventional cryptography is no longer beyond the reach of a general-purpose UHF tag. In this paper, (1) we provide preliminary experimental data on how much computation is available on a TI MSP430F2132 microcontroller-based RFID tag containing approximately 8 KBytes of ?ash and 512 bytes of RAM, and (2) we show that symmetric cryptography is feasible on an RF-powered, general-purpose RFID tag — providing the ?rst implementation of conventional cryptography on an RF-powered UHF RFID tag as far as we are aware
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paper_title: Security and privacy challenges in industrial internet of things

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Today, embedded, mobile, and cyberphysical systems are ubiquitous and used in many applications, from industrial control systems, modern vehicles, to critical infrastructure. Current trends and initiatives, such as "Industrie 4.0" and Internet of Things (IoT), promise innovative business models and novel user experiences through strong connectivity and effective use of next generation of embedded devices. These systems generate, process, and exchange vast amounts of security-critical and privacy-sensitive data, which makes them attractive targets of attacks. Cyberattacks on IoT systems are very critical since they may cause physical damage and even threaten human lives. The complexity of these systems and the potential impact of cyberattacks bring upon new threats. This paper gives an introduction to Industrial IoT systems, the related security and privacy challenges, and an outlook on possible solutions towards a holistic security framework for Industrial IoT systems.
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paper_title: 8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chips

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Physically unclonable function (PUF) circuits are for generating unique secure keys or chip IDs based on intrinsic properties of each chip itself [1–2]. PUFs are a step forward to improve the security level compared to traditional NVM (non-volatile memory) solutions (FUSEs, EEPROM/FLASH, etc.) because they resolve security issues, such as active data-probing, transferring the security key from outside, etc. Since the MOSFET mismatch (e.g. size, doping concentration, mobility and oxide thickness) due to process variations cannot be fully controlled, PUFs, which are based on such phenomena, cannot be replicated. Unfortunately, the PUF output is erroneous by nature, as caused by thermal noise, voltage/temperature influence, aging effects, etc. The stability issue must be overcome since standard security applications, such as data encryption and digital signatures, have zero error-tolerance. In this work, a PUF structure based on the threshold voltage (Vth) difference of inverting logic gates is presented, which is implemented for secure 24b key generation in a 45nm smart card chip. The key is used as part of an encryption key and achieves an error rate as low as 2.01×10−38. The PUF system is also scalable for a larger key size.
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paper_title: Internet of Things for Smart Cities

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The Internet of Things (IoT) shall be able to incorporate transparently and seamlessly a large number of different and heterogeneous end systems, while providing open access to selected subsets of data for the development of a plethora of digital services. Building a general architecture for the IoT is hence a very complex task, mainly because of the extremely large variety of devices, link layer technologies, and services that may be involved in such a system. In this paper, we focus specifically to an urban IoT system that, while still being quite a broad category, are characterized by their specific application domain. Urban IoTs, in fact, are designed to support the Smart City vision, which aims at exploiting the most advanced communication technologies to support added-value services for the administration of the city and for the citizens. This paper hence provides a comprehensive survey of the enabling technologies, protocols, and architecture for an urban IoT. Furthermore, the paper will present and discuss the technical solutions and best-practice guidelines adopted in the Padova Smart City project, a proof-of-concept deployment of an IoT island in the city of Padova, Italy, performed in collaboration with the city municipality.
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paper_title: Power balanced circuits for leakage-power-attacks resilient design

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The continuous rise of static power consumption in modern CMOS technologies has led to the creation of a novel class of security attacks on cryptographic systems. The latter exploits the correlation between leakage current and the input patterns to infer the secret key; it is called leakage power analysis (LPA). The use power-balanced (m-of-n) logic is a promising solution that provides an answer to this problem, such circuits are designed to consume constant amount of power regardless of data being processed. This work evaluates the security of cryptographic circuits designed with this technology against the newly developed LPA. Two forms of LPA are investigated, one is based on differential power analysis (LDPA) and the other based on Hamming weight analysis (LHPA). Simulations performed at 90nm CMOS technology reveal that (m-of-n) circuits are totally resilient to LHPA and have a higher security level against LDPA than standard logic circuits.
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paper_title: Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

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As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
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paper_title: Area efficient configurable physical unclonable functions for FPGAs identification

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Physical Unclonable Functions (PUF) is an emerging design technology for secure hardware. It exploits the physical manufacturing variations of silicon ICs to generate a unique signature for each chip. A Ring Oscillator (RO) based PUF is a promising solution for the authentication of FPGA devices. However; this technique has not yet been widely adopted due to its large area costs and the lack of platform-independent PUF architectures which are “easy to implement”. Existing RO PUF design requires large number of ring oscillators to generate a relatively safe unique identifier; they also have complex routing requirements. This work proposes a novel configurable RO PUF architecture easily portable between different FPGA platforms. It also offers significantly larger number of challenge-response pairs compared to existing solutions with the same area overheads. The design was realized and characterized using an Altera FPGA device. Experimental results show that the quality of this design conforms to the requirements of general RO PUF.
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paper_title: TCO-PUF: A subthreshold physical unclonable function

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A Physical Unclonable Function (PUF) is a promising technology towards comprehensive security protection for integrated circuit applications. It provides a secure method of hardware identification and authentication by exploiting inherent manufacturing process variations to generate a unique response for each device. Subthreshold Current Array PUFs, which are based on the non-linearity of currents and voltages in MOSFETs in the subthreshold region, provide higher security against machine learning-based attacks compared with delay-based PUFs. However, their implementation is not practical due to the low output voltages generated from transistor arrays. In this paper, a novel architecture for a PUF, called the “Two Chooses One” PUF or TCO-PUF, is proposed to improve the output voltage ranges. The proposed PUF shows excellent quality metrics. The average inter-chip Hamming distance is 50.23%. The reliability over the temperature and ±10% supply voltage fluctuations is 91.58%. In terms of security, on average TCO-PUF shows higher security compared to delay-based PUFs and existing designs of Subthreshold Current Array PUFs against machine learning attacks.
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paper_title: Physical unclonable functions for device authentication and secret key generation

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Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.
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paper_title: A comprehensive model for PMOS NBTI degradation: Recent progress

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Abstract Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.
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paper_title: PUF Modeling Attacks on Simulated and Silicon Data

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We discuss numerical modeling attacks on several proposed strong physical unclonable functions (PUFs). Given a set of challenge-response pairs (CRPs) of a Strong PUF, the goal of our attacks is to construct a computer algorithm which behaves indistinguishably from the original PUF on almost all CRPs. If successful, this algorithm can subsequently impersonate the Strong PUF, and can be cloned and distributed arbitrarily. It breaks the security of any applications that rest on the Strong PUF's unpredictability and physical unclonability. Our method is less relevant for other PUF types such as Weak PUFs. The Strong PUFs that we could attack successfully include standard Arbiter PUFs of essentially arbitrary sizes, and XOR Arbiter PUFs, Lightweight Secure PUFs, and Feed-Forward Arbiter PUFs up to certain sizes and complexities. We also investigate the hardness of certain Ring Oscillator PUF architectures in typical Strong PUF applications. Our attacks are based upon various machine learning techniques, including a specially tailored variant of logistic regression and evolution strategies. Our results are mostly obtained on CRPs from numerical simulations that use established digital models of the respective PUFs. For a subset of the considered PUFs-namely standard Arbiter PUFs and XOR Arbiter PUFs-we also lead proofs of concept on silicon data from both FPGAs and ASICs. Over four million silicon CRPs are used in this process. The performance on silicon CRPs is very close to simulated CRPs, confirming a conjecture from earlier versions of this work. Our findings lead to new design requirements for secure electrical Strong PUFs, and will be useful to PUF designers and attackers alike.
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paper_title: PUF modeling attacks: An introduction and overview

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Machine learning (ML) based modeling attacks are the currently most relevant and effective attack form for so-called Strong Physical Unclonable Functions (Strong PUFs). We provide an overview of this method in this paper: We discuss (i) the basic conditions under which it is applicable; (ii) the ML algorithms that have been used in this context; (iii) the latest and most advanced results; (iv) the right interpretation of existing results; and (v) possible future research directions.
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Title: Overview of PUF-based hardware security solutions for the internet of things
Section 1: INTRODUCTION
Description 1: This section introduces the concept of the Internet of Things (IoT) and highlights the key security challenges associated with IoT devices.

Section 2: PRINCIPLES OF PUF DESIGN AND EVALUATION METHODS
Description 2: This section outlines the design principles of Physically Unclonable Functions (PUFs) and summarizes their evaluation metrics.

Section 3: PUF-BASED HARDWARE SECURITY SOLUTIONS
Description 3: This section presents two classes of PUF-based security applications, specifically focusing on authentication and encryption/decryption schemes.

Section 4: OUTSTANDING RELIABILITY AND SECURITY PROBLEMS
Description 4: This section discusses the major reliability and security issues associated with PUF technology and their implications for IoT security.

Section 5: CONCLUSION
Description 5: This section summarizes the key findings and points out future directions for research to mitigate the reliability and security problems of PUFs in IoT devices.