Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World
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paper_title: A Fully-Integrated, Short-Range, Low Data Rate FM-UWB Transmitter in 90 nm CMOS

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This paper presents a fully-integrated 3-5 GHz-band FM-UWB transmitter implemented in 90 nm bulk CMOS. The front-end consists of an RF current-controlled oscillator (RF-ICO) and class-AB power amplifier. Transmit data modulates a sub-carrier oscillator. The 2-FSK modulated output is amplified by a transconductor, and directly modulates the RF-ICO tune input. A successive approximation register (SAR) algorithm and on-chip all-digital frequency-locked loop (FLL) calibrate the carrier and sub-carrier frequencies. All voltage and current references required by the transmitter are included on-chip. The 0.2 × 0.5 mm2 active area transmitter consumes 900 μW from a 1 V supply. Energy efficiency of the transmitter is 9 nJ/bit running continuously at 100 kbits/s.
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paper_title: Power-efficient switching-based CMOS UWB transmitters for UWB communications and Radar systems

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This paper presents a new carrier-based ultra-wideband (UWB) transmitter architecture. The new UWB transmitter implements a double-stage switching to enhance RF-power efficiency, reduce dc-power consumption, and increase switching speed and isolation, while reducing circuit complexity. In addition, this paper also demonstrates a new carrier-based UWB transmitting module implemented using a 0.18-mum CMOS integrated pulse generator-switch chip. The design of a UWB sub-nanosecond-switching 0.18-mum CMOS single-pole single-throw (SPST) switch, operating from 0.45 MHz to 15 GHz, is discussed. The design of a 0.18-mum CMOS tunable impulse generator is also presented. The edge-compression phenomenon of the impulse signal controlling the SPST switch, which makes the generated UWB signal narrower than the impulse, is described. Measurement results show that the generated UWB signal can vary from 2 V peak-to-peak with 3-dB 4-ns pulsewidth to 1 V with 0.5 ns, covering 10-dB signal bandwidths from 0.5 to 4 GHz, respectively. The generated UWB signal can be tuned to cover the entire UWB frequency range of 3.1-10.6 GHz. The sidelobe suppression in the measured spectrums is more than 15 dB. The entire CMOS module works under a 1.8-V supply voltage and consumes less than 1 mA of dc current. The proposed carrier-based UWB transmitter and the demonstrated module provide an attractive means for UWB signal generation for both UWB communications and radar applications
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paper_title: 20-pJ/Pulse 250 Mbps Low-Complexity CMOS UWB Transmitter for 3–5 GHz Applications

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This letter presents a CMOS on-off keying 3-5 GHz ultra-wideband (UWB) transmitter with low complexity, low power and high speed. In the transmitter, a new differential narrow triangular pulse generator using push and pull integrating technique was designed for reducing quiescent current and common-mode interference, and a new complementary switch mode on-off voltage controlled ring oscillator (VCRO) was proposed by breaking the oscillation loop instead of breaking the power to avoid base-band energy without extra shaping filter. Without using delay resistor and capacitor in the VCRO, the transient response speed of the transmitter can be increased by only utilizing the parasitic resistances and capacitances. The design was successfully implemented with a 0.18 μm CMOS technology. The test results show that the new UWB transmitter can obtain a sidelobe rejection of more than 20 dB, a low energy consumption of 20 pJ/pulse at 250 Mbps, and a small core chip size of 0.08 mm2.
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paper_title: A survey on technological, business and societal aspects of Internet of Things by Q3, 2017

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The Internet of Things (IoT) is one of the most trending technologies of the current era and is expected to cover a significant share of the global market in future. It connects physical objects to make them control and work for our daily chores; making it get its application in different fields of automation, thus reducing human effort. The objective of this paper is to emphasize on the different influencing aspects of IoT, namely Technology, Business and Society. After going through different journals, survey papers, blogs, newsletters, books and other information sources in this field, we pointed out the major Technological challenges of IoT; reviewed some relevant Business matters; and brought forward some affecting Social issues. We start this paper by presenting a brief overview of the IoT, and finally draw a relation among the different aspects of it.
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paper_title: An Energy-Efficient All-Digital UWB Transmitter Employing Dual Capacitively-Coupled Pulse-Shaping Drivers

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This paper presents an all-digital, non-coherent, pulsed-UWB transmitter. By exploiting relaxed center frequency tolerances in non-coherent wideband communication, the transmitter synthesizes UWB pulses from an energy-efficient, single-ended digital ring oscillator. Dual capacitively coupled digital power amplifiers (PAs) are used in tandem to attenuate low frequency content typically associated with single-ended digital circuits driving single-ended antennas. Furthermore, four level digital pulse shaping is employed to attenuate RF sidelobes, resulting in FCC compliant operation in the 3.5, 4.0, and 4.5 GHz IEEE 802.15.4a bands without the use of any off-chip filters or large passive components. The transmitter is fabricated in a 90 nm CMOS process and occupies a core area of 0.07 mm2 . The entirely digital architecture consumes zero static bias current, resulting in an energy efficiency of 17.5 pJ/pulse at data rates up to 15.6 Mb/s.
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paper_title: Area and Power Efficient Ultra-Wideband Transmitter Based on Active Inductor

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This brief presents the design of an impulse radio ultra-wideband (IR-UWB) transmitter for low-power, short-range, and high-data rate applications such as high density neural recording interfaces. The IR-UWB transmitter pulses are generated by modulating the output of a local oscillator. The large area requirement of the spiral inductor in a conventional on-chip LC tank is overcome by replacing it with an active inductor topology. The circuit has been fabricated in a UMC CMOS 180-nm technology, with a die area of 0.021 mm2. The temporal width of the output waveform is determined by a pulse generator based on logic gates. The measured pulse is compliant with federal communications commission power spectral density limits and within the frequency band of 3–6 GHz. For the minimum pulse duration of 1 ns, the energy consumption of the design is 20 pJ per bit, while transmitting at 200-Mbps data rate with an amplitude of 130 mV.
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paper_title: A Systems Approach to Conduct an Effective Literature Review in Support of Information Systems Research

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This paper introduces a framework for conducting and writing an effective literature review. The target audience for the framework includes information systems (IS) doctoral students, novice IS researchers, and other IS researchers who are constantly struggling with the development of an effective literature-based foundation for a proposed research. The proposed framework follows the systematic data processing approach comprised of three major stages: 1) inputs (literature gathering and screening), 2) processing (following Bloom’s Taxonomy), and 3) outputs (writing the literature review). This paper provides the rationale for developing a solid literature review including detailed instructions on how to conduct each stage of the process proposed. The paper concludes by providing arguments for the value of an effective literature review to IS research.
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paper_title: Literature search strategies for conducting knowledge-building and theory-generating qualitative systematic reviews

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AIM ::: To report literature search strategies for the purpose of conducting knowledge-building and theory-generating qualitative systematic reviews. ::: ::: ::: BACKGROUND ::: Qualitative systematic reviews lie on a continuum from knowledge-building and theory-generating to aggregating and summarizing. Different types of literature searches are needed to optimally support these dissimilar reviews. ::: ::: ::: DATA SOURCES ::: Articles published between 1989-Autumn 2011. These documents were identified using a hermeneutic approach and multiple literature search strategies. ::: ::: ::: DISCUSSION ::: Redundancy is not the sole measure of validity when conducting knowledge-building and theory-generating systematic reviews. When conducting these types of reviews, literature searches should be consistent with the goal of fully explicating concepts and the interrelationships among them. To accomplish this objective, a 'berry picking' approach is recommended along with strategies for overcoming barriers to finding qualitative research reports. ::: ::: ::: IMPLICATIONS ::: To enhance integrity of knowledge-building and theory-generating systematic reviews, reviewers are urged to make literature search processes as transparent as possible, despite their complexity. This includes fully explaining and rationalizing what databases were used and how they were searched. It also means describing how literature tracking was conducted and grey literature was searched. In the end, the decision to cease searching also needs to be fully explained and rationalized. ::: ::: ::: CONCLUSION ::: Predetermined linear search strategies are unlikely to generate search results that are adequate for purposes of conducting knowledge-building and theory-generating qualitative systematic reviews. Instead, it is recommended that iterative search strategies take shape as reviews evolve.
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paper_title: From ASIC to ASIP: the next design discontinuity

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A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a significant move towards the use of programmable solutions of various forms - increasingly referred to as programmable platforms. For the platform manufacturer, programmability provides higher volume to amortize design and manufacturing costs, as the same platform can be used over multiple related applications, as well as over generations of an application. For the application implementer, programmability provides a lower risk and shorter time-to-market implementation path. The flexibility provided by programmability comes with a performance and power overhead. This can be significantly mitigated by using application specific platforms, also referred to as Application Specific Instruction Set Processors (ASIPs). This paper details the reasons for this significant change in application implementation philosophy, provides illustrative contemporary evidence of this change, examines the space of application specific platforms, outlines fundamental problems in their development, and finally presents a methodology to deal with this changing design style.
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paper_title: Recent advances in IR-UWB transceivers: An overview

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Modern Ultra-Wide Band (UWB) regulations have recently been adopted worldwide allowing for unlicensed operation within 3.1 and 10.6 GHz, using an appropriate wideband signal format with a low Effective Isotropic Radiated Power (EIRP) level. UWB characteristics are suitable to transmit data using pulses instead of continuous-waves such as in narrowband radio links. It has the potential to be the right technology for high data-rate, low-power and short-to-medium range communication systems. We will focus on Impulse Radio-UWB (IR-UWB) systems and show their suitability for many different applications, including sensor networks, ad-hoc networks, cognitive radio, home networking, etc. We will also discuss the difficulties and challenges of designing IR-UWB systems. We present a tutorial overview of UWB regulations and usable signals. We present the existing standards and recommendations, and we review recently published results, highlighting trends in UWB transceiver power consumption and the impact of CMOS scaling on performance.
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paper_title: Integrated Light Sensing and Communication for LED Lighting

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Solid state lighting is nowadays widely diffused both in residential and office or industrial environment. Ambient light sensing to modulate lamp power is typical too, but sensors inside a lamp are a challenge, due to the high flux of these sources, which easily saturates nearby light detectors. Usually, separate sensing devices must be introduced in the system, thus increasing complexity and cost. In this work, a methodology will be presented, to allow integration of a light sensing device inside a lamp, using low cost circuitry to mitigate interactions between high power light-emitting diode (LED) sources and sensing photodiodes. Moreover, the same circuit allows visual light communication among sources.
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paper_title: LiFi is a paradigm-shifting 5G technology

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Abstract In this paper we will first explain what Light-Fidelity (LiFi) is and argue that it is a 5th Generation (5G) technology. Peak transmission speeds of 8 Gbps from a single light source have been demonstrated, and complete cellular networks based on LiFi have been created. We will discuss numerous misconceptions and illustrate the potential impact this technology can have across a number of existing and emerging industries. We also discuss new applications which LiFi can unlock in the future.
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paper_title: Design of a 10 bit 50MS/s SAR ADC in 14nm SOI FinFET CMOS

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This paper presents a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with 60.9 dB SNDR at 50MS/s while with 41.3uW power consumption. Several techniques were used to decrease the power consumption. First, Segmented architecture was used to decrease the total number of capacitance. Aligned switching with skip (ASS) method was used during copy MSB bits from coarse to fine, which saves 58% switching power. Second, the normal SAR switching is based on VCM-based switching algorithm; it saves 85.72% power compared with traditional SAR. Third, dual supply mode with analog at 0.8V and digital at 0.4V was used to decrease the digital logic power consumption, simulation results show that it saves 23% total power consumption at dual supply mode. Differential architecture was used to minimize the commode non-idealities. The proposed ADC achieved a peak figure of merit (FoM) of 0.93 fJ/Conv with simulation results in 14nm SOI FinFET technology.
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paper_title: Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation

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In this paper, a new design paradigm referred to as compressive acquisition CMOS image sensors is introduced. The idea consists of compressing the data within each pixel prior to storage, and hence, reducing the size of the memory required for digital pixel sensor. The proposed compression algorithm uses a block-based differential coding scheme in which differential values are captured and quantized online. A time-domain encoding scheme is used in our CMOS image sensor in which the brightest pixel within each block fires first and is selected as the reference pixel. The differential values between subsequent pixels and the reference within each block are calculated and quantized, using a reduced number of bits as their dynamic range is compressed. The proposed scheme enables reduced error accumulation as full precision is used at the start of each block, while also enabling reduced memory requirement, and hence, enabling significant silicon area saving. A mathematical model is derived to analyze the performance of the algorithm. Experimental results on a field-programmable gate-array (FPGA) platform illustrate that the proposed algorithm enables more than 50% memory saving at a peak signal-to-noise ratio level of 30 dB with 1.5 bit per pixel.
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paper_title: A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS

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This paper presents the design and implementation of a 10-bit ultra-low voltage energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). The proposed first 2-bit guess (F2G) scheme reduces the DAC switching energy by 90% and improves the DNL and INL by $\sqrt {3} {/2}$ in theory compared with the conventional approach. By employing majority-vote comparison at the conversions of LSBs, the noise requirement of comparator can be relaxed by half. With the segmented and bundled routing, the parasitic capacitors of bottom-plates of DAC array are reduced to improve power efficiency and speed. Implemented in 90-nm CMOS technology, the test chip occupied a core area of 0.03 mm2. The prototype consumes 67.3 nW at 150 kS/s from a single 0.3 V supply voltage and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant Walden’s FoM and Schreier’s FoM are 0.97 fJ/conv.-step and 175.5 dB, respectively.
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paper_title: Per-Pixel Mirror-Based Acquisition Method for video compressive sensing

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High-speed videos are essential to many types of scientific investigations. However, using high-speed cameras to directly acquire these videos is prohibitively expensive in many circumstances. This paper proposes a compressive sensing-based method for obtaining high-speed videos using low-speed cameras, which we call the Per-Pixel Mirror-Based Acquisition Method. The proposed technique is light efficient and generates time-independent samples. We compare the reconstruction results of the proposed technique with other techniques available in the literature in terms of signal-to-error (SER) ratios, for natural and synthetic videos. For the tested real videos, the proposed method provided an improvement in SER ranging from 3 to 28 dB, with respect to known techniques such as the flutter shutter and the per-pixel shutter. The actual improvement is higher for higher levels of sparsity in the used transformed representations and for lower used sub-sampling rates.
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paper_title: Design of a Digital Address-Event Triggered Compressive Acquisition Image Sensor

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This paper describes a compressive acquisition image sensor realizing an on-chip focal plane compressive sensing algorithm. The proposed design enables signal sampling at a rate much lower than the Nyquist rate while preserving the capability to recover the useful information of the signal. Address events are employed to convert illumination intensity into time domain information, eliminating the use of analog-to-digital converters and effectively reducing the readout rate. A pixel-level all digital address event triggered compressive sensing request generator is implemented. An image pixel array of 48 × 72 was fabricated in 0.18 μm standard CMOS technology, featuring a 22-transistor all-digital pixel architecture with a size of 15 × 15 μm ::: 2 ::: and a fill factor of 32.4%. Experimental results show a higher than 10 compression ratio with a power consumption of 1.56 mW at 23 fps under image acquisition mode.
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paper_title: Universal Asynchronous Receiver and Transmitter (UART)

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Data transfer between two devices can be as parallel communication or serial communication.
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paper_title: Compressive sensing based microarray image acquisition

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This paper implements Orthogonal Matching Pursuit (OMP) algorithm for reconstruction of Microarray Images based on the compressive sensing paradigm. Gaussian and Bernoulli random patterns are used to capture the scene. A Monte Carlo simulation is performed to calculate the peak signal to noise ratio, relative error and universal quality index of the red and green channels of the image independently. Since images are not sparse but rather compressible, the paper seeks to reconstruct approximately 90 percent of the energy using Discrete Cosine Transform (DCT) as the basis. This paper successfully proposes the use of post processing for quality improvement rather than increase in measurements. Post processing using median filter can account for a reduction of 200 samples per block. The results obtained show that, both the sensing matrices tested are equally good with Bernoulli pattern having the advantage of being sparse.
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paper_title: A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS

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Internet-of-things applications require high energy-efficient ADC. Several SAR ADCs have been reported [1-2] with comparatively low FoMs by reducing the switching energy of the power hungry capacitor array. This paper proposes a shifted monotonic switching (SMS) scheme to achieve an average switching energy of 63.75CV2 with a reduction of 75%, 72%, and 73% compared to monotonic switching (MS), sub-ranging (SR) procedure [1], and merge and split (MAS) switching [2] procedure, respectively. Proper redundancy design is also employed to tolerate the non-ideal effects including dynamic comparator offset, Vcm variation, and settling error.
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paper_title: IoT: Bird’s Eye View, Megatrends and Perspectives

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This chapter opens the book and provides a summary of the challenges and the opportunities that are offered by the Internet of Things (IoT), with emphasis on the aspects that are relevant to integrated circuit and system design from circuits to packaging for IoT nodes. The chapter is organized along a chronological perspective, first reviewing technology historical trends beyond mere Moore’s law, and summarizing recent past achievements and capabilities that are making the IoT possible. Then, present challenges are described, as pathway to up-coming advances and developments in the design of IoT nodes. Finally, mega-trends are examined to unearth clues on longer-term evolution of the IoT and the implications on integrated system design.
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paper_title: Single-pixel compressive imaging based on motion compensation

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Compressive sensing (CS) theory enables single-pixel compressive imaging (SPCI) popular in optical remote sensing imaging, since single-pixel imager not only realises the acquisition and recovery of sparse images at the sampling rates significantly below the classical Nyquist rate, but also makes use of special detectors to improve sensitivity, dynamic range, spectral range and so on. However, its requirement of static imaging condition for the time-sequential measurements makes it difficult to apply in remote sensing, since the imaging platform is always in motion relative to the imaging scene. In this study, the authors develop a new method for SPCI on moving platform in optical remote sensing. Instead of ignoring the motion during sampling, the proposed method first builds the compressive sampling model based on motion compensation during sampling, and then reconstructs the image by frame-by-frame recovery method and joint recovery method, respectively, in the framework of CS theory, where the recovery condition is also analysed. To validate the basic principle and the physical feasibility of motion compensation, the authors implement the numerical simulations and optical experiments, where different conditions are exploited sufficiently. In addition, the proposed method for SPCI can be also extended into other applications, such as 360° annular imaging, multi-pixel compressive imaging as well as super-resolution imaging.
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paper_title: A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

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This paper presents an 11-bit ultralow voltage energy efficient successive approximation register (SAR) analog-to-digital converter (ADC). With the proposed semi-resting (SR) digital-to-analog convertor (DAC) switching scheme, this paper consumes only 6%–13.5% switching energy, compared to the state-of-the-art works. In addition, the SR switching scheme effectively reduces the differential nonlinearity and integral nonlinearity to be 1/2, compared to the conventional approach under the same matching conditions. With the proposed SR DAC switching scheme, this paper can handle the same input swing using a half supply and consume smaller power consumption. A cascade-input comparator is developed to consume only 49% of the power and 66% of the decision time with a threefold front-stage gain boost. The test chip occupies a core area of 0.035 mm2 in 90-nm CMOS technology. The prototype consumes 187 nW at 600 kS/s with a single 0.3-V supply voltage. The achieved effective number of bits and spurious-free dynamic range at Nyquist input are 9.46 bits and 73 dB, respectively. The resultant Walden’s figure of merit (FoM) and Schreier’s FoM are 0.44 fJ/conversion-step and 180.8 dB, respectively.
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paper_title: A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC

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A 0.3V 600KS/s 11b SAR ADC with semi-resting (SR) DAC, cascade-input (CI) comparator, and double rail-to-rail input range is implemented in 90nm CMOS. The SR DAC consumes only 6–13.5% switching energy of the state-of-the-art works. The CI comparator consumes only 49% of power and 66% of decision time with an ×3 front-stage gain boost. The prototype achieves a SNDR of 58.7dB, an ENOB of 9.46b, a power of 187nW, and a resulting FoM of 0.44fJ/conv.-step.
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paper_title: A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window

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This paper presents a 0.35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS. The SAR ADC uses the transient information of the latch comparator to create redundancy ranges. Furthermore, the proposed technique also uses the transient information to produce AW for each bit which can significantly reduce the power consumption of the comparator, the DAC settling time and also digital control logic. Last but not least, the timing control window can also avoid ADC from encountering meta-stability. The measurement result achieves an SNDR of 57.18 dB, an ENOB of 9.2 bits, a power consumption of 74 nW, and a resulting FoM of 1.25 fJ/conv.-step.
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paper_title: Compressive video sensing based on user attention model

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We propose a compressive video sensing scheme based on user attention model (UAM) for real video sequences acquisition. In this work, for every group of consecutive video frames, we set the first frame as reference frame and build a UAM with visual rhythm analysis (VRA) to automatically determine region-of-interest (ROI) for non-reference frames. The determined ROI usually has significant movement and attracts more attention. Each frame of the video sequence is divided into non-overlapping blocks of 16×16 pixel size. Compressive video sampling is conducted in a block-by-block manner on each frame through a single operator and in a whole region manner on the ROIs through a different operator. Our video reconstruction algorithm involves alternating direction l 1 — norm minimization algorithm (ADM) for the frame difference of non-ROI blocks and minimum total-variance (TV) method for the ROIs. Experimental results showed that our method could significantly enhance the quality of reconstructed video and reduce the errors accumulated during the reconstruction.
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paper_title: A Comprehensive IoT Attacks Survey based on a Building-blocked Reference Model

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Internet of Things (IoT) has not yet reached a distinctive ::: definition. A generic understanding of IoT is that it offers ::: numerous services in many domains, utilizing conventional internet ::: infrastructure by enabling different communication patterns ::: such as human-to-object, object-to-objects, and object-to-object. ::: Integrating IoT objects into the standard Internet, however, has ::: unlocked several security challenges, as most internet technologies ::: and connectivity protocols have been specifically designed for ::: unconstrained objects. Moreover, IoT objects have their own ::: limitations in terms of computation power, memory and bandwidth. ::: IoT vision, therefore, has suffered from unprecedented ::: attacks targeting not only individuals but also enterprises, some ::: examples of these attacks are loss of privacy, organized crime, ::: mental suffering, and the probability of jeopardizing human ::: lives. Hence, providing a comprehensive classification of IoT ::: attacks and their available countermeasures is an indispensable ::: requirement. In this paper, we propose a novel four-layered IoT ::: reference model based on building blocks strategy, in which we ::: develop a comprehensive IoT attack model composed of four key ::: phases. First, we have proposed IoT asset-based attack surface, ::: which consists of four main components: 1) physical objects, 2) ::: protocols covering whole IoT stack, 3) data, and 4) software. ::: Second, we describe a set of IoT security goals. Third, we ::: identify IoT attack taxonomy for each asset. Finally, we show ::: the relationship between each attack and its violated security ::: goals, and identify a set of countermeasures to protect each asset ::: as well. To the best of our knowledge, this is the first paper that ::: attempts to provide a comprehensive IoT attacks model based on ::: a building-blocked reference model.
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paper_title: Detection of Known and Unknown Intrusive Sensor Behavior in Critical Applications

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This article presents a hybrid architecture to identify intrusive behavior among networked sensors that monitor critical systems such as environment, medical, and smart grid. Monitoring through sensors is desired for critical applications such as epilepsy seizures, pollution, power quality assessment, and transformer monitoring. Wireless sensors are being widely used in critical applications due to their advantages including low-cost, flexibility, and communication efficiency. However, when sensors are networked to monitor a critical infrastructure such as the smart grid, they become the target of different types of attackers such as intruders via the communication medium. In order to maintain sensing in a secure manner, robust architectures are needed to identify intrusive behavior of sensors in a network. In this article, we present a hybrid architecture to detect intrusive behavior of sensors for both unknown and known intruders. The former requires anomaly detection, whereas the latter requires signature detection. The proposed architecture consists of two subsystems that co-operate to detect unknown and known attacks through duty-cycling of enhanced density-based spatial clustering of applications with noise and random forest methods. Through various tests on real intrusion data, we show that the proposed architecture has a strong potential to detect both known and unknown intrusive behavior of sensor nodes as the results show 99.73% detection rate with 98.95% overall accuracy.
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paper_title: Mitigating False Negative intruder decisions in WSN-based Smart Grid monitoring

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Monitoring the Smart Grid (SG) is highly desired for critical applications such as power quality assessment and transformer monitoring. Due to their low-cost, flexibility and efficiency as well as their widely usage in several critical infrastructure monitoring applications, Wireless Sensor Networks (WSNs) are estimated to be extensively used in SG applications. WSNs-based SG networks are vulnerable to different types of attacks and intruders. In order to operate networks in secured environments, in this paper we analyze our Clustered Hierarchal Hybrid-Intrusion Detection System (CHH-IDS) that is responsible for various attacks injected by known and unknown intruders. As False Positives (FPs) and False Negatives (FNs) are the key performance parameters in IDS, we investigate mitigation of FNs through a two-tier intrusion detection approach, which deals with anomaly and signature detection in parallel. In the presence of such a hybrid mode, utilization proportion between the anomaly detection and signature detection models affect the FN performance. In these two subsystems, Random Forest method is used for signature detection over known attacks and E-DBSCAN (Enhanced Density-Based Spatial Clustering of Applications with Noise) method is used for anomaly detection over unknown attacks. Through simulations that run on real datasets, we validate that the higher the weight of anomaly detection subsystem (i.e. the lower the weight of the signature detection subsystem), the lower the FN rates experienced by the entire H-IDS system. More specifically, we show that FN rates can be significantly reduced by 20.4% when the weight on anomaly detection subsystem is increased from 60% to 70% while the accuracy is expected to be improved through signature detection subsystem by using the Random Forest which has higher detection rate than the E-DBSCAN method.
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paper_title: Collusion attacks in Internet of Things: Detection and mitigation using a fog based model

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This paper discusses the problem of collusion attacks in Internet of Things (IoT) environments and how mobility of IoT devices increases the difficulty of detecting such types of attacks. It demonstrates how approaches used in detecting collusion attacks in WSNs are not applicable in IoT environments. To this end, the paper introduces a model based on the Fog Computing infrastructure to keep track of IoT devices and detect collusion attackers. The model uses fog computing layer for real-time monitoring and detection of collusion attacks in IoT environments. Moreover, the model uses a software defined system layer to add a degree of flexibility for configuring Fog nodes in order to enable them to detect various types of collusion attacks. Furthermore, the paper highlights the possible overhead on Fog nodes and network when applying the proposed model, and claims that the Fog layer infrastructure can provide the required resources for the scalability of the model.
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paper_title: Internet of Things (IoT) in 5G Wireless Communications

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During the past decade, the Internet of Things (IoT) has revolutionized the ubiquitous computing with multitude of applications built around various types of sensors. A vast amount of activity is seen in IoT based product-lines and this activity is expected to grow in years to come with projections as high as billions of devices with on average 6-7 devices per person by year 2020. With most of the issues at device and protocol levels solved during the past decade, there is now a growing trend in integration of sensors and sensor based systems with cyber physical systems and device-to-device (D2D) communications. 5 ::: th ::: generation wireless systems (5G) are on the horizon and IoT is taking the center stage as devices are expected to form a major portion of this 5G network paradigm. IoT technologies such as machine to machine communication complemented with intelligent data analytics are expected to drastically change landscape of various industries. The emergence of cloud computing and its extension to fog paradigm with proliferation of intelligent `smart' devices is expected to lead further innovation in IoT. These developments excite us and form a motivation to survey existing work, design new techniques, and identify new applications of IoT. Researchers, scientists, and engineers face emerging challenges in designing IoT based systems that can efficiently be integrated with the 5G wireless communications.
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paper_title: Adaptively Supervised and Intrusion-Aware Data Aggregation for Wireless Sensor Clusters in Critical Infrastructures

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Wireless sensor networks have become integral components of the monitoring systems for critical infrastructures such as the power grid or residential microgrids. Therefore, implementation of robust Intrusion Detection Systems (IDS) at the sensory data aggregation stage has become of paramount importance. Key performance targets for IDS in these environments involve accuracy, precision, and the receiver operating characteristics which is a function of the sensitivity and the ratio of false alarms. Furthermore, the interplay between machine learning and networked systems has led to promising opportunities, particularly for the system level security of wireless sensor networks. Pursuant to these, in this paper, we propose Adaptively Supervised and Clustered Hybrid IDS (ASCH-IDS) for wirelessly connected sensor clusters that monitor critical infrastructures. The proposed ASCH-IDS mechanism is built on a hybrid IDS framework, and transforms the previous work by continuously monitoring the behavior of the receiver operating characteristics, and adaptively directing the incoming packets at a sensor cluster towards either misuse detection or anomaly detection module. We evaluate the proposed mechanism by introducing real attack data sets into simulations, and show that our proposal performs at 98.9% detection rate and approximately 99.80% overall accuracy to detect known and unknown malicious behavior in the sensor network.
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paper_title: Trusted Third Party for service management in vehicular clouds

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As vehicles get smarter, with supplementary onboard gear providing advanced applications and provisioning services related to traffic management, the requirement for simple and effective access to information has grown extensively. The new applications manage more complex operations and, unlike other mobile devices, mobile vehicle devices provide location based services, real-time functionality, provisioning services and storage, all without the shortcomings of traditional mobile devices. Vehicular cloud computing can perform a broad set of on-demand services and applications, which make this method highly applicable to urban settings. Provisioning services often encounter unexpected interruptions that increase provisioning latency and service usage duration, ultimately leading to higher charges for the driver. This paper advances our previously proposed distributed model to handle service management in vehicular clouds, by using the concept of Vehicular Trusted Third Party (VTTP) with different type of provisioning services. This model has the capability to switch between TTPs, which allows drivers to exploit the benefits of different existing services, and connect to the TTP that best meets their specific requirements. Two new service latency modes are proposed and evaluated: Service Latency Sensitive Mode (SLSM) and Neutral mode. The proposed model has been implemented and evaluated using simulations of real-time light and heavy duty services, and various simulation scenarios show that using a VTTP can significantly help drivers reduce their service latency (∼30%) and costs (∼26%).
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paper_title: Security threats to critical infrastructure: the human factor

paper_content:

In the twenty-first century, globalisation made corporate boundaries invisible and difficult to manage. This new macroeconomic transformation caused by globalisation introduced new challenges for critical infrastructure management. By replacing manual tasks with automated decision making and sophisticated technology, no doubt we feel much more secure than half a century ago. As the technological advancement takes root, so does the maturity of security threats. It is common that today’s critical infrastructures are operated by non-computer experts, e.g. nurses in health care, soldiers in military or firefighters in emergency services. In such challenging applications, protecting against insider attacks is often neither feasible nor economically possible, but these threats can be managed using suitable risk management strategies. Security technologies, e.g. firewalls, help protect data assets and computer systems against unauthorised entry. However, one area which is often largely ignored is the human factor of system security. Through social engineering techniques, malicious attackers are able to breach organisational security via people interactions. This paper presents a security awareness training framework, which can be used to train operators of critical infrastructure, on various social engineering security threats such as spear phishing, baiting, pretexting, among others.
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paper_title: A Continuous Diversified Vehicular Cloud Service Availability Framework for Smart Cities

paper_content:

Abstract The intelligent and connected transportation system (ICTS) is a significant and mandatory component of the smart city architecture. Multimedia content sharing, vehicle power management, and road navigation are all examples of ICTS services. As smart cities continue to deploy different technologies to improve the performance and diversity of vehicular cloud services, one of the main issues that prevails is efficient and reliable service discovery and selection for smart vehicles. Furthermore, cloud service providers (SPs) are limited to the availability, variety and quality of services made available to vehicular cloud subscribers. Smart vehicles rely on a number of SPs to acquire the required services while moving. It therefore becomes challenging for vehicular cloud subscribers to acquire services that meet their quality of experience (QoE) preferences. This paper introduces a new service provision scheme to provide continuous availability of diversified cloud services targeting vehicular cloud users through a cluster-based trusted third party (TTP) framework. TTPs act as cloud service mediators between cloud service subscribers and providers. Vehicles that are considered to have similar patterns of movement and service acquisition characteristics are grouped into service-specific clusters. TTPs communicate with service providers and cluster heads to negotiate for services with high QoE characteristics. A location prediction method is adopted to determine a vehicle's future location and allow services to be negotiated for before the vehicle's arrival. We provide simulation results to show that our approach can adequately discover and deliver cloud services with increased QoE results, minimal overhead burden and reduced end-to-end latency.
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paper_title: Fairness-Aware Game Theoretic Approach for Service Management in Vehicular Clouds

paper_content:

Vehicular cloud computing can perform a broad set of on-demand applications and services, which makes it highly suitable for urban settings. Despite a wide range of benefits to various services and applications by vehicular clouds, there are several issues and challenges that need to be carefully addressed in the context of provisioning services. This paper proposes a cooperative distributed game model to handle service management in vehicular clouds. Under this model, service providers play a cooperative game to maximize their total utility taking into consideration their recourse availability, current load, and total payoff. The proposed game has been implemented and evaluated using simulations with scenarios of light and heavy weight services. The game demonstrates that a cooperative technique leads players to handle higher number of services when compared to a non-cooperative setting. Furthermore, we also show that the proposed game mimics the behaviour of an optimization-based baseline solution. Through various simulation scenarios, we show that the proposed scheme introduces more than 85% similarity to the optimal solution when a few number of players participate, and its similarity to the optimal solution is improved to 99% when the number of the players increases by only 50%.
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paper_title: Hierarchical trust-based black-hole detection in WSN-based smart grid monitoring

paper_content:

Wireless Sensor Networks (WSNs) have been widely adopted to monitor various ambient conditions including critical infrastructures. Since power grid is considered as a critical infrastructure, and the smart grid has appeared as a viable technology to introduce more reliability, efficiency, controllability, and safety to the traditional power grid, WSNs have been envisioned as potential tools to monitor the smart grid. The motivation behind smart grid monitoring is to improve its emergency preparedness and resilience. Despite their effectiveness in monitoring critical infrastructures, WSNs also introduce various security vulnerabilities due to their open nature and unreliable wireless links. In this paper, we focus on the, Black-Hole (B-H) attack. To cope with this, we propose a hierarchical trust-based WSN monitoring model for the smart grid equipment in order to detect the B-H attacks. Malicious nodes have been detected by testing the trade-off between trust and dropped packet ratios for each Cluster Head (CH). We select different thresholds for the Packets Dropped Ratio (PDR) in order to test the network behaviour with them. We set four different thresholds (20%, 30%, 40%, and 50%). Threshold of 50% has been shown to reach the system stability in early periods with the least number of re-clustering operations.
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paper_title: A Fog Computing Based System for Selective Forwarding Detection in Mobile Wireless Sensor Networks

paper_content:

Intrusions detection is one of the major issues that worry organizations in wireless sensor networks (WSNs). Many researchers have dealt with this problem and have proposed many methods for detecting different kinds of intrusions such as selective forwarding, which is a serious attack that may obstruct communications in WSNs. However, as the applications of mobile computing, vehicular networks, and internet of things (IoT) are spreading immensely, selective forwarding detection in Mobile Wireless Sensor Networks (MWSNs) has become a key demand. This paper introduces the problem of selective forwarding in MWSNs, and discusses how available techniques for mitigation this problem in WSNs are not applicable in handling the problem in MWSNs due to sensors mobility. Therefore, the paper proposes a model that provides a global monitoring capability for tracing moving sensors and detecting malicious ones. The model leverages the infrastructure of Fog Computing to achieve this purpose. Furthermore, the paper provides a complete algorithm, a comprehensive discussion and experiments that show the correctness and importance of the proposed approach.
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paper_title: Artificial intelligence framework for smart city microgrids: State of the art, challenges, and opportunities

paper_content:

Smart city concepts have gained substantial attention over the last few years, as they apply advances in Information and Communication Technology (ICT) to enhance the quality and efficiency of services and resources. Microgrids are potentially powerful building blocks in the development of smart cities. Motivated by the opportunity, this article examines the factors leadings to the adoption of microgrids for mainstream electrical utilities grids, discusses the benefits that drive the growth, identifies the issues hindering benefit-capture of distributed energy generation inside microgrids, and provides a framework for the application of Artificial Intelligence (AI) to overcome challenges. We examine a simulation framework scenario and useful data sources that can help build AI capabilities within utilities. A brief description of the scalable BluWave-ai framework that leverages deep learning in the data centre is also provided, and AI inference at edge computing nodes and IoT sensors to optimize the benefits from microgrids at residential, neighbourhood, campus, enterprise and community levels is examined.
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paper_title: Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

paper_content:

We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 bits/cell are experimentally demonstrated.
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paper_title: A novel low power phase change memory using inter-granular switching

paper_content:

We propose and demonstrate a new low power phase change memory using a novel 3D network of crystallites with phase change confined to only at grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalcogenide glass is amorphized or crystallized for high or low resistance, we propose a multi-grained structure where we only induce phase change in the inter-grain regions. This not only drastically reduces the phase change volume but also improves the thermal efficiency of the cell. 3D simulation is used to understand the local heating effect. To create the multi-grained structure we have carefully studied the Ge/Sb/Te composition, the doping material and concentration and PVD deposition conditions. Consequently, the switching current can be reduced to 20uA. Furthermore, localizing the heating also reduces thermal disturbance to neighboring cells thus provides excellent pitch scalability.
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paper_title: Novel fast-switching and high-data retention phase-change memory based on new Ga-Sb-Ge material

paper_content:

Attempts to improve the retention so far must sacrifice switching speed. This work explores new phase change material based on pseudobinary GaSb-Ge system. The resulting new phase-change material has demonstrated fast switching speed of 80 ns, long endurance of 1G cycles and excellent data retention that survives 250 oC-300 hrs. The 10 years-220 oC data retention is the best ever reported. It is also the fastest material that can pass the solder bonding criteria for embedded automotive applications.
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paper_title: A low store energy and robust ReRAM-based flip-flop for normally off microprocessors

paper_content:

Normally-off computing (NoC) is one of promising techniques that benefits microsystems with long sleep time. Because NoC can turn off power to achieve zero power consumption and can activate microsystems instantly. This study proposes a novel resistive random access memory (ReRAM)-based nonvolatile flip-flop (NVFF), fabricated using 90-nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. The proposed NVFF uses a complementary structure with one-phase store to mitigate limitation on store energy and was verified as the registers in three pipeline stages of a NV multiplier-and-accumulator macro. The proposed ReRAM-based NVFF, compared with the state-of-the-art complementary design, can reduce store energy by 36.4%, restore time by 64.2%, and circuit area by 42.8%. The proposed design was also superior in reducing restoration error (by 9.44%) under hardship condition compared to NVFFs with a single NV device.
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paper_title: PCRAM-assisted ECC management for enhanced data reliability in flash storage systems

paper_content:

Recent advance in per-cell bit density and semiconductor technology for NAND flash memories have led to significant cost reduction in non-volatile storage implementation. However, the reliability of data stored in flash memory has dramatically decreased, requiring an efficient mechanism to detect and correct bit errors during read and write operations of the data. For this purpose, when user data are often written into a flash page, an Error Correction Code (ECC) for the data is generated and stored in the spare area of the page. ECCs tend to become longer to correct more bit errors, sometimes beyond what is affordable by the spare area. In order to cope with this problem, there have been many attempts to keep ECCs in the data area, as opposed to the spare area of the flash memory. However, an additional mapping mechanism is required to locate ECCs for a given data page, and the program time and cycle are increased due to reading/storing the ECCs. In this paper, we present a novel ECC management mechanism with an assist from PCM for NAND flash storage systems. This technique uses PCM as a temporal storage to store ECCs for the data in log blocks. Later, the pages in log blocks are merged into data blocks with their ECCs kept in the PCM. Our experimental results show that the overhead from ECC management has been improved by 57% and 69% over previous attempts in BAST and FAST mapping schemes, respectively.
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paper_title: A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

paper_content:

In order to realize a digital system with no distinction between “on” and “off,” the computational state must be stored in nonvolatile memory elements. If the energy cost and time cost of managing the computational state in nonvolatile memory can be lowered to the microsecond and picojoule-per-bit level, such a system could operate from unreliable harvested energy, never requiring a reboot. This work presents a nonvolatile D-flip-flop (NVDFF) designed in 0.13- μm CMOS that retains state in ferroelectric capacitors during sporadic power loss. The NVDFF is integrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying power management unit automatically saves and restores the state based on the status of a one-bit indicator of energy availability. Correct operation has been verified over power-cycle intervals from 4.8 μs to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are statistical measurements across 21 \thinspace000 NVDFFs to validate the capability of the circuit to achieve the requisite 10-ppm failure rate for embedded system applications.
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paper_title: Emerging resistive memories for low power embedded applications and neuromorphic systems

paper_content:

In this work, we will focus on the role that new nonvolatile resistive memory technologies can play in emerging fields of application, such as non-volatile logic circuits or neuromorphic circuits, to save energy and increase performance. Concerning the introduction of non-volatile functionalities at the logic level, we will demonstrate hybrid CMOS logic plus ReRAM (specifically CBRAM and OXRAM) circuits for ultra low power FPGA and fixed-logic IC design, as Non Volatile Flip-Flops. Concerning neuromorphic circuits, we will focus on the emulation of synaptic plasticity effects with resistive memory synapses. We will present large-scale energy efficient neuromorphic systems based on ReRAM as stochastic-binary synapses. Prototype applications such as complex visual- and auditory-pattern extraction will be also discussed using feedforward spiking neural networks.
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paper_title: A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

paper_content:

Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs and local nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large store energy ( $\text{E}_{\mathrm {S}}$ ) and long voltage stress time on the device ( $\text{T}_{\mathrm {STRESS}}$ ), due to wide distribution in the write time of NVM device as well as unnecessary writes. Moreover, heavy parasitic load on the power rail cause long wake-up time for restoring data from NVM to FFs. This paper proposes the resistive RAM (ReRAM)-based nvFF with self-write termination (SWT) and reduced loading on power rail to: 1) reduce 93+% waste of $\text{E}_{\mathrm {S}}$ from fast switching or matched cells; 2) suppress endurance and reliability degradation resulted from overprogramming and long $\text{T}_{\mathrm {STRESS}}$ ; and 3) achieve reliable and 26+ times faster restore operation compared with previous nvFFs. We have fabricated a nonvolatile processor and a test chip with SWT-nvFFs using logic-process ReRAM in a 65-nm CMOS process. Measured results show sub-2-ns termination response time and sub-20-ns chip-level restore time.
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paper_title: High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States

paper_content:

ReRAM technologies feature desired properties, e.g. fast switching and high read margin, that make them attractive candidates to be used in non-volatile flip-flops (NVFFs). However, they suffer from limited endurance. Therefore, cell degradation considerations are a necessity for practical deployment in non-volatile processors (NVPs). In this paper, we present two bipolar ReRAM-based NVFFs, Hypnos and Morpheus, with enhanced endurance and energy efficiency. Hypnos reduces the ReRAM electrical stress during set operation while keeping the imposed NVFF area overhead at a minimum. In Morpheus, a write-termination circuit is used to further enhance the ReRAM endurance and energy efficiency at the cost of an affordable area overhead. Moreover, both NVFFs feature run-time tunable resistive states to enable on-line adjustment of the trade-off among endurance, retention, energy consumption, and restore success rate (in case of approximate computing). Experimental results demonstrate that Hypnos reduces the ReRAM set degradation by 91%, on average. Moreover, the write-termination mechanism in Morpheus further reduces the remaining degradation by 93%/97% in set/reset operation, on average. The results also demonstrate enhanced energy efficiency in both NVFFs.
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paper_title: Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology

paper_content:

A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line scheme. Furthermore, 32 instances of 6bit SAR-ADC per bank are built-in with specific logic for adaptive data detection as a sense-amplifier. Experimental results for a bank of 2Gb multi-level density are demonstrated with total read latency of 450ns including word-line settling and the adaptive data detection scheme.
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paper_title: Phase-change random access memory: A scalable technology

paper_content:

Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm × 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.
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paper_title: A novel design for low power Re-RAM based non-volatile flip flop using content addressable memory

paper_content:

Low power consumption is the major issue in electronic systems and memories are the major contributors of the power consumption. Resistive Memories (ReRAMs) has fast access time, ultra-low stand by power and high reliability. Memristor based NV logics like resistive SRAM and resistive CAM memories were proposed and focused on the behavior of resistive property with memory operation. Complementary metal oxide semiconductor technology is used to design nvff with memristor. The resistive CAM has less power and timing compared to resistive SRAM. The total power, delay and area were analyzed and compared for both ReSRAM and ReCAM.
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paper_title: Resistive Memories for Ultra-Low-Power embedded computing design

paper_content:

This paper addresses two technologies as an example of optimized devices for FPGA and fixed-logic IC design (as non volatile Flip-Flops).
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paper_title: Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall

paper_content:

Circuit techniques to realize unlimited program cycle operation in ferroelectric nonvolatile (NV) SRAM have been developed with conventional ferroelectric materials. Program operation is separated into volatile write operation without polarization change and nonvolatile store operation with polarization change. Biasing of the memory cell is optimized to meet reliability requirements. The developed circuit principle is extended to implement a low-power nonvolatile flip-flop applicable to long communication range radio frequency identification tag LSIs.
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paper_title: Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

paper_content:

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near- $V_{\rm T}$ ) or even to the subthreshold (sub- $V_{\rm T}$ ) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present and compare ReRAM-based Non-Volatile Flip-Flop (NVFF) topologies which are optimized for low-voltage operation (including near- $V_{\rm T}$ and sub- $V_{\rm T}$ operation). Three low-voltage NVFF circuit topologies are proposed and evaluated in terms of energy dissipation and reliability. Using topologies with two complementary programmed ReRAM devices, Monte Carlo simulations accounting for parametric variations confirm reliable data restore operation from the ReRAM devices at a sub- $V_{\rm T}$ voltage as low as 400 mV. A topology using a single ReRAM device exhibits lower write energy, but requires a near- $V_{\rm T}$ voltage for robust read. Energy characterization is performed at nominal, near- $V_{\rm T}$ , and sub- $V_{\rm T}$ supply voltages. The minimum energy point is reached for near- $V_{\rm T}$ read operation with a total read+write energy of 735 fJ.
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paper_title: A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write

paper_content:

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and program state, respectively. On the one hand, supply voltage scaling down to the near-threshold (near-VT) or even to the sub-threshold (sub-VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present a ReRAM-based non-volatile flip-flop which is optimized for sub-VT operation. Writing to the ReRAM devices works with a CMOS-compatible supply voltage. Thanks to near-VT and sub-VT operation and as compared to the write energy, which depends on the ReRAM technology, the read consumes only 5.4% of the total read+write energy. Monte Carlo simulations accounting for parametric variations in both the MOS transistors and the ReRAM devices confirm reliable data restore operation from the ReRAM devices at a sub-VT voltage as low as 400 mV, and a standard deviation of up to 5% of the nominal value of the ReRAM resistance.
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paper_title: Hardening techniques for MRAM-based non-volatile storage cells and logic

paper_content:

Magnetic RAM (MRAM) is considered as a promising non-volatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. However, MRAM-based non-volatile storage cells and logic circuits are vulnerable to Single Event Effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are presented in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on Configurable Logic Block to mitigate SET on data paths. By using 65nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness.
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paper_title: Implementing the design of magnetic flip-flop based on swapped MOS design

paper_content:

Flip-flops are used as data storage elements for storing its states. Non-volatile may retain stored information even without power. In this proposed, a power-efficient Magnetic Flip-flop design architecture is implemented to reduce high write energy which required at the time of computing purpose and reduces leakage power. The design is based on multi-threshold swapped MOS design using CMOS technology which reduces writing energy and time. The CMOS technology provides less noise ratio during the design. Thus the proposed method achieves lower power consumption and reduced writing energy and its time.
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paper_title: Low power magnetic flip-flop based on checkpointing and self-enable mechanism

paper_content:

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep submicron CMOS technology. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Torque Transfer MRAM (STT-MRAM) is considered the most promising NVM technology to address this issue thanks to its fast speed, low power, and infinite endurance. In this paper, we present a new design of magnetic flip-flop (MFF) based on STT-MRAM. By integrating multi-context data checkpointing and self-enable switching mechanisms, its overall power can be lowered further than conventional structures. We performed hybrid simulations to validate its functional behaviors and evaluate its performance by using an accurate STT-MRAM spice model and an industrial CMOS 40 nm design kit.
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paper_title: Area-efficient STT/CMOS non-volatile flip-flop

paper_content:

An area-efficient non-volatile flip flop (NVFF) is proposed. The proposed NVFF is comprised of two storages: a conventional flip flop as a static storage during the power-on and a spin-torque transfer magnetic tunnel junction (STT-MTJ) as a temporary storage during the power-off. The area overhead of the MTJ block is minimized by reusing a part of the existing flip flop. The energy overhead for the temporary storage is reduced by a current reuse technique. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10nm technology node. Results indicate that area overhead is 6.9% normalized to the conventional flip flop and that the energy overhead is 0.2pJ. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1× and the energy by 1.5×.
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paper_title: A ferroelectric-based non-volatile flip-flop for wearable healthcare systems

paper_content:

The low-power FE-based NVFF is developed by reduction of FE capacitor size. In the proposed NVFF, coupled FE capacitors with complementary data storage are introduced. The use of complementarily stored data in coupled FE capacitors achieves 88% FE capacitor size reduction while maintaining a wide read voltage margin of 240 mV (minimum) at 1.5 V, which results in 2.4 pJ low access energy with 10-year, 85°C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 μs for 10-year data retention, and 170 ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. As a design example, the proposed NVFF is applied to 32-bit CPU in a vital sensor LSI for wearable healthcare applications. The vital sensor LSI consists of an electrocardiogram (ECG) sensor, the 32-bit CPU core with NVFF, and a 16-Kbyte FE-based non-volatile memory (NVRAM) for data and instruction. Because the frequency range of vital signals is low, both the standby power reduction and sleep time maximization is important to system level power reduction. Its standby current can be cut when the state of CPU core transits to deep sleep. Then the data in the memory and register values of CPU core in the NVFF are stored sequentially to ferroelectric capacitors. The implementation result demonstrates that 87% of total power dissipation during measurement of the heart rate can be reduced with 64% area overhead using 130-nm CMOS with Pb(Zr, Ti)O3(PZT) thin films.
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paper_title: Simulation of the RRAM-based flip-flops with data retention

paper_content:

A RRAM-based non-volatile flip-flop (NYFF) is designed to meet energy efficiency requirement for standby-power-critical applications in the deployment solution of IoT (Internet of Things). Adding only a pair of 1T1R cell into slave latch of a traditional FF can cut off the standby leakage at the cost of 4pJ write energy, and 20ps data retention time upon ideal power-on. The NVFF circuit is simulated and analyzed in HSPICE with a SPICE compact model of oxide-based RRAM on the conductive filament evolution model.
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paper_title: Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

paper_content:

A nonvolatile magnetic flip-flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An MFF test chip was fabricated with the process. The chippsilas functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of SoCs dramatically.
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paper_title: OxRAM-based non volatile flip-flop in 28nm FDSOI

paper_content:

This paper presents a robust OxRAM-based nonvolatile flip-flop (NVFF) solution, designed for deep nano-scaled CMOS technologies. Forming, set and reset operations rely on a reliable design approach using thin gate oxide CMOS. The NVFF is benchmarked against a standard FF in 28nm CMOS FDSOI. Non-volatility is added with minimal impact on the FF performances.
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paper_title: A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability

paper_content:

A ferroelectric-based (FE-based) non-volatile flip-flop (NWF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85°C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6/fS for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr, Ti)O 3 (PZT) thin Alms.
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paper_title: Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

paper_content:

In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.
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paper_title: Multi-bit non-volatile spintronic flip-flop

paper_content:

As leakage increases proportionally with the technology downscaling, it becomes extremely challenging to manage to meet the total power budget. This is because, CMOS-based logic blocks can not be completely power-gated as their flip-flops always require a retention supply to hold the system states. Alternatively, their data can be stored in a separate memory during the standby mode, however, that results in a huge area and energy overhead. Spin Transfer Torque (STT) based nonvolatile flip-flops can offer normally-off/instant-on computing features to reduce leakage by complete power shut-down without the need to transfer and restore system states separately. The non-volatile component of such flip-flops can be easily shared for the overall design optimizations. In this paper, we design a unique multi-bit non-volatile flip-flop architecture using STT devices to reduce the area and energy costs associated with nonvolatile components. This architecture is developed based on the resource sharing principle using a custom design that enables the optimization for the area and energy consumption. Moreover, we have developed a framework in which we have replaced the conventional neighbor flipflops in the layout with our proposed multi-bit non-volatile designs. Results show that using our multi-bit flip-flop architecture, we improve the system-level area and energy by 26% and 14% in average, respectively, compared to the standard single-bit non-volatile flip-flop design.
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paper_title: A non-volatile flip-flop in magnetic FPGA chip

paper_content:

In this paper, the authors propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed. This flip-flop is based on MRAM (magnetic RAM) technology on standard CMOS. In this non-volatile flip-flop design, the authors use magnetic tunnel junctions (MTJ) as storage element. Contrary to the complex sense amplifier circuit in standard MRAM circuits, a simple one based on SRAM cell is used to couple with two MTJs per bit in magnetic logic circuit. The flip-flop works exactly as a classical flip-flop hut the information is stored simultaneously in the two MTJs, which makes this flip-flop non-volatile. As the writing frequency has a strong impact on the power consumption, the MTJ writing frequency is designed to be defined by the users depending on different usage. During the startup or reset phase, the flip-flop master stage is used as the MTJ sense amplifier and the flip-flop is initialized to the previously stored state in about 200 ps. This figure has been demonstrated by electrical simulation on a 90 nm CMOS technology and with a complete and precise MTJ model
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paper_title: A novel non-volatile flip-flop using a ferroelectric capacitor

paper_content:

A novel structure for a non-volatile flip-flop (NVFF) was proposed combining the in-series structure (MFMIM) of a ferroelectric capacitor and a dielectric capacitor followed by a CMOS-inverter. It was demonstrated that the proposed NVFF acted as a flip-flop compatible device. Also, even if the entire power supply was turned off, if it was turned on again within 6000 seconds, the last information was restored. A detailed examination of the time dependence of the leakage current of each component revealed that the retention property of NVFF was chiefly controlled by the characteristics of the dielectric relaxation current of the measured ferroelectric capacitor, taking into account the whole history of applied voltage to the ferroelectric capacitor.
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paper_title: A Low-Power Low-VDD Nonvolatile Latch Using Spin Transfer Torque MRAM

paper_content:

The high leakage power due to the scaling down of the process nodes has been one of the critical issues in CMOS circuits, especially in the sleep power critical systems. The emerging nonvolatile flip-flops (nvFFs) with fast saving and restoration speed and zero sleep power may be the solution to address the high sleep power issue. However, the “source degeneration” and/or “serial write” issues of the reported works may significantly limit the scalability. We propose a novel nvFF using two-phase write approach and complementary write drivers, which reduces more than 38% power for the saving operation and also scales VDD down to 1 V and below. Our proposed nvFF has the closest flip-flop (FF) performance as the CMOS retention FF. Moreover, it has more than 50% area reduction compared to the smallest nvFF in the prior arts.
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paper_title: Compact low-power instant store and restore D flip-flop using a self-complementing spintronic device

paper_content:

To simplify power-gating requirements in ultra-low-power architectures, design strategies for low-power non-volatile flip-flops (F/Fs) are sought, for which the utilisation of spintronic devices offers a promising option. A D F/F that utilises a five-terminal spintronic device for non-volatile state holding in an intrinsically self-complementing fashion is introduced. This self-complementing device can be exploited to reduce overhead interfacing circuitry in order to realise a compact ten transistors with one spintronic device D F/F with instant store and restore functionality, while consuming <9 µW of power.
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paper_title: Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

paper_content:

This paper presents a new nonvolatile magnetic flip-flop (MFF) for standby-power-critical applications. An MFF primitive cell for design libraries has been developed using 150 nm, 1.5 V CMOS and 240 nm MRAM processes. It has advantages over other nonvolatile flip-flops in high-speed store operations without endurance limitations. It also has high design compatibility with conventional CMOS LSI designs because it does not include any additional power lines and special transistors. A toggle frequency of 3.5 GHz was achieved by a SPICE simulation, which is comparable to that of a normal CMOS DFF in the same generation. The maximum frequency in a store operation was also estimated to be 500 MHz with 1-ns current width for the data backup. An MFF test chip, which includes 16-stage 8-bit shift register using MFFs, was fabricated with these processes. A 333 MHz store operation was measured without failed bits. The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically.
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paper_title: High-Speed, Low-Power, Magnetic Non-Volatile Flip-Flop With Voltage-Controlled, Magnetic Anisotropy Assistance

paper_content:

A magnetic non-volatile flip-flop (MNV-FF) design, with the assistance of voltage-controlled magnetic anisotropy (VCMA) effect, is proposed for low-power and high-speed applications. The MNV-FF employs perpendicular-anisotropy magnetic junnel junctions (MTJs) and exploits the VCMA effect for assisting data backup operations, in cooperation with either spin-transfer torque (STT) or spin-Hall effect (SHE). Thanks to the VCMA assistance, the required STT or SHE current density and pulse duration can be greatly reduced for MTJ switching, resulting in faster and more energy-efficient operations. Our simulation results show that the proposed VCMA-assisted MNV-FFs can achieve 98.4% and 74.6% improvement in data backup energy, and 89.5% and 19.0% improvement in data backup delay, compared to conventional STTand SHE-based MNV-FFs, respectively.
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paper_title: MTJ based non-volatile flip-flop in deep submicron technology

paper_content:

The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technology) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.
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paper_title: Address Data Event Representation (ADER) for Efficient Neuromorphic Communication

paper_content:

A new form of address event representation (AER) is presented that is suitable for simultaneous data conversion and communication in large neuromorphic computational systems. The proposed ADER representation allows for efficient use of available communication bandwidth and ensures that no information is lost through collisions despite having a predominantly asynchronous scheme.
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paper_title: Address-data event representation for communication in multichip neuromorphic system architectures

paper_content:

A new approach to asynchronous parallel-data conversion and transmission for computation in large neuromorphic distributed systems is reported. The proposed address data event representation (ADER) allows for efficient use of available bandwidth and ensures that no information is lost through collisions despite having a predominantly asynchronous nature.
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paper_title: A low power architecture for AER event-processing microcontroller

paper_content:

This paper presents a custom MSP430™-compatible microcontroller, specifically tailored for quasi-digital processing Address Event Representation (AER) events. Main target applications are fully reprogrammable sensory systems where events pre-processing has to be carried out by means of easily-tunable elaboration algorithms; a microcontroller-based design could provide the right trade-off between flexibility and performance. Key features are good time resolution, high reactivity, on-demand only processing and power consumption reduction. The proposed architecture has been analyzed and compared with an open source MSP430TM-compliant microcontroller (openMSP430) in terms of performance and power consumption. Accurate and wide cases-spectrum simulations (targeting ASIC technology) show an average power consumption reduction ranging from 50 % (same operating frequency) up to 79 % (same maximum event rate); equivalently, with the same power budget, an average improvement of either resolution of 84 % or maximum event rate of 1020 % is obtained.
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paper_title: Low-latency asynchronous networking for the IoT: Routing analog pulse delays using IR-UWB

paper_content:

The advances in the design of circuits and systems for low-complexity and ultra-low power IR-UWB communication has revealed the possibility of transmitting and receiving analog information, by fully exploiting the delay resolution among asynchronously transmitted pulses. This paper investigates on the feasibility of low-latency asynchronous networking through the devising of a specific system model built onto high-threshold IR-UWB transceivers using a bottom-up approach. Compared to the other wireless technologies low-latency and event-driven analog data transmission are distinctive features specifically enabled by the UWB pulses time resolution combined with asynchronous threshold detectors receivers. Revisiting networking in this cross-sectional light can possibly open the way to a significant number of solutions to critical applications and consequent research & development.
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paper_title: Integrated bio-inspired systems: An event-driven design framework

paper_content:

Human robotics is an emerging research field aiming at the conjugation of mechanical and electrical engineering with biology; neuromorphic engineering has shown that it is possible to develop effective systems mimicking key aspects of biological systems, such as spiking (event driven) information processing and communication, adaptive and learning behavior. However, most of these solutions are tightly focused on one biological aspect, often aiming to precisely replicate it with a one-to-one mapping between the electronic and biological domain. We believe that, to successfully “port” biological strengths to the engineering world, such a tight relationship has to be loosened, and a new multi-domain co-design approach has to be devised. By exploiting the properties of the information processing, we are able to better design and integrate information transmission subsystems, with particular regard to the power consumption; by taking into account low-power requirements/constraints, we can develop energy-aware information processing modules. Designing the whole systems in a modular way, allows us to easily re-design a full-fledged system for new scenarios/applications. The research regards the implementation of discrete component systems as well, so that integrated circuits or proof-of-concept implementations can be easily validated.
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paper_title: The rapidly tuned analog-to-information converter

paper_content:

This paper explores using a rapidly tuned, narrowband device as an analog-to-information converter (AIC). This concept is applied to a rapidly tuned, instantaneously narrowband antenna. Such a setup is advantageous in cognitive radio, where an antenna designed for communicating over a portion of the spectrum may be used to meet the wideband spectrum sensing requirement. A method for reducing the bandwidth of the control signal below the Nyquist rate is also discussed.
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paper_title: Modeling the Connectivity of Data-Channel-Based Bluetooth Low Energy Mesh Networks

paper_content:

Bluetooth Low Energy (BLE) has become one of the most popular low-power wireless technologies. While BLE was originally designed for star topology networks only, recent developments have focused on enabling mesh network topology support for BLE. An emerging category of BLE mesh network initiatives is based on routing data units over BLE data channels. This letter investigates the fundamental connectivity parameters of data-channel-based BLE mesh networks, such as the probability of no isolation of a node and network $K$ -connectivity. We provide an analytical model for both parameters which is validated by means of extensive simulations.
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paper_title: Cluster-Based Mobility Supporting WMN for IoT Networks

paper_content:

IoT (Internet of Things) network has recently emerged as a promising technology for various fields. To realize IoT service, access points are needed for heterogeneous terminals, sensors, actuators, laptop and mobile terminal. Wireless Mesh Network (WMN) could be a good solution. WMN consists of mesh points (MPs) that serve as a relay for other MPs for extension of network coverage. Reliable service coverage is given for network users who suffer from lack of wired infrastructure. WMN has self-recovery scheme, so it gives reliability and cost-effective. Most researches about WMN consider MPs without mobility. However, mobile MPs could give flexibility to IoT network. In this paper, MPs have mobility for flexible IoT services. It is considered that terminals which have same characteristics form a cluster and mobile MP gives access to those terminals. However, mobility of MPs degrade performance of network, packet success ratio, delay and jitter. Especially, frequent link breakages and extended hidden nodes problem occur. In this paper, Group mobility based clustering and multi-channel MAC schemes are used to overcome results of mobility. Moreover, cluster-based multi-channel framework is suggested for reliable wireless communication for IoT services.
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paper_title: Performance trade-offs and design limitations of analog-to-information converter front-ends

paper_content:

This paper evaluates the impact of circuit impairments on the energy cost and performance limitations of analog-to-information converters (AIC). In applications where signal frequencies are high, but information bandwidths are low, AICs have been proposed as a potential solution to overcome the resolution and performance limitations of sampling jitter in high-speed analog-to-digital converters (ADC). Although the AIC architecture facilitates slower ADCs, the signal encoding, typically realized with a mixer-like circuit, still occurs at the Nyquist frequency of the input to avoid aliasing. We show that the jitter of this mixing stage limits the achievable AIC resolution. In this work, the end-to-end system evaluation framework is designed to analyze these limitations as well as the relative energy-efficiency of AICs versus ADCs across the resolution, receiver gain and signal sparsity. The evaluation shows that AICs improve the resolution by 1 bit when the signal of interest is very sparse, and enable 2× in energy savings when no pre-amplification is required.
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paper_title: A Systematic Review of Compressive Sensing: Concepts, Implementations and Applications

paper_content:

Compressive Sensing (CS) is a new sensing modality, which compresses the signal being acquired at the time of sensing. Signals can have sparse or compressible representation either in original domain or in some transform domain. Relying on the sparsity of the signals, CS allows us to sample the signal at a rate much below the Nyquist sampling rate. Also, the varied reconstruction algorithms of CS can faithfully reconstruct the original signal back from fewer compressive measurements. This fact has stimulated research interest toward the use of CS in several fields, such as magnetic resonance imaging, high-speed video acquisition, and ultrawideband communication. This paper reviews the basic theoretical concepts underlying CS. To bridge the gap between theory and practicality of CS, different CS acquisition strategies and reconstruction approaches are elaborated systematically in this paper. The major application areas where CS is currently being used are reviewed here. This paper also highlights some of the challenges and research directions in this field.
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paper_title: VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter

paper_content:

One of the key tasks in cognitive radio and communications intelligence is to detect active bands in the radio-frequency (RF) spectrum. In order to perform spectral activity detection in wideband RF signals, expensive and energy-inefficient high-rate analog-to-digital converters (ADCs) in combination with sophisticated digital detection circuitry are typically used. In many practical situations, however, the RF spectrum is sparsely populated, i.e., only a few frequency bands are active at a time. This property enables the design of so-called analog-to-information (A2I) converters, which are capable of acquiring and directly extracting the spectral activity information at low cost and low power by means of compressive sensing (CS). In this paper, we present the first very-large-scale integration (VLSI) design of a monolithic wideband CS-based A2I converter that includes a signal acquisition stage capable of acquiring RF signals having large bandwidths and a high-throughput spectral activity detection unit. Low-cost wideband signal acquisition is obtained via CS-based randomized temporal subsampling in combination with a 4-bit flash ADC. High-throughput spectrum activity detection from the coarsely quantized and compressive measurements is achieved by means of a massively-parallel VLSI design of a novel accelerated sparse spectrum dequantization (ASSD) algorithm. The resulting monolithic A2I converter is designed in 28 nm CMOS, acquires RF signals up to 6 GS/s, and the on-chip ASSD unit detects the active RF bands at a rate 30 × below real-time.
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paper_title: A rakeness-based design flow for Analog-to-Information conversion by Compressive Sensing

paper_content:

Classical design of Analog-to-Information converters based on Compressive Sensing uses random projection matrices made of independent and identically distributed entries. Leveraging on previous work, we define a complete and extremely simple design flow that quantifies the statistical dependencies in projection matrices allowing the exploitation of non-uniformities in the distribution of the energy of the input signal. The energy-driven reconstruction concept and the effect of this design technique are justified and demonstrated by simulations reporting conspicuous savings in the number of measurements needed for signal reconstruction that approach 50%.
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paper_title: IEEE 802.15.4 Thread Mesh Network – Data Transmission in Harsh Environment

paper_content:

the goal of the publication is to describe outcome form environmental tests of wireless Thread mesh network which was designed for indoor environment monitoring. The sensor is based on NRF52840 SoC (System on Chip) and allows to monitor parameters like: temperature, humidity, atmospheric pressure and light luminescence. For implementation of wireless communication OpenThread Thread protocol stack was used. All test were set in office building, where the harsh environmental condition, generated by hundreds of wire and wireless devices create perfect test place for verifying network reliability. The paper contains description of hardware and software solution, tests setup and outcomes concluded from collected data.
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paper_title: Theory and hardware implementation of an analog-to-Information Converter based on Compressive Sensing

paper_content:

In the practical application, Nyquist-Shannon sampling theorem has brought great challenges to high sampling rate, fast processing speed and hardware equipment. In the context, a new theory called Compressive Sensing (CS) has been proposed, which can break the restriction of the Nyquist theorem for sparse signal. The Analog-to-Information Converter(AIC) makes the CS theory into practical, which can replace the traditional Analog-to-Digital Converter (ADC) to sample the high rate signals at lower rate and solve the bottleneck of Shannon-Nyquist theorem. In this paper, we will analyze the mathematical model and architecture of AIC, Finally we proposed a hardware implementation for AIC.
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paper_title: A Survey on Energy Efficient Routing for Delay Minimization in IoT Networks

paper_content:

The IoT networks consists of many sensor nodes with limited computational power and energy (battery power). The lifetime of the node depends upon its battery size and volume of data processing (sensing and routing). The connectivity hole is one of the major problems in the IoT networks. The connectivity holes are the nodes, which can't process the data properly due to the software malfunctioning or attack. Hence, it becomes very necessary to eliminate the connectivity holes from the routing paths to avoid the data drop and reduce the delay. The end-to-end delay and data drop rate can be improved by designing the new smart routing protocol scheme based upon the segmental computation for smart cities with the ability to avoid or eliminate the connectivity holes from the routing paths and to handle the larger volumes of data across the multiple paths. This means the network divided in the individual cluster will involve the each cluster's nodes individually to discover the stable and robust path. This path is maintained within the clusters, rather than maintaining the whole source to destination path at once. The proposed work will handle the dynamic routing for the mobile nodes in the given heterogeneous wireless mesh network. The backward and forward technique will be used to detect the presence of connectivity hole in the network. The dynamic route update algorithm will be proposed and designed for the dynamic route updation in the segmental (micro) routing mechanism when operating within the given zone. The inter-zone handovers will be treated with the complete route updates in order to remove the chances of bad route origination.
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paper_title: Wireless Mesh Networks in IoT networks

paper_content:

Internet of Things is one of the hottest topics in both industry and academia of the communication engineering world. On the other hand, wireless mesh networks, a network topology that has been discuss for decades that haven't been put into use in large scale, can make a difference when it comes to the network in the IoT world today. This paper is a brief introduction of how these technologies has the possibility to come together and how to integrate the mesh network into existing IoT networks to potentially make a difference in the new era.
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paper_title: Energy efficient wireless sensor networks utilizing adaptive dictionary in compressed sensing

paper_content:

Wireless Sensor Networks (WSNs) are fundamental blocks of Internet of Things (IoT) which made it to proliferate into many real-time diversified applications. Typically, WSN nodes are small and battery powered devices. Hence, energy efficient data aggregation method which maximizes the network lifetime is the paramount importance. Compressed Sensing (CS) is one of the approaches proves to be very promising for energy efficient data aggregation in WSN. The sparsity of the sensor data can change significantly due to their time varying nature and it affects the recovery of the measured signal. Most of the existing CS aided data aggregation methods for WSN are neither optimized nor address the issue of change in data sparsity, which demands additional energy to maintain low reconstruction accuracy. Thus, variation in the sparsity of the sensor data makes data aggregation to be energy inefficient that inherently reduces network lifetime. To overcome this, we propose an optimal method for CS-WSN where we use a dictionary as a sparsifier that learns with adaptive sparse training data. The proposed method achieves minimum reconstruction error by accounting changes in the data sparsity while data can be delivered to the sink with low energy consumption thereby improving energy efficiency.
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paper_title: μPnP-Mesh: The plug-and-play mesh network for the Internet of Things

paper_content:

Deploying and customizing networks of Internet of Things (IoT) devices remains extremely challenging. This complexity has two main sources. First, end-users must integrate diverse sensor and actuator peripherals with IoT devices to realize their application. Second, the resulting system must provide reliable mesh networking in harsh network environments at extremely low power. This paper addresses both problems by proposing μPnP-Mesh, which combines the ease of use of μPnP with the industrial performance of SmartMesh IP. μPnP provides a low-power and low-cost method for achieving plug-and-play integration of peripherals with embedded IoT devices; SmartMesh IP provides low-power reliable mesh networking. With a true plug-and-play user experience and a lifetime above 6.5 years on a pair of AA batteries, μPnP-Mesh is a ready-to-use game-changing solution for applications such as home, building and factory automation.
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paper_title: Hardware-Algorithms Co-Design and Implementation of an Analog-to-Information Converter for Biosignals Based on Compressed Sensing

paper_content:

We report the design and implementation of an Analog-to-Information Converter (AIC) based on Compressed Sensing (CS). The system is realized in a CMOS $180~{\rm nm}$ technology and targets the acquisition of bio-signals with Nyquist frequency up to $100~{\rm kHz}$ . To maximize performance and reduce hardware complexity, we co-design hardware together with acquisition and reconstruction algorithms. The resulting AIC outperforms previously proposed solutions mainly thanks to two key features. First, we adopt a novel method to deal with saturations in the computation of CS measurements. This allows no loss in performance even when 60% of measurements saturate. Second, the system is able to adapt itself to the energy distribution of the input by exploiting the so-called rakeness to maximize the amount of information contained in the measurements.
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paper_title: Analog-to-information conversion of sparse and non-white signals: Statistical design of sensing waveforms

paper_content:

Analog to Information conversion is a new paradigm in signal digitalization. In this framework, compressed sensing theory allows to reconstruct sparse signal from a limited number of measures. In this work, we will assume that the signal is not only sparse but also localized in a given domain, so that its energy is concentrated in a subspace. We will present a formal and quantitative discussion to explain how localization of sparse signals can be exploited to improve the quality of the reconstructed signal.
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paper_title: Energy Efficient Analog-to-Information Converter for Biopotential Acquisition Systems

paper_content:

Analog to Information Converter (AIC) is the heart of an energy efficient bio potential acquisition system using compressed sensing (CS) technique. This paper presents the design and implementation of AIC. Charge redistribution Digital to Analog Convertors (DAC) is used for power and area efficiency. A successive approximation register (SAR) control logic and dynamic latch type comparator are used for low power operation. We have used 65nm CMOS technology for this design. The pseudorandom clock generator enables random under-sampling for the 12-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). The designed AIC achieves a sample rate of 0.5 KS/s, an ENOB 9.54 bits, FOM 187 fJ/conv-step and consumes 69.66 nW with 1 V power supply.
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paper_title: A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master–Slave PLL Synthesis

paper_content:

This paper presents an ultralow power asynchronous logic transmitter operating at 1 Gpps that achieves pulse synthesis using a double phase-locked loop (PLL) architecture for applications exploiting large-scale neuronal interfacing with CMOS probes. The 4 GHz center frequency OOK transmitter synthesizes 500 ps duration pulses from a 31.25 MHz crystal oscillator using a cascade of a master and a slave PLL with the latter locked to the former. Both PLLs are implemented with CMOS digital cells and ring oscillator-based VCO. A prototype fabricated in a 130 nm RFCMOS process operates at a measured 5 pJ/pulse energy budget for an active area of 0.04 mm2. To generate timing references and packets for high data rate recording devices, the synthesizer core feeds also a logic interface operating at 250 MHz with four 1.2–3.3 V external parallel channels. From reset time, the master–slave PLL combination achieves locking in a measured time of 450 ns, settling is resolved in $\sim 4~\mu \text{s}$ , and the output pulses across the antenna load are generated with a 3.42 ps RMS jitter standard deviation. The obtained phase noise of a continuous OOK stream at 1 and 4 GHz, 1 MHz offset, is −103 and −93 dBc/Hz, respectively.
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paper_title: A 1 Gpps asynchronous logic OOK IR-UWB transmitter based on master-slave PLL synthesis

paper_content:

This paper presents an asynchronous logic high data rate IR-UWB transmitter operating with a single 31.25 MHz reference that robustly synthesizes 1 GHz rate pulses to enable sub-meter range neural data transmission. It is designed for a low power CMOS-based implantable electrode array and operates with a master-slave PLL cascade and a simple static CMOS logic combining. The master PLL consumes a simulated 1 mW power, and locking is based on the evolution of three non-overlapping feedback loops whose switching is controlled by a duty cycling window. The transmitter core enables OOK data transmission with a ∼3.1 pJ/pulse energy budget, comprising master and slave PLL and antenna buffer contributions. The paper introduces the TX core architecture, details the master PLL operation and presents simulation results obtained in a 130 nm RFCMOS technology prior to measurement verification.
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paper_title: Fast and Adaptive Mesh Access Control in Low-Power and Lossy Networks

paper_content:

Low-power and lossy networks (LLNs) comprised of thousands of embedded networking devices connected to the larger Internet architecture can be used in a variety of applications, leading to the emerging concept of the Internet of Things (IoT). Access control and key management in such LLN is a big challenge since authentication, authorization, and key management process involves several handshakes of large size packets over low bandwidth and high latency links through a bottlenecked LLN border router (LBR). This may result in significant wasted bandwidth and slow authentication completion time. The goal of this work is to propose a “fast and adaptive node authentication mechanism for low-power lossy networks,” called FINALLY , that solves these problems and significantly improves the efficiency and speed of mesh authentication process. We evaluate FINALLY through simulations and show that it allows devices to authenticate quickly without repeated authentication failures, reduces unnecessarily wasted transmissions, and improves the overall completion time of the authentication process.
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paper_title: Low power wireless mesh network over the TDMA link for connecting things

paper_content:

In this paper, a low power wireless mesh network over channel hopped TDMA links is introduced as an area network for connecting things. The links and virtual links over the IEEE 802.15.4e DSME MAC are established and unbalanced cluster-tree based network formation provides routed link paths for the things to have deterministic-latency and scalable wireless mesh connectivity.
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paper_title: Joint analog-to-information conversion of heterogeneous biosignals

paper_content:

In this work, we propose an analog-to-information conversion based sensing protocol for the joint acquisition of signals in a typical body sensor network composed of different kinds of sensing devices. The proposed system is based on the compressive sensing paradigm, and jointly encodes sparse and non-sparse signals with an advantage in terms of required transmission bits and achieved signal-to-noise ratio with respect to the standard case of disjoint signal acquisition. A theoretical analysis is supported by some practical examples which show how the proposed system is able to outperform traditional approaches.
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paper_title: A multi banked — Multi ported — Non blocking shared L2 cache for MPSoC platforms

paper_content:

On-chip L2 cache architectures, well established in high-performance parallel computing systems, are now becoming a performance-critical component also for multi/many-core architectures targeted at lower-power, embedded applications. The very stringent requirements on power and cost of these systems result in one of the key challenges in many-core designs, mandating the deployment of highly efficient L2 caches. In this perspective, sharing the L2 cache layer among all system cores has important advantages, such as increased utilization, fast inter-core communication, and reduced aggregate footprint because no undesired replication of lines occurs. This paper presents a novel architecture for a shared L2 cache system with multi-port and multi-bank features. We target this L2 cache to a many-core platform based on hierarchical cluster structure that does not employ private data caches, and therefore does not require complex coherency mechanisms. In fact, our shared L2 cache can be seen logically as a Last Level Cache (LLC) adopting the terminology of higher-performance many-core products, although in these latter the LLC is more often an L3 layer. Our experimental results show a maximum aggregate bandwidth of 28GB/s (89% of the maximum channel capacity) for 100% hit traffic with random banking conflicts, as a realistic case. Physical implementation results in 28nm Fully-Depleted-Silicon-on-Insulator (FDSoI) show that our L2 cache can operate at up to 1GHz with a memory density loss of only 20% with respect to an L2 scratchpad for a 2 MB configuration.
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paper_title: CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories

paper_content:

MPSoCs with hierarchical communication infrastructures are promising architectures for low power embedded systems. Multiple CPU clusters are coupled using an Network-on-Chip (NoC). Our CoreVA-MPSoC targets streaming applications in embedded systems, like signal and video processing. In this work we introduce a tightly coupled shared data memory to each CPU cluster, which can be accessed by all CPUs of a cluster and the NoC with low latency. The main focus is the comparison of different memory architectures and their connection to the NoC. We analyze memory architectures with local data memory only, shared data memory only, and a hybrid architecture integrating both. Implementation results are presented for a 28 nm FD-SOI standard cell technology. A CPU cluster with shared memory shows similar area requirements compared to the local memory architecture. We use post place and route simulations for precise analysis of energy consumption on both cluster and NoC level using the different memory architectures. An architecture with shared data memory shows best performance results in combination with a high resource efficiency. On average, the use of shared memory shows a 17.2 percent higher throughput for a benchmark suite of 10 applications compared to the use of local memory only.
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paper_title: NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems

paper_content:

Energy consumption is one of the prominent design constraints of multi-core embedded systems. Since the memory subsystem is responsible for a considerable portion of energy consumption of embedded systems, Non-Volatile Memories (NVMs) have been proposed as a candidate for replacing conventional memories such as SRAM and DRAM. The advantages of NVMs compared to conventional memories are that they consume less leakage power and provide higher density. However, these memories suffer from increased overhead of write operations and limited lifetime. In order to address these issues, researchers have proposed NVM-aware memory management techniques that consider the characteristics of the memories of the system when deciding on the placement of the application data. In systems equipped with memory management unit (MMU), the application data is partitioned into pages during the compile phase and the data is managed at page level during the runtime phase. In this paper we present an NVM-aware data partitioning and mapping technique for multi-core embedded systems equipped with MMU that specifies the placement of the application data based on access pattern of the data and characteristics of the memories. The experimental results show that the proposed technique improves the energy consumption of the system by 28.10 percent on average.
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paper_title: PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision

paper_content:

Novel pervasive devices such as smart surveillance cameras and autonomous micro-UAVs could greatly benefit from the availability of a computing device supporting embedded computer vision at a very low power budget. To this end, we propose PULP (Parallel processing Ultra-Low Power platform), an architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability that exploit the capabilities of the STMicroelectronics UTBB FD-SOI 28nm technology. We show that PULP performance can be scaled over a 1x-354x range, with a peak theoretical energy efficiency of 211 GOPS/W. We present performance results for several demanding kernels from the image processing and vision domain, with post-layout power modeling: a motion detection application that can run at an efficiency up to 192 GOPS/W (90 % of the theoretical peak); a ConvNet-based detector for smart surveillance that can be switched between 0.7 and 27fps operating modes, scaling energy consumption per frame between 1.2 and 12mJ on a 320 ×240 image; and FAST + Lucas-Kanade optical flow on a 128 ×128 image at the ultra-low energy budget of 14 μJ per frame at 60fps.
---

Title: Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World

Section 1: Introduction
Description 1: This section introduces the Internet of Things (IoT) paradigm, its growing impact, and the need for hardware considerations in implementing edge computing in IoT.

Section 2: Definitions and Motivations
Description 2: This section discusses the increasing number of IoT devices, their requirements for low power consumption, and their sustainable design considerations.

Section 3: Ultra-Low Power MCU Architectures
Description 3: This section describes the main hardware components of typical IoT nodes focusing on ultra-low power solutions and their architectures.

Section 4: IO Architecture
Description 4: This section examines the role of peripherals in IoT devices, their interfaces, and techniques for optimizing off-chip and inter-chip communication.

Section 5: Communication and Security
Description 5: This section covers Internet communication systems and the security challenges associated with IoT devices, including encryption and protection against hacking.

Section 6: Non-Volatile Memories
Description 6: This section explores non-volatile memory technologies that address data retention during low power modes and their integration into IoT devices.

Section 7: Power Management
Description 7: This section discusses various power management techniques, including dynamic and static power optimization, to enhance battery life and device efficiency.

Section 8: Near-Threshold MCU Architectures
Description 8: This section focuses on the challenges and benefits of operating transistors in the near-threshold region to achieve ultra-low power operation.

Section 9: Data Processing
Description 9: This section reviews methods for efficient data processing in IoT nodes, including architectural optimizations and specialized instructions for power savings.

Section 10: Compressive Sensing
Description 10: This section details algorithmic techniques such as compressive sensing to reduce data transmission requirements and enhance energy efficiency.

Section 11: From Single Core to Multi Core
Description 11: This section explains the transition from single-core to multi-core architectures to handle increasing computational demands and improve parallel processing efficiency.

Section 12: Memory Hierarchy for Multi-Core Domain
Description 12: This section addresses the complexities of memory management in multi-core systems and innovative solutions to optimize energy consumption and performance.

Section 13: Example of a Many-Core Low-Power Processor: PULP
Description 13: This section presents a case study on the PULP platform, an ultra-low power many-core architecture, showcasing its features and performance benefits.

Section 14: Conclusions and Future Perspectives
Description 14: This section summarizes the survey findings, discusses future trends in IoT and Edge Computing, and emphasizes the need for ongoing research and innovation.