Recent Development in Analog Computation - A Brief Overview
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paper_title: Analog Versus Digital: Extrapolating from Electronics to Neurobiology

paper_content:

We review the pros and cons of analog and digital computation. We propose that computation that is most efficient in its use of resources is neither analog computation nor digital computation but, rather, a mixture of the two forms. For maximum efficiency, the information and informationprocessing resources of the hybrid form must be distributed over many wires, with an optimal signal-to-noise ratio per wire. Our results suggest that it is likely that the brain computes in a hybrid fashion and that an underappreciated and important reason for the efficiency of the human brain, which consumes only 12 W, is the hybrid and distributed nature of its architecture.
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paper_title: An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

paper_content:

A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively
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paper_title: A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC

paper_content:

An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 muW in the test, corresponding to a figure of merit of 65 f J/conversion-step.
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paper_title: A low-power dynamic comparator with time-domain bulk-driven offset cancellation

paper_content:

This paper presents a low-power dynamic comparator utilizing a novel time-domain bulk-driven offset cancellation scheme with minimal additional power consumption and delay. It uses an open loop dynamic phase detector to achieve very high precision. The circuit is designed in a 0.6-µm process. The simulation results show that the circuit consumes 540 nA current at 100 kHz clock frequency and the proposed offset cancellation scheme is able to reduce the input referred offset to within 25 µV from an initial value of 20 mV.
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paper_title: A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation

paper_content:

A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 μV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 μW of power, or 23 pJ of energy per comparison.
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paper_title: Reproducibility and variability in neural spike trains

paper_content:

To provide information about dynamic sensory stimuli, the pattern of action potentials in spiking neurons must be variable. To ensure reliability these variations must be related, reproducibly, to the stimulus. For H1, a motion-sensitive neuron in the fly's visual system, constant-velocity motion produces irregular spike firing patterns, and spike counts typically have a variance comparable to the mean, for cells in the mammalian cortex. But more natural, time-dependent input signals yield patterns of spikes that are much more reproducible, both in terms of timing and of counting precision. Variability and reproducibility are quantified with ideas from information theory, and measured spike sequences in H1 carry more than twice the amount of information they would if they followed the variance-mean relation seen with constant inputs. Thus, models that may accurately account for the neural response to static stimuli can significantly underestimate the reliability of signal transfer under more natural conditions.
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paper_title: A high input impedance low-noise instrumentaion amplifier with JFET input

paper_content:

This paper presents a high input impedance instrumentation amplifier with low-noise low-power operation. JFET input-pair is employed instead of CMOS to significantly reduce the flicker noise. This amplifier features high input impedance (15.3 GΩ∥1.39 pF) by using current feedback technique and JFET input. This amplifier has a mid-band gain of 39.9 dB, and draws 3.65 μA from a 2.8-V supply and exhibits an input-referred noise of 3.81 μVrms integrated from 10 mHz to 100 kHz, corresponding to a noise efficiency factor (NEF) of 3.23.
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paper_title: A low-power 84-dB dynamic-range tunable Gm-C filter for bio-signal acquisition

paper_content:

Abstract —A tunable Gm-C filter is presented for bio-signal acquisition application. It incorporates linear tunable trans-conductors utilizing MOSFETs biased in the triode region. Both the filter architecture and transconductor circuit design are optimized for good tuning, linearity and noise performance with low power consumption. The filter was fabricated in a 0.6 μ m BiCMOS process, occupying 0.17 mm 2 . Measurement results show a tuning range of cut-off frequency from 2.5 kHz to 10 kHz. At 5 kHz cut-off frequency, the filter achieves a dynamic range of 85 dB with 1% THD, and consumes 75.9 μ W from 3.3 V supply. Keywords— Gm-C filter, transconductor, bio-signal acquisition I. I NTRODUCTION Bio-potential signals provide vital information about the patient for disease diagnosis and health monitoring. Fig. 1 shows the block diagram of a typical bio-signal acquisition system. In the analog frontend, the ac-coupled low-noise amplifier (LNA) and the programmable-gain amplifier (PGA) provides gain to reduce noise contribution of subsequent blocks [1] [2]. They are followed by a low-pass filter to eliminate the out-of-band noise. In addition, this filter acts as anti-aliasing filter for the ADC backend. In biomedical applications, it is often desirable to have a filter with tunable cut-off frequency as the bio-signal can range from sub-Hz to a few kHz [3]. In a wearable or implantable system, low power consumption is imperative to extend the battery life and avoid heating of nearby tissue. Furthermore, as the bio-signal amplitude can range from several microvolts to tens of millivolts, high dynamic range (high linearity with low noise) is required to maintain fidelity of the acquired signal. All these requirements place challenges on the filter design. The filter function can be integrated in the LNA by adding load capacitors at the output of the amplifier [4]. This approach is not economic in terms of chip area because the LNA is normally placed in a feedback loop and has large trans-conductance (
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paper_title: Neuromorphic electronic systems

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It is shown that for many problems, particularly those in which the input data are ill-conditioned and the computation can be specified in a relative manner, biological solutions are many orders of magnitude more effective than those using digital methods. This advantage can be attributed principally to the use of elementary physical phenomena as computational primitives, and to the representation of information by the relative values of analog signals rather than by the absolute values of digital signals. This approach requires adaptive techniques to mitigate the effects of component differences. This kind of adaptation leads naturally to systems that learn about their environment. Large-scale adaptive analog systems are more robust to component degradation and failure than are more conventional systems, and they use far less power. For this reason, adaptive analog technology can be expected to utilize the full potential of wafer-scale silicon fabrication. >
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paper_title: An analog floating-gate node for Supervised learning

paper_content:

We present an improved analog floating-gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this floating-gate synapse exhibits this behavior. We examine implications of the weight decay appearing in the correlation learning rule realized in the floating-gate synapse and provide experimental data characterizing the synapse and its performance in one-input and two-input LMS networks. Analog floating-gate synapses will enable larger-scale, on-chip learning networks than previously possible.
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paper_title: Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

paper_content:

Spin-torque-transfer (STT) MRAM is a promising candidate for embedded non-volatile memory in next generation microcontrollers, because of superior endurance, low process costs and logic supply voltage operation. Two major drawbacks of STT-MRAM technology are the small read window because of the low tunnel magnetic resistance (TMR) ratio, and the low read current due to read disturb, which is proportional to the bitline (BL) voltage [1].
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paper_title: Trimming analog circuits using floating-gate analog MOS memory

paper_content:

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100 degrees C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV. >
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paper_title: A floating-gate analog memory with bidirectional sigmoid updates in a standard digital process

paper_content:

A floating-gate current-output analog memory is implemented in a 0.13-μm digital CMOS process. The proposed memory cell achieves random-accessible and bidirectional updates with a sigmoid update rule. A novel writing scheme is proposed to obtain tunneling selectivity without on-chip highvoltage switches or charge pumps, and reduces interconnections and pin count. Parameters of empirical models for floating gate charge modification are extracted from measurements. Measurement and simulation results show that the proposed memory consumes 45 nW of power, has a 7-bit programming resolution, 53.8 dB dynamic range and 86.5 dB writing isolation.
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paper_title: Deweenh ”A CMOS Programmable Analog Memory-Cell Array Using Floating-Gate Circuits

paper_content:

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells.
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paper_title: A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

paper_content:

A 20nm high-κ metal-gate planar CMOS technology is optimized and developed for SoC platform applications that span a wide range of power and performance. This technology is based on a 20nm SoC process featuring high-κ metal gate and strain techniques for core logic transistors with low-power/high-performance and I/O transistors. A high-density and a high-performance embedded memory bit cell each has an area <;0.1μm2. This technology is targeted to high-density low-cost low-power high-performance applications, such as mobile applications with video. Increased threshold-voltage variation of scaled transistors reduces the static noise margin (SNM) and write margin (WM) of the SRAM bit cell. The effect is more predominant for the high-density SRAMs due to small device sizes and large memory capacity requirement for modern SoC design. Therefore, chip performance and minimum operating voltage (VDDmin) are both degraded by the embedded SRAM. Reducing the pass-gate strength or BL capacitance with slow WL rise are effective techniques to improve the SRAM cell stability [1,2]. Underdriving the pass-gate reduces the bit-cell read current but also reduces WM, resulting in SRAM performance degradation. Physically shortening the BL limits the SRAM array configuration. Lowering the SRAM cell power supply improves the WM [3,4], but is less effective than the negative-bitline-based write-assist technique. Compared to conventional techniques, this work presents a partially suppressed wordline (PSWL) scheme for read assist and a bitline-length-tracked negative-bitline-boosting (BT-NBL) scheme for write assist without significantly degrading SRAM performance. With the read/write assist circuitry, the overall VDDmin improvement is over 200mV in a 112Mb SRAM test-chip.
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paper_title: A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

paper_content:

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.
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paper_title: A very high precision 500-nA CMOS floating-gate analog voltage reference

paper_content:

A floating gate with stored charge technique has been used to implement a precision voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate analog voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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paper_title: An Analog Programmable Multidimensional Radial Basis Function Based Classifier

paper_content:

A compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated. The probability distribution of each feature in the templates is modeled by a Gaussian function that is approximately realized by the bell-shaped transfer characteristics of a proposed floating-gate circuit, which we term a floating-gate bump circuit. The maximum likelihood, the mean, and the variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our RBF-based classifier as well as a resultant analog vector quantizer. We show that the classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.
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paper_title: A p-channel MOS synapse transistor with self-convergent memory writes

paper_content:

We have developed a p-channel floating-gate-MOS synapse transistor for silicon-learning applications. The synapse stores a nonvolatile analog weight by means of charge on its floating gate, modifies this weight bidirectionally using electron tunneling and hot-electron injection, and allows simultaneous memory reading and writing. The synapse also learns locally-its weight updates depend only on the applied terminal voltages and on the stored weight. We fabricated an array of synapses that computed both the array output, and the weight updates, in parallel. We also demonstrated a self-convergent write procedure that permitted accurate initialization of the synapse weights. Our pFET synapse is small, and is operated at subthreshold current levels; it will permit the development of dense, low-power, silicon learning systems.
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paper_title: Flash memory cells—An overview

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The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories.
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paper_title: A 19.2 GOPS mixed-signal filter with floating-gate adaptation

paper_content:

We have built a 48-tap, mixed-signal adaptive FIR filter with 8-bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulse-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35-/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6-mA differential output current.
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paper_title: A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology

paper_content:

ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have been used for several megabit test-chips and memory macros [1-3]. This paper presents a MeOx-based 32Gb ReRAM test chip developed in 24nm technology.
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paper_title: A wideband ultra-low-current on-chip ammeter

paper_content:

A high-bandwidth ultra-low-current measurement circuit is presented in this paper. The circuit is capable of measuring an on-chip 75 fA current at a bandwidth up to 1 kHz with a noise floor of 0.235 fA rms /√Hz. A low leakage reset scheme is utilized to improve the precision. Nested auto-zeroing combined with modified correlated double sampling is employed to mitigate the error due to various circuit imperfections. Noise analysis is carried out and “capacitive noise matching” is proposed to minimize the noise floor. The circuit is also capable of digitizing the measured current and streaming the data through a serial interface. The measurement circuit occupies 0.065 mm2 of active silicon area in a 90 nm CMOS process and consumes 147 μW from 2.5 V and 1V supplies.
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paper_title: A voltage-controllable linear MOS transconductor using bias offset technique

paper_content:

A linear large-signal MOS transconductor with the gain adjustable linearly by a voltage is described. A perfect linear transfer characteristic is obtained by two cross-coupled differential transistor pairs operating in saturation pairwise at unequal bias, offering offset-free operation, with both differential or single-ended input and differential output. Single-ended output is achievable by use of a current mirror. The nonlinearity caused by mobility reduction, channel-length modulation, mismatch, etc. is discussed. A test circuit with transconductance of 6.25 mu mho has been built with 3- mu m MOS components, and a linearity error of less than +or-1% was measured for an input voltage range from -4 to 4 V. >
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paper_title: Nano-power tunable bump circuit using wide-input-range pseudo-differential transconductor

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An ultra-low-power tunable bump circuit is presented. It incorporates a novel wide-input-range tunable pseudo-differential transconductor linearised using the drain resistances of saturated transistors. Measurement results show that the transconductor has a 5 V differential input range with <20% of linearity error. The bump circuit demonstrates tunability of the centre, width and height, consuming 18.9 nW power from a 3 V supply, occupying 988 μm2 in a 0.13 μm CMOS process.
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paper_title: CMOS triode transconductor for continuous-time active integrated filters

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A ‘triode transconductor’ fully differential transconductance element for use in continuous-time CMOS integrated filters is proposed. It is based on a common-source pair of triodemode MOS transistors. Preliminary experimental results from breadboarded transconductors and complete filters show good distortion performance. Several practical advantages are claimed over previous approaches.
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paper_title: A very low power 0.7 V subthreshold fully programmable Gaussian function generator

paper_content:

In this paper, an analog current mode implementation of a fully programmable Gaussian function generator (GFG) is presented. The subthreshold current mode circuits enable the design to operate at very low supply voltage and consume very little power. Translinear loop technique is used to generate high precision quadratic current and a single PMOS transistor is used to generate the Gaussian profile. The peak, standard deviation, and mean of the Gaussian profile can be freely programmed. An accurate second order Gaussian profile can be generated by two identical Gaussain circuits with the translinear loop at twice the speed of the cascaded Gaussian circuits. Simulation results show that the circuit consumes only 2 μW at maximum at 0.7 V in 0.18 μm CMOS technology.
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paper_title: 30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS

paper_content:

Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in the human brain to achieve robust automated feature extraction, reducing the dimension of such data. However, the computational complexity of DML systems limits large-scale implementations in standard digital computers. Custom analog or mixed-mode signal processors have been reported to yield much higher energy efficiency than DSP [1-4], presenting the means of overcoming these limitations. However, the use of volatile digital memory in [1-3] precludes their use in intermittently-powered devices, and the required interfacing and internal A/D/A conversions add power and area overhead. Nonvolatile storage is employed in [4], but the lack of learning capability requires task-specific programming before operation, and precludes online adaptation.
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paper_title: An Analog Programmable Multidimensional Radial Basis Function Based Classifier

paper_content:

A compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated. The probability distribution of each feature in the templates is modeled by a Gaussian function that is approximately realized by the bell-shaped transfer characteristics of a proposed floating-gate circuit, which we term a floating-gate bump circuit. The maximum likelihood, the mean, and the variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our RBF-based classifier as well as a resultant analog vector quantizer. We show that the classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.
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paper_title: 'Bump' circuits for computing similarity and dissimilarity of analog voltages

paper_content:

The author describes two small analog circuits that compute generalised measures of the similarity of two voltage inputs. The similarity outputs from the circuits, given as currents, become large when the input voltages are close to each other. One of the circuits, the bump circuit, computes only this similarity output. The other circuit, the bump-anti-bump circuit, computes the similarity output as well as the dissimilarity measure. Each of its dissimilarity outputs becomes large only when the corresponding input is sufficiently larger than the other input. The dissimilarity outputs can be summed together or left separate; when left separate, they resemble generalised rectifier outputs. Test results are presented that illustrate these transfer characteristics. >
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paper_title: An on-chip-trainable Gaussian-kernel analog support vector machine

paper_content:

We propose an analog circuit architecture of the Gaussian-kernel support vector machine having on-chip training capability. Thanks to the hardware-friendly algorithm, the learning function is realized by attaching a small additional circuitry to the SVM classifying hardware. Though the system works as analog circuits, the input and output signals including training results are all available in digital format. Therefore, the learned parameters are easily stored and reused after training sessions. The Gaussian kernel is realized by a new type of circuits utilizing Gilbert multipliers. The proof-of-concept chip was designed and sent to fabrication. Its successful operation was confirmed by transistor level SPICE simulation.
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paper_title: Design of linear CMOS transconductance elements

paper_content:

Some novel circuit techniques for realizing linear CMOS tranconductance elements are proposed. The circuits discussed have superior linearity and input voltage range compared with the conventional source-coupled differential pair. Design tradeoffs are examined and computer simulation results are used to verify theoretical predictions. The results show close agreement between predicted behavior and simulated performance.
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paper_title: Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology

paper_content:

A flexible analog pattern-matching classifier has been developed and its performance is demonstrated in conjunction with a robust image representation algorithm called projected principal-edge distribution (PPED). In the circuit, the functional form of matching is made tunable in terms of the peak position, the peak height and the sharpness of the similarity evaluation by employing the floating-gate MOS technology. The test chip was fabricated in a 0.6-/spl mu/m complimentary metal-oxide semiconductor technology and successfully applied to the recognition of simple handwritten patterns and Arabic numerals using the PPED algorithm for robust image coding. The separation and classification of overlapping patterns have been also experimentally demonstrated.
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paper_title: Analog Versus Digital: Extrapolating from Electronics to Neurobiology

paper_content:

We review the pros and cons of analog and digital computation. We propose that computation that is most efficient in its use of resources is neither analog computation nor digital computation but, rather, a mixture of the two forms. For maximum efficiency, the information and informationprocessing resources of the hybrid form must be distributed over many wires, with an optimal signal-to-noise ratio per wire. Our results suggest that it is likely that the brain computes in a hybrid fashion and that an underappreciated and important reason for the efficiency of the human brain, which consumes only 12 W, is the hybrid and distributed nature of its architecture.
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paper_title: Theano: Deep Learning on GPUs with Python

paper_content:

In this paper, we present Theano 1 , a framework in the Python programming language for defining, optimizing and evaluating expressions involving high-level operations on tensors. Theano offers most of NumPy’s functionality, but adds automatic symbolic differentiation, GPU support, and faster expression evaluation. Theano is a general mathematical tool, but it was developed with the goal of facilitating research in deep learning. The Deep Learning Tutorials 2 introduce recent advances in deep learning, and showcase how Theano
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paper_title: A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition

paper_content:

Object recognition processors have been reported for the applications of autonomic vehicle navigation, smart surveillance and unmanned air vehicles (UAVs) [1-3]. Most of the processors adopt a single classifier rather than multiple classifiers even though multi-classifier systems (MCSs) offer more accurate recognition with higher robustness [4]. In addition, MCSs can incorporate the human vision system (HVS) recognition architecture to reduce computational requirements and enhance recognition accuracy. For example, HMAX models the exact hierarchical architecture of the HVS for improved recognition accuracy [5]. Compared with SIFT, known to have the best recognition accuracy based on local features extracted from the object [6], HMAX can recognize an object based on global features by template matching and a maximum-pooling operation without feature segmentation. In this paper we present a multi-classifier many-core processor combining the HMAX and SIFT approaches on a single chip. Through the combined approach, the system can: 1) pay attention to the target object directly with global context consideration, including complicated background or camouflaging obstacles, 2) utilize the super-resolution algorithm to recognize highly blurred or small size objects, and 3) recognize more than 200 objects in real-time by context-aware feature matching.
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paper_title: A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition

paper_content:

A digital/analog mixed-mode processor is proposed to realize low-power and real-time neuro-fuzzy system for mobile object recognition. It integrates 1024 highly-parallel analog processing element for high dimensional inference operation, and accurate and fast digital accelerator for cascaded learning operation of neuro-fuzzy network. A neuro-fuzzy controller is proposed to manage the mixed-mode operations as a host processor while reducing extra processing delay and power consumption on inter-domain communications. To solve the conventional problems of a large dimensional mixed-mode VLSI system such as throughput degradation due to long channel delay, limited functionality of fixed analog circuits, and mismatches from process variation, the proposed processor adopts 2-stage asynchronous mixed-mode pipeline, flexible channel configuration of each domain, and learning-based calibration technologies respectively. As a result, the processor only consumes 57 mW on average and obtains 12.5 μJ/epoch energy efficiency for on-line learning mixed-mode neuro-fuzzy system with 50 fuzzy rules.
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paper_title: An analog online clustering circuit in 130nm CMOS

paper_content:

An analog clustering circuit is presented. It is capable of inferring the underlying pattern and extracting the statistical parameters from the input vectors, as well as providing measures of similarity based on both mean and variance. A floating-gate analog memory provides non-volatile storage. A current-mode distance computation, a time-domain loser-take-all and a memory adaptation circuit implement efficient and robust learning algorithm. We show that our analog computation element can achieve more than 10x higher energy efficiency than its digital counterpart. An 8-dimension 4-centroid prototype was fabricated in a 130 nm standard CMOS process. Measurement results demonstrate vector classification at 16 kHz, and unsupervised online clustering at 4 kHz with a power consumption of 15 μW.
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paper_title: 30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS

paper_content:

Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in the human brain to achieve robust automated feature extraction, reducing the dimension of such data. However, the computational complexity of DML systems limits large-scale implementations in standard digital computers. Custom analog or mixed-mode signal processors have been reported to yield much higher energy efficiency than DSP [1-4], presenting the means of overcoming these limitations. However, the use of volatile digital memory in [1-3] precludes their use in intermittently-powered devices, and the required interfacing and internal A/D/A conversions add power and area overhead. Nonvolatile storage is employed in [4], but the lack of learning capability requires task-specific programming before operation, and precludes online adaptation.
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paper_title: Deep Machine Learning - A New Frontier in Artificial Intelligence Research [Research Frontier]

paper_content:

This article provides an overview of the mainstream deep learning approaches and research directions proposed over the past decade. It is important to emphasize that each approach has strengths and "weaknesses, depending on the application and context in "which it is being used. Thus, this article presents a summary on the current state of the deep machine learning field and some perspective into how it may evolve. Convolutional Neural Networks (CNNs) and Deep Belief Networks (DBNs) (and their respective variations) are focused on primarily because they are well established in the deep learning field and show great promise for future work.
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paper_title: A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine

paper_content:

A 201.4 GOPS real-time multi-object recognition processor is presented with a three-stage pipelined architecture. Visual perception based multi-object recognition algorithm is applied to give multiple attentions to multiple objects in the input image. For human-like multi-object perception, a neural perception engine is proposed with biologically inspired neural networks and fuzzy logic circuits. In the proposed hardware architecture, three recognition tasks (visual perception, descriptor generation, and object decision) are directly mapped to the neural perception engine, 16 SIMD processors including 128 processing elements, and decision processor, respectively, and executed in the pipeline to maximize throughput of the object recognition. For efficient task pipelining, proposed task/power manager balances the execution times of the three stages based on intelligent workload estimations. In addition, a 118.4 GB/s multi-casting network-on-chip is proposed for communication architecture with incorporating overall 21 IP blocks. For low-power object recognition, workload-aware dynamic power management is performed in chip-level. The 49 mm2 chip is fabricated in a 0.13 ?m 8-metal CMOS process and contains 3.7 M gates and 396 KB on-chip SRAM. It achieves 60 frame/sec multi-object recognition up to 10 different objects for VGA (640 × 480) video input while dissipating 496 mW at 1.2 V. The obtained 8.2 mJ/frame energy efficiency is 3.2 times higher than the state-of-the-art recognition processor.
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paper_title: An Analog Programmable Multidimensional Radial Basis Function Based Classifier

paper_content:

A compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated. The probability distribution of each feature in the templates is modeled by a Gaussian function that is approximately realized by the bell-shaped transfer characteristics of a proposed floating-gate circuit, which we term a floating-gate bump circuit. The maximum likelihood, the mean, and the variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our RBF-based classifier as well as a resultant analog vector quantizer. We show that the classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.
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paper_title: An on-chip-trainable Gaussian-kernel analog support vector machine

paper_content:

We propose an analog circuit architecture of the Gaussian-kernel support vector machine having on-chip training capability. Thanks to the hardware-friendly algorithm, the learning function is realized by attaching a small additional circuitry to the SVM classifying hardware. Though the system works as analog circuits, the input and output signals including training results are all available in digital format. Therefore, the learned parameters are easily stored and reused after training sessions. The Gaussian kernel is realized by a new type of circuits utilizing Gilbert multipliers. The proof-of-concept chip was designed and sent to fabrication. Its successful operation was confirmed by transistor level SPICE simulation.
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paper_title: A micropower learning vector quantizer for parallel analog-to-digital data compression

paper_content:

An analog VLSI architecture for learning vector quantization (LVQ), with on-chip adaptation and dynamic storage of the analog templates, is presented. The architecture extends to fuzzy ART and Kohonen self-organizing maps through digital programming. The analog memory and adaptive element of the LVQ cell comprise 6 MOS transistors and one capacitor, and provide for robust self-refresh of the dynamic analog storage. Total cell size including distance and adaptive computations is 80/spl times/70 lambda in scalable MOSIS technology. Experimental results from a fabricated 16/spl times/16 cell prototype in 2 /spl mu/m CMOS are included.
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paper_title: Sub-Microwatt Analog VLSI Trainable Pattern Classifier

paper_content:

The design and implementation of an analog system-on-chip template-based pattern classifier for biometric signature verification at sub-microwatt power is presented. A programmable array of floating-gate subthreshold MOS translinear circuits matches input features with stored templates and combines the scores into category outputs. Subtractive normalization of the outputs by current-mode feedback produces confidence scores which are integrated for category selection. The classifier implements a support vector machine to select programming values from training samples. A two-step calibration procedure during programming alleviates offset and gain errors in the analog array. A 24-class, 14-input, 720-template classifier trained for speaker identification and fabricated on a 3 mmtimes3 mm chip in 0.5 mum CMOS delivers real-time recognition accuracy on par with floating-point emulation in software. At 40 classifications per second and 840 nW power, the processor attains a computational efficiency of 1.3times1012 multiply-accumulates per second per Watt of power
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paper_title: Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology

paper_content:

A flexible analog pattern-matching classifier has been developed and its performance is demonstrated in conjunction with a robust image representation algorithm called projected principal-edge distribution (PPED). In the circuit, the functional form of matching is made tunable in terms of the peak position, the peak height and the sharpness of the similarity evaluation by employing the floating-gate MOS technology. The test chip was fabricated in a 0.6-/spl mu/m complimentary metal-oxide semiconductor technology and successfully applied to the recognition of simple handwritten patterns and Arabic numerals using the PPED algorithm for robust image coding. The separation and classification of overlapping patterns have been also experimentally demonstrated.
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paper_title: On the Impact of Approximate Computation in an Analog DeSTIN Architecture

paper_content:

Deep machine learning (DML) holds the potential to revolutionize machine learning by automating rich feature extraction, which has become the primary bottleneck of human engineering in pattern recognition systems. However, the heavy computational burden renders DML systems implemented on conventional digital processors impractical for large-scale problems. The highly parallel computations required to implement large-scale deep learning systems are well suited to custom hardware. Analog computation has demonstrated power efficiency advantages of multiple orders of magnitude relative to digital systems while performing nonideal computations. In this paper, we investigate typical error sources introduced by analog computational elements and their impact on system-level performance in DeSTIN-a compositional deep learning architecture. These inaccuracies are evaluated on a pattern classification benchmark, clearly demonstrating the robustness of the underlying algorithm to the errors introduced by analog computational elements. A clear understanding of the impacts of nonideal computations is necessary to fully exploit the efficiency of analog circuits.
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Title: Recent Development in Analog Computation - A Brief Overview

Section 1: INTRODUCTION
Description 1: Provide an overview of the importance of energy-efficient computational elements in various applications, highlighting the efficiency gap between the human brain and digital processors, and introduce the potential of analog computation.

Section 2: ANALOG MEMORY
Description 2: Discuss the indispensable role of memory in computation systems, compare digital and analog memory designs, and elaborate on recently proposed designs of Floating gate (FG) memories for analog non-volatile storage.

Section 3: ANALOG NON-LINEAR OPERATOR
Description 3: Explain how analog computation can realize non-linear functions directly, focusing on the implementation and advantages of radial-basis functions and bump circuits in analog systems.

Section 4: ANALOG ONLINE CLUSTERING ENGINE
Description 4: Describe the resource-intensive nature of the k-means clustering algorithm in digital domains and discuss how analog computation offers improvements in energy efficiency, with examples of previous works and novel implementations.

Section 5: CONCLUSIONS
Description 5: Summarize the key points discussed in the paper, emphasizing the potential of analog computation for energy efficiency improvements and the importance of innovative design considerations at the circuit, algorithm, and architecture levels.