Survey on Coarse Grained Reconfigurable Architectures
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paper_title: Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture

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This paper presents the hardware structure and application of a coarse-grained dynamically reconfigurable hardware architecture dedicated to wireless communication systems. The application tailored architecture, called DReAM (D_ynamically R_econfigurable Hardware A_rchitecture for M_obile Communication Systems), is a research project at the Darmstadt University of Technology. It covers the complete design process from analyzing the requirements for the dedicated application field, the specification and VHDL implementation of the architecture, up to the physical layout for the final chip. In the following we provide an overview of the major design stages, starting with a motivation for choosing the concept of distributed arithmetic in reconfigurable computing.
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paper_title: A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing

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The evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. The system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper presents first the major challenges in realizing flexible microelectronic system solutions for digital baseband signal processing in future mobile communication applications. Based thereupon, the architecture design of flexible system-on-a-chip solutions is discussed. The focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.
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paper_title: Reconfigurable computing: a new business model-and its impact on SoC design

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Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA application is RAM-based, but by structural programming (also called "(re)configuration") instead of procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC design. Now also accelerator definition may be-at least partly-conveyed from vendor site to customer site. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware syntheses method. From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging future competitor to FPGAs. Supporting roughly single bit wide configurable logic blocks (CLBs) the mapping tools are mainly based on gate level methods-similar to CAD for hardware logic. In contrast to this fine-grained arrays of coarse-grained reconfigurable datapath units (rDPUs) with drastically reduced reconfigurability overhead: to directly configure high level parallelism. But the "von Neumann" paradigm does not support soft datapaths because "instruction fetch" is not done at run time, and, since most reconfigurable computing arrays do not run parallel processes, but multiple pipe networks instead.
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paper_title: Architecture generation of customized reconfigurable hardware

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Reconfigurable hardware is ideal for use in systems-on-a-chip (SoCs), achieving hardware speeds but also flexibility not available with more traditional custom circuitry. Traditional FPGA structures can be used in an SoC, but they suffer from significant overhead due to their generic nature. Alternatively, for cases when the application domain of the SoC is known, the reconfigurable hardware can be optimized for that domain. The Totem Project focuses on the automatic creation of customized reconfigurable architectures, including high-level design, VLSI layout, and associated custom place and route tools. ::: This thesis focuses on the high-level design phase, or “Architecture Generation”. Two distinct categories of reconfigurable architectures can be created: highly optimized near-ASIC designs with a very low degree of reconfigurability, and flexible architectures with a one-dimensional segmented routing structure. Each of these design methods shows significant improvements through tailoring the architectures to the given application area. The cASIC designs are on average up to 12.3x smaller than an FPGA solution with embedded multipliers and 2.2x smaller than a standard cell implementation. The more flexible architectures, able to support a wider variety of circuits, are on average up to 5.5x smaller than the FPGA solution, and close in area to standard cells.
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paper_title: MorphoSys: a reconfigurable architecture for multimedia applications

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We describe the MorphoSys reconfigurable system, which combines a reconfigurable array of processor cells with a RISC processor core and a high bandwidth memory interface unit. We introduce the array architecture, its configuration memory, inter-connection network, role of the control processor and related components. Architecture implementation is described in brief and the efficacy of MorphoSys is demonstrated through simulation of video compression (MPEG-2) and target-recognition applications. Comparison with other implementations illustrates that MorphoSys achieves higher performance by up to 10X.
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paper_title: A reconfigurable arithmetic array for multimedia applications

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In this paper we describe a reconfigurable architecture optimised for media processing, and based on 4-bit ALUs and interconnect.
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paper_title: Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures

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The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future broadband mobile communication systems. Here, new and flexible microelectronic architectures are required solving various problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper sketches first the major motivation for developing flexible microelectronic System-onChip (SoC) solutions for the digital baseband processing in future mobile radio devices. The paper introduces a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. The focus of this contribution is the efficient communication and dynamic reconfiguration realization for such reconfigurable array architectures, which is crucial for their overall performance and flexibility.
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paper_title: Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures

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Reconfigurable ALU Array (RAA) architectures – representing a popular class of Coarse-grained Reconfigurable Architectures – are gaining in popularity especially for media applications due to their flexibility, regularity, and efficiency. In such architectures, memory is critical not only for configuration data but also for the heavy data traffic required by the application. In this paper, we offer a scheme for system designers to quickly estimate the performance of media applications on RAA architectures. Our experimental results demonstrate the flexibility of our memory architecture evaluation scheme as well as the varying effects of the memory architectures on the application performance.
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paper_title: A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

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We have designed a coarse-grained, dynamically reconfigurable architecture, specifically for implementing the wireless MAC layer in consumer hand-held devices. The dynamically reconfigurable MAC Processor is a SoC architecture that uses a reconfigurable hardware co-processor to delegate critical tasks. The co-processor can reconfigure packet-by-packet, handling upto 3 data streams of different protocols concurrently. We present results of simulations involving transmission and reception of packets, showing that the platform concurrently handles three protocol streams, reconfigures dynamically, yet meets and exceeds the protocol timing constraints, all at a moderate frequency. Thus we show that this architecture is capable of replacing up to three MAC processors in a wireless device. Its heterogeneous and coarse-grained functional units, requirements of limited connectivity between these units, and the idle time of hardware resources promise a very modest power-consumption, suitable for mobile devices.
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paper_title: Research Article SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications

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This paper presents SmartCell, a novel coarse-grained reconfigurable architecture, which tiles a large number of processor elements with reconfigurable interconnection fabrics on a single chip. SmartCell is able to provide high performance and energy efficient processing for stream-based applications. It can be configured to operate in various modes, such as SIMD, MIMD, and systolic array. This paper describes the SmartCell architecture design, including processing element, reconfigurable interconnection fabrics, instruction and control process, and configuration scheme. The SmartCell prototype with 64 PEs is implemented using 0.13 µm CMOS standard cell technology. The core area is about 8.5mm2, and the power consumption is about 1.6mW/MHz. The performance is evaluated through a set of benchmark applications, and then compared with FPGA, ASIC, and two well-known reconfigurable architectures including RaPiD and Montium. The results show that the SmartCell can bridge the performance and flexibility gap between ASIC and FPGA. It is also about 8% and 69% more energy efficient than Montium and RaPiD systems for evaluated benchmarks. Meanwhile, SmartCell can achieve 4 and 2 times more throughput gains when comparing with Montium and RaPiD, respectively. It is concluded that SmartCell system is a promising reconfigurable and energy efficient architecture for stream processing.
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paper_title: FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability

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This paper demonstrates a chip implementation of coarse-grained reconfigurable architecture named FloRA. Two-dimensional array of integer processing elements in the FloRA is configured in run-time to perform integer functions as well as floating-point functions. FloRA is implemented in Dongbu HiTek 130nm process and evaluate by running applications including physics engine and jpeg decoder.
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paper_title: FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability

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This paper demonstrates a chip implementation of coarse-grained reconfigurable architecture named FloRA. Two-dimensional array of integer processing elements in the FloRA is configured in run-time to perform integer functions as well as floating-point functions. FloRA is implemented in Dongbu HiTek 130nm process and evaluate by running applications including physics engine and jpeg decoder.
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paper_title: Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture

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With the increasing requirements for more flexibility and higher performance in embedded systems design, reconfigurable computing has become more popular. There have been many coarse-grained reconfigurable architectures proposed and/or commercialized. But most of the existing architectures cannot be used for applications that require floating-point operations, since they have only integer units. In this paper, we present how we can perform various floating-point operations on a coarse-grained reconfigurable array of integer processing elements. We demonstrate the effectiveness of our approach through the implementation of various floating-point operations for 3D graphics and their performance analysis.
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Title: Survey on Coarse Grained Reconfigurable Architectures

Section 1: INTRODUCTION
Description 1: This section introduces the background and motivation for developing coarse-grained reconfigurable architectures, highlighting the advantages over fine-grained FPGAs and ASICs.

Section 2: COARSE GRAINED RECONFIGURABLE ARCHITECTURES
Description 2: This section describes the basic architecture of coarse-grained reconfigurable architectures, including data-paths, processing elements, and interconnection networks.

Section 3: CGRA DEVELOPMENT
Description 3: This section outlines the development history and various approaches of different coarse-grained reconfigurable architectures, providing an overview of key architectures in the field.

Section 4: The Reconfigurable Pipelined Datapath (RaPiD) Architecture
Description 4: This sub-section discusses the RaPiD architecture, its components, and its target applications, specifically DSP tasks.

Section 5: MorphoSys Architecture
Description 5: This sub-section explores the MorphoSys architecture, focused on multimedia applications, and its combination of coarse and fine grain reconfiguration techniques.

Section 6: The CHESS Architecture
Description 6: This sub-section examines the CHESS architecture, tailored for multimedia and motion estimation applications, and discusses its computation components and routing strategies.

Section 7: Dynamically Reconfigurable Architecture for Mobile Systems (DReAM)
Description 7: This sub-section details the DReAM architecture, designed for mobile devices, and its capabilities in supporting future generations of wireless communication systems.

Section 8: Dynamically Reconfigurable ALU Array (DRAA)
Description 8: This sub-section introduces the DRAA, a generic architecture template with a focus on efficient memory interface for media applications.

Section 9: ADRES (Architecture for Dynamically Reconfigurable Embedded System)
Description 9: This sub-section describes the ADRES architecture, highlighting its VLIW processor and array of configurable processing cells for embedded applications.

Section 10: MORA Architecture
Description 10: This sub-section provides an overview of the MORA architecture, its scalable reconfigurable cells, and its application in multimedia.

Section 11: Dynamically Reconfigurable MAC Processor (DRMP)
Description 11: This sub-section covers the DRMP, designed for wireless MAC layer implementation in hand-held devices, and its power-efficient functional units.

Section 12: PACT XPP-III
Description 12: This sub-section focuses on the XPP-III architecture, its heterogeneous processor types, and its application in stream-based processing.

Section 13: SYSCORE Architecture
Description 13: This sub-section highlights the SYSCORE architecture, aimed at biosignal processing with low power consumption features.

Section 14: SmartCell
Description 14: This sub-section discusses the SmartCell architecture targeted for high data throughput and computationally intensive applications.

Section 15: Floating-point Reconfigurable Array (FloRA)
Description 15: This sub-section outlines the FloRA architecture, capable of performing both integer and floating-point operations, optimized for mobile applications.

Section 16: CONCLUSION
Description 16: This section summarizes the survey, emphasizing the performance and flexibility of coarse-grained reconfigurable architectures in SoC design.