Overview and perspectives of depleted CMOS sensors for high radiation environments
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paper_title: ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

paper_content:

A new 10 m2 inner tracking system based on seven concentric layers of Monolithic Active Pixel Sensors will be installed in the ALICE experiment during the second long shutdown of LHC in 2019–2020. The monolithic pixel sensors will be fabricated in the 180 nm CMOS Imaging Sensor process of TowerJazz. The ALPIDE design takes full advantage of a particular process feature, the deep p-well, which allows for full CMOS circuitry within the pixel matrix, while at the same time retaining the full charge collection efficiency. Together with the small feature size and the availability of six metal layers, this allowed a continuously active low-power front-end to be placed into each pixel and an in-matrix sparsification circuit to be used that sends only the addresses of hit pixels to the periphery. This approach led to a power consumption of less than 40mWcm−2, a spatial resolution of around 5 μm, a peaking time of around 2 μs, while being radiation hard to some 10131MeVneq/cm2, fulfilling or exceeding the ALICE requirements. ::: ::: Over the last years of R & D, several prototype circuits have been used to verify radiation hardness, and to optimize pixel geometry and in-pixel front-end circuitry. The positive results led to a submission of full-scale (3 cm×1.5 cm) sensor prototypes in 2014. They are being characterized in a comprehensive campaign that also involves several irradiation and beam tests. A summary of the results obtained and prospects towards the final sensor to instrument the ALICE Inner Tracking System are given.
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paper_title: A monolithic active pixel sensor for charged particle tracking and imaging using standard VLSI CMOS technology

paper_content:

Abstract A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode, which is readily available in a CMOS technology. The diode has a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. Semiconductor device simulation, using either ToSCA based or 3-D ISE-TCAD software packages shows that the charge collection is efficient, reasonably fast (order of 100 ns), and the charge spreading limited to a few pixels only. A first prototype has been designed, fabricated and tested. It is made of four arrays each containing 64×64 pixels, with a readout pitch of 20 μm in both directions. The device is fabricated using standard submicron 0.6 μm CMOS process, which features twin-tub implanted in a p-type epitaxial layer, a characteristic common to many modern CMOS VLSI processes. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/ c pions) fully demonstrate the predicted performances, with the individual pixel noise (ENC) below 20 electrons and the Signal-to-Noise ratio for both 5.9 keV X-rays and Minimum Ionising Particles (MIP) of the order of 30. This novel device opens new perspectives in high-precision vertex detectors in Particle Physics experiments, as well as in other application, like low-energy beta particle imaging, visible light single photon imaging (using the Hybrid Photon Detector approach) and high-precision slow neutron imaging.
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paper_title: A MAPS based vertex detector for the STAR experiment at RHIC

paper_content:

Abstract The STAR experiment at RHIC is in the process of upgrading the inner detector region of the experiment to improve the vertex resolution. We describe the current design of a MAPS based vertex detector, which is the innermost and highest resolution detector of the set of three planned upgrade detectors. This detector will enable the identification of decay vertices displaced from the interaction vertex by 100–150 μm and extend the capabilities of the STAR detector in the heavy flavor domain. We present selected detector design characteristics and prototyping results, which help to validate the design in preparation for the construction of the detector.
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paper_title: Radiation-induced edge effects in deep submicron CMOS transistors

paper_content:

The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).
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paper_title: A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology ☆

paper_content:

A new concept for monolithic pixel detector with 100% fill-factor is presented. The detection is based on the charge collection in the depleted zone of the reverse biased diode. Complex pixel electronics, including charge sensitive amplifier, amplitude discriminator and digital storage element is placed completely inside the diode cathode (N-well). A test chip that comprises a small pixel matrix and test structures has been fabricated in a 0.35μm high-voltage CMOS process and successfully tested. The results of the electrical tests and measurements with X-ray and beta radioactive sources are presented.
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paper_title: Simulation of charge multiplication and trap-assisted tunneling in irradiated planar pixel sensors

paper_content:

We present a model for the TCAD simulation of charge multiplication and trap-to-band tunneling to explain the discrepancies between the experimentally observed charge collection in highly irradiated planar pixel sensors and the predictions made using the Hamburg model. DC and transient TCAD simulations of one dimensional n-in-p diodes were performed and reproduce well the observed behavior of diode irradiated to fluences of the order of 1015–16 n eq cm−2. The results of the simulations show that impact ionization and de-trapping due to tunneling qualitatively explain the behavior of irradiated sensors observed experimentally.
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paper_title: Hybrid Pixel Particle-Detector Without Bump Interconnection

paper_content:

A hybrid pixel particle-detector which does not require bump-interconnection is presented. The sensor signals are transmitted from the sensor to the readout chip using capacitive (AC) coupling. In order to facilitate the signal transmission, simple preamplifiers are implemented in the sensor pixels. The sensor chip with 100% fill-factor and in-pixel amplification is implemented in a standard high-voltage CMOS technology. Depleted high-voltage n-well/p-substrate diodes are used as sensors. CMOS charge-sensitive amplifiers are placed inside the sensor-collecting electrodes (n-wells) using twin-wells. The outputs of the preamplifiers are connected to transmitter electrodes implemented in the top metal-layer of the sensor chip. The inputs of the receivers in the readout chip are also connected to electrodes in the top metal-layer. When the readout chip is precisely flipped and glued onto the sensor chip, the sensor- and receiver electrodes form capacitors that allow AC signal transmission. The first test results obtained with a small test-matrix containing 14 times 14 pixels of 78 times 60 mum2-size are presented. Noise, threshold dispersion and radioactive source spectra are measured.
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paper_title: A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology ☆

paper_content:

A new concept for monolithic pixel detector with 100% fill-factor is presented. The detection is based on the charge collection in the depleted zone of the reverse biased diode. Complex pixel electronics, including charge sensitive amplifier, amplitude discriminator and digital storage element is placed completely inside the diode cathode (N-well). A test chip that comprises a small pixel matrix and test structures has been fabricated in a 0.35μm high-voltage CMOS process and successfully tested. The results of the electrical tests and measurements with X-ray and beta radioactive sources are presented.
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paper_title: Research Proposal for an Experiment to Search for the Decay {\mu} ->eee

paper_content:

We propose an experiment (Mu3e) to search for the lepton flavour violating decay mu+ -> e+e-e+. We aim for an ultimate sensitivity of one in 10^16 mu-decays, four orders of magnitude better than previous searches. This sensitivity is made possible by exploiting modern silicon pixel detectors providing high spatial resolution and hodoscopes using scintillating fibres and tiles providing precise timing information at high particle rates.
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paper_title: Status of HVCMOS Developments for ATLAS

paper_content:

This paper describes the status of the developments made by ATLAS HVCMOS and HVMAPS collaborations. We have proposed two HVCMOS sensor concepts for ATLAS pixels—the capacitive coupled pixel detector (CCPD) and the monolithic detector. The sensors have been implemented in three semiconductor processes AMS H18, AMS H35 and LFoundry LFA15. Efficiency of 99.7% after neutron irradiation to 1015 neq/cm2W has been measured with the small area CCPD prototype in AMS H18 technology. About 84% of the particles are detected with a time resolution better than 25 ns. The sensor was implemented on a low resistivity substrate. The large area demonstrator sensor in AMS H35 process has been designed, produced and successfully tested. The sensor has been produced on different high resistivity substrates ranging from 80 Ωcm to more than 1 kΩ. Monolithic- and hybrid readout are both possible. In August 2016, six different monolithic pixel matrices for ATLAS with a total area of 1 cm2 have been submitted in LFoundry LFA15 process. The matrices implement column drain and triggered readout as well as waveform sampling capability on pixel level. Design details will be presented.
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paper_title: Development of depleted monolithic pixel sensors in 150 nm CMOS technology for the ATLAS Inner Tracker upgrade

paper_content:

This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150 nm CMOS process. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade for the High Luminosity Large Hadron Collider (HL-LHC). Implementing such a device in the detector module will result in a lower production cost and lower material budget compared to the presently used hybrid designs. In this paper the chip architecture will be described followed by the simulation and measurement results.
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paper_title: The FE-I4 pixel readout integrated circuit

paper_content:

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.
---
paper_title: ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

paper_content:

A new 10 m2 inner tracking system based on seven concentric layers of Monolithic Active Pixel Sensors will be installed in the ALICE experiment during the second long shutdown of LHC in 2019–2020. The monolithic pixel sensors will be fabricated in the 180 nm CMOS Imaging Sensor process of TowerJazz. The ALPIDE design takes full advantage of a particular process feature, the deep p-well, which allows for full CMOS circuitry within the pixel matrix, while at the same time retaining the full charge collection efficiency. Together with the small feature size and the availability of six metal layers, this allowed a continuously active low-power front-end to be placed into each pixel and an in-matrix sparsification circuit to be used that sends only the addresses of hit pixels to the periphery. This approach led to a power consumption of less than 40mWcm−2, a spatial resolution of around 5 μm, a peaking time of around 2 μs, while being radiation hard to some 10131MeVneq/cm2, fulfilling or exceeding the ALICE requirements. ::: ::: Over the last years of R & D, several prototype circuits have been used to verify radiation hardness, and to optimize pixel geometry and in-pixel front-end circuitry. The positive results led to a submission of full-scale (3 cm×1.5 cm) sensor prototypes in 2014. They are being characterized in a comprehensive campaign that also involves several irradiation and beam tests. A summary of the results obtained and prospects towards the final sensor to instrument the ALICE Inner Tracking System are given.
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paper_title: A novel source–drain follower for monolithic active pixel sensors

paper_content:

Abstract Monolithic active pixel sensors (MAPS) receive interest in tracking applications in high energy physics as they integrate sensor and readout electronics in one silicon die with potential for lower material budget and cost, and better performance. Source followers (SFs) are widely used for MAPS readout: they increase charge conversion gain 1/ C eff or decrease the effective sensing node capacitance C eff because the follower action compensates part of the input capacitance. Charge conversion gain is critical for analog power consumption and therefore for material budget in tracking applications, and also has direct system impact. This paper presents a novel source–drain follower (SDF), where both source and drain follow the gate potential improving charge conversion gain. For the inner tracking system (ITS) upgrade of the ALICE experiment at CERN, low material budget is a primary requirement. The SDF circuit was studied as part of the effort to optimize the effective capacitance of the sensing node. The collection electrode, input transistor and routing metal all contribute to C eff . Reverse sensor bias reduces the collection electrode capacitance. The novel SDF circuit eliminates the contribution of the input transistor to C eff , reduces the routing contribution if additional shielding is introduced, provides a way to estimate the capacitance of the sensor itself, and has a voltage gain closer to unity than the standard SF. The SDF circuit has a somewhat larger area with a somewhat smaller bandwidth, but this is acceptable in most cases. A test chip, manufactured in a 180 nm CMOS image sensor process, implements small prototype pixel matrices in different flavors to compare the standard SF to the novel SF and to the novel SF with additional shielding. The effective sensing node capacitance was measured using a 55 Fe source. Increasing reverse substrate bias from −1 V to −6 V reduces C eff by 38% and the equivalent noise charge (ENC) by 22% for the standard SF. The SDF provides a further 9% improvement for C eff and 25% for ENC. The SDF circuit with additional shielding provides 18% improvement for C eff , and combined with −6 V reverse bias yields almost a factor 2.
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paper_title: DMAPS: a fully depleted monolithic active pixel sensor - analog performance characterization

paper_content:

Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s based on silicon substrates with a thin epitaxial layer (thickness of 10-15 $\mu$m) in which charge is collected on an electrode, albeit by disordered and slow diffusion rather than by drift in a directed electric field. As a consequence, the signal is small ($\approx$ 1000 e$^-$) and the radiation tolerance is much below the LHC requirements by factors of 100 to 1000. In this paper we present the development of a fully Depleted Monolithic Active Pixel Sensors (DMAPS) based on a high resistivity substrate allowing the creation of a fully depleted detection volume. This concept overcomes the inherent limitations of charge collection by diffusion in the standard MAPS designs. We present results from a test chip EPCB01 designed in a commercial 150 nm CMOS technology. The technology provides a thin (50 $\mu$m) high resistivity n-type silicon substrate as well as an additional deep p-well which allows to integrate full CMOS circuitry inside the pixel. Different matrix types with several variants of collection electrodes have been implemented. Measurements of the analog performance of this first implementation of DMAPS pixels will be presented.
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paper_title: A Monolithic active pixel sensor for ionizing radiation using a 180nm HV-SOI process

paper_content:

An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry witch mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.
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paper_title: Radiation hardness of a 180 nm SOI monolithic active pixel sensor

paper_content:

Abstract The use of Silicon-on-Insulator (SOI) technology as a particle detector in a high radiation environment is, at present, limited mostly by radiation effects on the transistor characteristics, back gate effect, and mutual coupling between the Buried Oxide (BOX) and the sensor. We have fabricated and tested a new 0.18 μ m SOI CMOS monolithic pixel sensor using the XFAB process. In contrast to the most commonly used SOI technologies, this particular technology uses partially depleted SOI transistors, offering a double well structure, which shields the thin gate oxide transistors from the BOX. In addition, an increased distance between transistors and a thicker BOX than has been previously used offers promising solutions to the performance limitations mentioned above. The process further allows the use of high voltages (up to 200 V), which are used to partially deplete the substrate. Thus, the newly fabricated device in the XFAB process is especially interesting for applications in extremely high radiation environments, such as LHC experiments. A four stage validation programme of the technology and the fabricated monolithic pixel sensor has been performed and its results are shown in this paper. The first targets radiation hardness of the transistor characteristics up to 700 Mrad, the second investigates the existence of the back gate effect, the third one targets the coupling between the BOX and the sensor, and the fourth investigates the characterization of charge collection in the sensor diode below the BOX.
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paper_title: Radiation Imaging Detectors Using Soi Technology

paper_content:

Silicon-on-Insulator (SOI) technology is widely used in high-performance and low-power semiconductor devices. The SOI wafers have two layers of active silicon (Si), and normally the bottom Si layer is a mere physical structure. The idea of making intelligent pixel detectors by using the bottom Si layer as sensors for X-ray, infrared light, high-energy particles, neutrons, etc. emerged from very early days of the SOI technology. However, there have been several difficult issues with fabricating such detectors and they have not become very popular until recently. This book offers a comprehensive overview of the basic concepts and research issues of SOI radiation image detectors. It introduces basic issues to implement the SOI detector and presents how to solve these issues. It also reveals fundamental techniques, improvement of radiation tolerance, applications, and examples of the detectors. Since the SOI detector has both a thick sensing region and CMOS transistors in a monolithic die, many ideas have emerged to utilize this technology. This book is a good introduction for people who want to develop or use SOI detectors.
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paper_title: The FE-I4 pixel readout integrated circuit

paper_content:

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.
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Title: Overview and perspectives of depleted CMOS sensors for high radiation environments

Section 1: Introduction
Description 1: Provide an overview of the role of pixel detectors in particle physics, the current state of hybrid pixel detectors, and the motivation towards developing depleted CMOS sensors.

Section 2: Charge collection in the presence of trapping
Description 2: Discuss the impact of radiation on charge collection, highlighting the main effects of surface damage and bulk damage on sensor performance.

Section 3: Design approaches
Description 3: Compare and contrast different sensor design concepts for n-on-p CMOS sensor designs, highlighting the benefits and challenges of each approach.

Section 4: Example Implementations
Description 4: Summarize various prototype implementations of radiation-tolerant monolithic sensors developed in recent years, focusing on their design, performance, and radiation tolerance.

Section 5: Logic inside the collecting well (large fill-factor)
Description 5: Review the development of devices with logic inside the collecting well, providing specific examples and their performance metrics.

Section 6: Logic outside collecting well (small fill-factor)
Description 6: Discuss devices with logic located outside the collecting node, the technologies used, and their application in high radiation environments.

Section 7: HV-SOI
Description 7: Describe the HV-SOI technology and its potential in creating radiation-tolerant sensors, including initial prototypes and their performance.

Section 8: Conclusions
Description 8: Summarize the findings, emphasizing the advancements of monolithic sensors towards achieving high radiation tolerance and their potential to replace hybrid pixel devices in specific applications.