Sub 1 V CMOS bandgap reference design techniques: a survey
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paper_title: Predicting and designing for the impact of process variations and mismatch on the trim range and yield of bandgap references

paper_content:

Process tolerance and device mismatch produce significant random variations in bandgap voltage reference circuits. These variations lead to errors in the reference voltage and significantly impact manufacturing cost by increasing trimming requirements and decreasing yield. Current-mirror mismatch, followed by V/sub BE/ spread, package shift, and resistor mismatch are the dominant sources of random error in bandgap reference circuits. A folded-cascode topology, often used in low voltage applications, can be optimized to effectively alleviate the effects of a mismatch in the mirroring devices. By decreasing the ratio of the current in the cascode to that of the bandgap core circuit and ascertaining the best-matched devices for implementing current-mirrors and current sources, these mismatches can be significantly reduced.
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paper_title: Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference

paper_content:

The design considerations of CMOS bandgap voltage references, focusing on low-voltage and low-temperature-coefficient methodologies, are discussed in this paper. Some recently reported circuits of bandgap voltage references are included and analyzed. Moreover, a CMOS voltage reference is also addressed.
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paper_title: Predicting the effects of error sources in bandgap reference circuits and evaluating their design implications

paper_content:

Errors that arise from tolerance variations and mismatches between devices severely degrade the performance of bandgap reference circuits, which are essential building blocks to all high-performance systems. All these error sources have been analyzed (and verified through SPICE) and their design implications have been addressed. It has been found that resistor tolerance aid current-mirror mismatch are the dominant sources of error in bandgap reference-type circuits. Further, it has been found that resistor mismatch, transistor mismatch, and current-mirror mismatch errors have a PTAT variation, while resistor tolerance error has a CTAT dependence - both PTAT and CTAT errors are eliminated by trimming the PTAT terminating resistor in a bandgap circuit, only at room temperature. Resistor TC errors cannot be trimmed out and hence resistors must therefore be carefully selected and designed.
---
paper_title: Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference

paper_content:

The design considerations of CMOS bandgap voltage references, focusing on low-voltage and low-temperature-coefficient methodologies, are discussed in this paper. Some recently reported circuits of bandgap voltage references are included and analyzed. Moreover, a CMOS voltage reference is also addressed.
---
paper_title: Predicting the effects of error sources in bandgap reference circuits and evaluating their design implications

paper_content:

Errors that arise from tolerance variations and mismatches between devices severely degrade the performance of bandgap reference circuits, which are essential building blocks to all high-performance systems. All these error sources have been analyzed (and verified through SPICE) and their design implications have been addressed. It has been found that resistor tolerance aid current-mirror mismatch are the dominant sources of error in bandgap reference-type circuits. Further, it has been found that resistor mismatch, transistor mismatch, and current-mirror mismatch errors have a PTAT variation, while resistor tolerance error has a CTAT dependence - both PTAT and CTAT errors are eliminated by trimming the PTAT terminating resistor in a bandgap circuit, only at room temperature. Resistor TC errors cannot be trimmed out and hence resistors must therefore be carefully selected and designed.
---
paper_title: Predicting and designing for the impact of process variations and mismatch on the trim range and yield of bandgap references

paper_content:

Process tolerance and device mismatch produce significant random variations in bandgap voltage reference circuits. These variations lead to errors in the reference voltage and significantly impact manufacturing cost by increasing trimming requirements and decreasing yield. Current-mirror mismatch, followed by V/sub BE/ spread, package shift, and resistor mismatch are the dominant sources of random error in bandgap reference circuits. A folded-cascode topology, often used in low voltage applications, can be optimized to effectively alleviate the effects of a mismatch in the mirroring devices. By decreasing the ratio of the current in the cascode to that of the bandgap core circuit and ascertaining the best-matched devices for implementing current-mirrors and current sources, these mismatches can be significantly reduced.
---
paper_title: Predicting the effects of error sources in bandgap reference circuits and evaluating their design implications

paper_content:

Errors that arise from tolerance variations and mismatches between devices severely degrade the performance of bandgap reference circuits, which are essential building blocks to all high-performance systems. All these error sources have been analyzed (and verified through SPICE) and their design implications have been addressed. It has been found that resistor tolerance aid current-mirror mismatch are the dominant sources of error in bandgap reference-type circuits. Further, it has been found that resistor mismatch, transistor mismatch, and current-mirror mismatch errors have a PTAT variation, while resistor tolerance error has a CTAT dependence - both PTAT and CTAT errors are eliminated by trimming the PTAT terminating resistor in a bandgap circuit, only at room temperature. Resistor TC errors cannot be trimmed out and hence resistors must therefore be carefully selected and designed.
---
paper_title: CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

paper_content:

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.
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paper_title: Reliable Circuit Techniques for Low-Voltage Analog Design in Deep Submicron Standard CMOS: A Tutorial

paper_content:

We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-of-the-art circuit topologies and techniques (input level shifting, bulk and current driven, DTMOS), used to build main analog modules (operational amplifier, analog CMOS switches) are covered with the implementation of MOS capacitors.
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paper_title: Low-power bandgap references featuring DTMOSTs

paper_content:

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 /spl mu/W; the die area is 0.063 mm/sup 2/ in a standard digital 0.35-/spl mu/m CMOS process. The second bandgap reference circuit aims at high accuracy operation (/spl sigma/=0.3%) without trimming. It consumes approximately 5 /spl mu/W from a 1.8-V supply voltage and occupies 0.06 mm/sup 2/ in a standard 0.35-/spl mu/m CMOS process.
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paper_title: A CMOS subbandgap reference circuit with 1-v power supply voltage

paper_content:

A CMOS subbandgap reference circuit with 1-V supply voltage is described. To obtain subbandgap reference voltages with a 1-V supply voltage, threshold voltage reduction and subthreshold operation techniques are used. Large /spl Delta/V/sub BE/ (100 mV) as well as a 90-dB operational amplifier are used to circumvent the amplifier offset. A power-on-reset (POR) circuit is used as startup. This circuit has been implemented using a standard 0.5-/spl mu/m CMOS process, and its size is 940 /spl mu/m/spl times/1160/spl mu/m. The temperature coefficient is 17 ppm from -40/spl deg/C to 125/spl deg/C after resistor trimming and the minimum power supply voltage is 0.95 V. The measured total current consumption is below 10 /spl mu/A and the measured output voltage is 0.631 V at room temperature.
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paper_title: Curvature compensated BiCMOS bandgap with 1 V supply voltage

paper_content:

In this paper we present a bandgap circuit capable of generating a reference voltage of 0.54 V. The circuit, implemented in a submicron BiCMOS technology, operates with a supply voltage of 1 V. In the bandgap circuit proposed we use a non-conventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1 V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 5 ppm / K of accuracy without requiring additional operational amplifiers or complex circuits.
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paper_title: A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device

paper_content:

A new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-μm CMOS process, where the occupied silicon area is only 177 μm x 106 μm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/°C from-10°C to 120°C without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10kHz.
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paper_title: A low-voltage low-power voltage reference based on subthreshold MOSFETs

paper_content:

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.
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paper_title: Design of low-voltage bandgap reference using transimpedance amplifier

paper_content:

The minimum supply voltage for implementing a typical bandgap reference is usually over 1.8 V. This minimum is mainly due to the limited input common-mode range of the opamp used in the bandgap reference. In this work, a low-voltage bandgap reference using a transimpedance amplifier that does not have this limitation is proposed and some of the design considerations for the proposed technique are briefly discussed. Based on this technique, a 1.2-V bandgap reference was implemented in a 1.2-/spl mu/m CMOS process (V/sub TN//spl ap/0.53 V and V/sub TP//spl ap/-0.91 V) with bipolar option. The variations of the output voltage over temperature (0/spl deg/C/spl les/T/spl les/100/spl deg/C) were measured to be less than /spl plusmn/1%.
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paper_title: A low voltage low 1/f noise CMOS bandgap reference

paper_content:

For a low voltage bandgap reference design, there is a tradeoff between the supply voltage and the performance of the bandgap reference in terms of untrimmed accuracy and 1/f noise performance. In this paper, the application of chopper stabilizing technique is proposed to address this tradeoff. Over five times of improvement in untrimmed accuracy and 1/f noise performance were demonstrated through a low voltage bandgap reference fabricated in a 0.8 /spl mu/m CMOS process.
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paper_title: A CMOS bandgap reference circuit with sub-1-V operation

paper_content:

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.
---
paper_title: Curvature compensated BiCMOS bandgap with 1 V supply voltage

paper_content:

In this paper we present a bandgap circuit capable of generating a reference voltage of 0.54 V. The circuit, implemented in a submicron BiCMOS technology, operates with a supply voltage of 1 V. In the bandgap circuit proposed we use a non-conventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1 V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 5 ppm / K of accuracy without requiring additional operational amplifiers or complex circuits.
---
paper_title: A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device

paper_content:

A new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-μm CMOS process, where the occupied silicon area is only 177 μm x 106 μm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/°C from-10°C to 120°C without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10kHz.
---
paper_title: A CMOS subbandgap reference circuit with 1-v power supply voltage

paper_content:

A CMOS subbandgap reference circuit with 1-V supply voltage is described. To obtain subbandgap reference voltages with a 1-V supply voltage, threshold voltage reduction and subthreshold operation techniques are used. Large /spl Delta/V/sub BE/ (100 mV) as well as a 90-dB operational amplifier are used to circumvent the amplifier offset. A power-on-reset (POR) circuit is used as startup. This circuit has been implemented using a standard 0.5-/spl mu/m CMOS process, and its size is 940 /spl mu/m/spl times/1160/spl mu/m. The temperature coefficient is 17 ppm from -40/spl deg/C to 125/spl deg/C after resistor trimming and the minimum power supply voltage is 0.95 V. The measured total current consumption is below 10 /spl mu/A and the measured output voltage is 0.631 V at room temperature.
---
paper_title: New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation

paper_content:

A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-mum CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5 ppm/degC from 0 degC to 100 degC. With a 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz
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paper_title: CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V

paper_content:

A CMOS bandgap voltage reference (BVR) circuit is proposed that operates at power supply voltages down to 0.6 V. The BVR is designed in a commercially available 0.13 µm digital CMOS technology. No analogue process options are required.
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paper_title: Op-amps and startup circuits for CMOS bandgap references with near 1-V supply

paper_content:

The design of bandgap-based voltage references in digital CMOS raises several design difficulties, as the supply voltage is lower than the silicon bandgap in electron volts, i.e., 1.2 V. A current-mode architecture is used in order to address the main issues posed by the low supply, but the implementation of the operational amplifier and of dedicated startup circuits deserves some attention. Even if nonstandard devices such as depletion-mode MOS transistors may be helpful to manage the supply scaling, they are seldom available and poorly characterized. Therefore, they must be avoided in a robust design featuring a high portability. This paper proposes some circuit solutions suitable for very low-supply-voltage operation and addresses the main issues of achieving the correct bias point at the power on. A few bandgap references were implemented in digital 0.35- and 0.18-/spl mu/m technologies featuring a nominal output voltage of about 500 mV and minimum supplies from 1.5 to 0.9 V.
---
paper_title: A CMOS bandgap reference circuit with sub-1-V operation

paper_content:

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V/sub ref/ is the sum of the built-in voltage of the diode V/sub f/ and the thermal voltage V/sub T/ of kT/q multiplied by a constant. Therefore, V/sub ref/ is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V/sub ref/ has been converted from the sum of two currents; one is proportional to V/sub f/ and the other is proportional to V/sub T/. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-/spl mu/m flash memory process. Measured V/sub ref/ is 518/spl plusmn/15 mV (3/spl sigma/) for 23 samples on the same wafer at 27-125/spl deg/C.
---
paper_title: Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits

paper_content:

Mutual compensation of mobility and threshold voltage temperature variations may result in a zero temperature coefficient bias point of a MOS transistor. The conditions under which this effect occurs, and stability of this bias point are investigated. Possible applications of this effect include voltage reference circuits and temperature sensors with linear dependence of voltage versus temperature. The theory is verified experimentally investigating the temperature behavior of a simple voltage reference circuit realized in 0.35 /spl mu/m CMOS process.
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paper_title: Towards a sub-1 V CMOS voltage reference

paper_content:

A sub-1-V CMOS voltage reference which takes advantage of summing the gate-source voltages of two NMOS transistors operating in saturation region is presented. Both transistors are working below zero temperature coefficient point and thus the voltage reference is able to operate with low supply voltage. The circuit is implemented in a standard 0.18-/spl mu/m CMOS process and gives a temperature coefficient of 4 ppm//spl deg/C in the range of -50/spl deg/C to 150/spl deg/C.
---
paper_title: A low-voltage low-power voltage reference based on subthreshold MOSFETs

paper_content:

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.
---
paper_title: A Simple Subthreshold CMOS Voltage Reference Circuit With Channel- Length Modulation Compensation

paper_content:

This brief presents a simple reference circuit with channel-length modulation compensation to generate a reference voltage of 221 mV using subthreshold of MOSFETs at supply voltage of 0.85 V with power consumption of 3.3 muW at room temperature using TSMC 0.18-mum technology. The proposed circuit occupied in less than 0.0238 mm 2 achieves the reference voltage variation of 2 mV/V for supply voltage from 0.9 to 2.5V and about 6 mV of temperature variation in the range from -20degC to 120 degC. The agreement of simulation and measurement data is demonstrated
---
paper_title: CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

paper_content:

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.
---
paper_title: Low-power bandgap references featuring DTMOSTs

paper_content:

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 /spl mu/W; the die area is 0.063 mm/sup 2/ in a standard digital 0.35-/spl mu/m CMOS process. The second bandgap reference circuit aims at high accuracy operation (/spl sigma/=0.3%) without trimming. It consumes approximately 5 /spl mu/W from a 1.8-V supply voltage and occupies 0.06 mm/sup 2/ in a standard 0.35-/spl mu/m CMOS process.
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Title: Sub 1 V CMOS Bandgap Reference Design Techniques: A Survey

Section 1: Introduction
Description 1: Introduce the importance and application of bandgap voltage references and provide an overview of the paper.

Section 2: Design challenges of sub 1 V CMOS bandgap references
Description 2: Discuss the performance limitations and accuracy issues of sub 1 V CMOS bandgap references.

Section 3: Operational amplifier offset
Description 3: Describe the impact of operational amplifier offset on bandgap reference circuits.

Section 4: Current mirror mismatch
Description 4: Explain how mismatches in current mirrors affect the performance of bandgap reference circuits.

Section 5: Transistor mismatch
Description 5: Detail the effects of transistor mismatches on the accuracy of bandgap reference circuits.

Section 6: Package induced offset
Description 6: Discuss the packaging-induced mechanical stress and its impact on voltage references.

Section 7: Sub 1 V bandgap circuits based on resistive division technique
Description 7: Review circuits that use resistive division techniques to achieve sub 1 V bandgap references.

Section 8: BVR circuits that use threshold voltage reduction by forward biasing the substrate of the MOSFETs
Description 8: Describe the method of reducing threshold voltage through forward biasing to design low voltage bandgap references.

Section 9: BVR circuits based on the zero temperature coefficient point
Description 9: Explain the use of zero temperature coefficient points in MOSFETs for creating temperature-insensitive bandgap references.

Section 10: BVR circuits based on subthreshold MOSFET
Description 10: Review bandgap reference designs using subthreshold operation of MOSFETs for temperature-insensitive circuits.

Section 11: BVR circuits based on threshold voltage
Description 11: Detail the design and operation of bandgap references based on threshold voltage differences.

Section 12: BVR circuits based on virtual/real low-bandgap devices
Description 12: Discuss innovative techniques using low-bandgap devices for sub 1 V bandgap references.

Section 13: Summary
Description 13: Summarize the key takeaways and provide a comprehensive overview of the surveyed bandgap reference design techniques.