A survey of design techniques for system-level dynamic power management
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paper_title: Dynamic Power Management: Design Techniques and CAD Tools

paper_content:

From the Publisher: ::: Dynamic Power Management: Design Techniques and CAD Tools addresses design techniques and computer-aided design solutions for power management. Different approaches are presented and organized in an order related to their applicability to control-units, macro-blocks, digital circuits and electronic systems, respectively. All approaches are based on the principle of exploiting idleness of circuits, systems, or portions thereof. They involve both detection of idleness conditions and the freezing of power-consuming activities in the idle components. Dynamic Power Management: Design Techniques and CAD Tools is of interest to researchers and developers of computer-aided design tools for integrated circuits and systems, as well as to system designers.
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paper_title: Software Strategies for Portable Computer Energy Management

paper_content:

Limiting the energy consumption of computers, especially portables, is becoming increasingly important. Thus, new energy-saving computer components and architectures have been and continue to be developed. Many architectural features have both high-performance and low-power modes, with the mode selection under software control. The problem is to minimize energy consumption while not significantly impacting the effective performance. We group the software control issues as follows: transition, load-change, and adaptation. The transition problem is deciding when to switch to low-power, reduced-functionality modes. The load-change problem is determining how to modify the load on a component so that it can make further use of its low-power modes. The adaptation problem is determining how to create software that allows components to be used in novel, power-saving ways. We survey implemented and proposed solutions to software energy management issues created by existing and suggested hardware innovations.
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paper_title: PowerPC 603, a microprocessor for portable computers

paper_content:

The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking. System-level features include three software-programmable static power management modes and a hardware-programmable phase-lock loop. Operating at 80 MHz, the 603 typically dissipates 2.2 W, while achieving an estimated 75 Specint92 and 85 Specfp92. >
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paper_title: Technology directions for portable computers

paper_content:

This paper contains an evaluation of trends in the key system parameters (e.g., size, weight, function, performance, battery life) for battery-powered portable computers, together with a review of development trends in the technologies required for such systems. The discussion focuses on notebook-size portable computers. Those technologies which will have substantial impact on battery life and power budgets of future notebook computers receive the primary emphasis in this paper for example, liquid crystal displays, storage technology, wireless communication technology, and low power electronics. System power management is also be addressed. The basic theme of this paper is first to develop a view of what the key attributes of future notebook computers will be, and then to discuss how technologies must evolve to allow such systems to be advanced over the current state of the art in terms of portability and battery life. >
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paper_title: System-level power estimation and optimization

paper_content:

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of /spl sim/10%, and a 23% reduction in power after policy optimization.
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paper_title: Toward power-sensitive network architectures in wireless communications: concepts, issues, and design aspects

paper_content:

Transmitter power control can be used to concurrently achieve several key objectives in wireless networking, including minimizing power consumption and prolonging the battery life of mobile nodes, mitigating interference and increasing the network capacity, and maintaining the required link QoS by adapting to node movements, fluctuating interference, channel impairments, and so on. Moreover, power control can be used as a vehicle for implementing on-line several basic network operations, including admission control, channel selection and switching, and handoff control. We consider issues associated with the design of power-sensitive wireless network architectures, which utilize power efficiently in establishing user communication at required QoS levels. Our focus is mainly on the network layer and less on the physical one. Besides reviewing some of the developments in power control, we also formulate some general associated concepts which have wide applicability to wireless network design. A synthesis of these concepts into a framework for power-sensitive network architectures is done, based on some key justifiable points. Various important relevant issues are highlighted and discussed, as well as several directions for further research in this area. Overall, a first step is taken toward the design of power-sensitive network architectures for next-generation wireless networks.
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paper_title: Mobile power management for wireless communication networks

paper_content:

For fixed quality-of-service constraints and varying channel interference, how should a mobile node in a wireless network adjust its transmitter power so that energy consumption is minimized? Several transmission schemes are considered, and optimal solutions are obtained for channels with stationary, extraneous interference. A simple dynamic power management algorithm based on these solutions is developed. The algorithm is tested by a series of simulations, including the extraneous-interference case and the more general case where multiple, mutually interfering transmitters operate in a therefore highly responsive interference environment. Power management is compared with conventional power control for models based on FDMA/TDMA and CDMA cellular networks. Results show improved network capacity and stability in addition to substantially improved battery life at the mobile terminals.
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paper_title: Low power communications protocols: paging and beyond

paper_content:

Paging subscriber devices leverage multiple technologies to achieve low power and long battery life: semiconductors, circuits, systems architecture and network protocol. While many types of electronic devices have capitalized on low-power features for several of these technologies, few other than personal paging services have taken advantage of opportunities presented by well designed protocols with explicit power-reduction features. This paper will review the state-of-practice in existing paging services, and discuss the relevance of such techniques to other wireless communication systems.
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paper_title: Energy constrained error control for wireless channels

paper_content:

We posit that limiting the performance metrics of error control protocols to throughput and delay is inappropriate when terminals are powered by a finite energy battery source. We propose the total number of correctly transmitted packets during the lifetime of a finite energy source as another metric. We study the go-back-N error control protocol assuming (1) Markov errors on both the forward and the feedback channels and (2) a finite energy source with a flat power profile, and characterize the sensitivity of the total number of correctly transmitted packets to the choice of the output power level. We then generalize our results to arbitrary power profiles through both a recursive technique and Markov analysis. Finally, we compare the performance of GBN with an adaptive error control protocol (which slows down the transmission rate when the channel is impaired) and document the advantages.
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paper_title: Monitoring system activity for OS-directed dynamic power management

paper_content:

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy , which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of ∼10%, and a 23% reduction in power after policy optimization.
---
paper_title: System-level power estimation and optimization

paper_content:

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of /spl sim/10%, and a 23% reduction in power after policy optimization.
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paper_title: Guarded evaluation: pushing power management to logic synthesis/design

paper_content:

The need to reduce the power consumption of the next generation of digital systems is clearly recognized at all levels of system design. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. The ideas behind power management can be extended to the logic level. This would involve determining which parts of a circuit are computing results that will be used and which are not. The parts that are not needed are then "shut off". This paper describes an approach termed guarded evaluation, which is an implementation of this idea. A theoretical framework and the algorithms that form the basis of the approach are presented. The underlying idea is to automatically determine the parts of the circuit that can be disabled on a per-clock-cycle basis. This saves the power used in all the useless transitions in those parts of the circuit. Initial experiments indicate substantial power savings and the strong potential of this approach for a large number of benchmark circuits. While this paper presents the development of these ideas at the logic level of design, the same ideas have direct application at the register-transfer level of design also.
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paper_title: Adaptive Disk Spindown via Optimal Rent-to-Buy in Probabilistic Environments

paper_content:

In the {single rent-to-buy decision} problem, without a priori knowledge of the amount of time a resource will be used we need to decide when to buy the resource, given that we can rent the resource for \$1 per unit time or buy it once and for all for \$$c$. In this paper we study algorithms that make a sequence of single rent-to-buy decisions, using the assumption that the resource use times are independently drawn from an unknown probability distribution. Our study of this rent-to-buy problem is motivated by important systems applications, specifically, problems arising from deciding when to spindown disks to conserve energy in mobile computers~[DKM, LKH, MDK], thread blocking decisions during lock acquisition in multiprocessor applications~[KLM], and virtual circuit holding times in IP-over-ATM networks~[KLP, SaK]. We develop a provably optimal and computationally efficient algorithm for the rent-to-buy problem and evaluate its practical merit for the disk spindown scenario via simulation studies. Our algorithm uses $O(\sqrt{t})$ time and space, and its expected cost for the $t$th resource use converges to optimal as $O(\sqrt{\log t/t})$, for any bounded probability distribution on the resource use times. Alternatively, using $O(1)$ time and space, the algorithm almost converges to optimal. We describe the results of simulating our algorithm for the disk spindown problem using disk access traces obtained from an HP workstation environment. We introduce the natural notion of {\em effective cost\/} which merges the effects of energy conservation and response time performance into one metric based on a user specified parameter~$a$, the relative importance of response time to energy conservation. (The buy cost~$c$ varies linearly with~$a$.) We observe that by varying~$a$, we can model the tradeoff between power and response time well. We also show that our algorithm is best in terms of effective cost for almost all values of~$a$, saving effective cost by 6--25\% over the optimal online algorithm in the competitive model~(i.e., the 2-competitive algorithm that spins down the disk after waiting~$c$ seconds). In addition, for small values of~$a$ (corresponding to when saving energy is critical), our algorithm when compared against the optimal online algorithm in the competitive model reduces excess energy by 17--60\%, and when compared against the 5~second threshold reduces excess energy by 6--42\%.
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paper_title: Idleness is not sloth

paper_content:

Many people have observed that computer systems spend much of their time idle, and various schemes have been proposed to use this idle time productively. The commonest approach is to off-load activity from busy periods to less-busy ones in order to improve system responsiveness. In addition, speculative work can be performed in idle periods in the hopes that it will be needed later at times of higher utilization, or non-renewable resource like battery power can be conserved by disabling unused resources. ::: ::: We found opportunities to exploit idle time in our work on storage systems, and after a few attempts to tackle specific instances of it in ad hoc ways, began to investigate general mechanisms that could be applied to this problem. Our results include a taxonomy of idle-time detection algorithms, metrics for evaluating them, and an evaluation of a number of idleness predictors that we generated from our taxonomy.
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paper_title: Adaptive hard disk power management on personal computers

paper_content:

Dynamic power management can be effective for designing low-power systems. In many systems, requests are clustered into sessions. This paper proposes an adaptive algorithm that can predict session lengths and shut down components between sessions to save power. Compared to other approaches, simulations show that this algorithm can reduce power consumption in hard disks with less impact on performance or reliability.
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paper_title: Transformation and synthesis of FSMs for low-power gated-clock implementation

paper_content:

We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transformation for general incompletely speci ed Mealy-type machines that makes them suitable for gated clock implementation. The transformation is probabilistic-driven, and leads to the synthesis of an optimized combinational logic block that stops the clock with
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paper_title: Adaptive Disk Spin-Down Policies for Mobile Computers

paper_content:

Mobile computers typically spin down their hard disk after a fixed period of inactivity. If this threshold is too long, the disk wastes energy; if it is too short, the delay due to spinning the disk up again frushates the user. Usage patterns change over time, so a single fixed threshold may not be appropriate at all times. Also, different users may have varying pri- orities with respect to trading off energy conservation against performance. We describe a method for vary- ing the spin-down threshold dynamically by adapting to the user's access patterns and priorities. Adaptive spin-down can in some circumstances reduce by up to 507o the number of disk spin-ups that are deemed by the user to be inconvenient, while only moderately increasing energy consumption.
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paper_title: Predictive system shutdown and other architectural techniques for energy efficient programmable computation

paper_content:

With the popularity of portable devices such as personal digital assistants and personal communicators, as well as with increasing awareness of the economic and environmental costs of power consumption by desktop computers, energy efficiency has emerged as an important issue in the design of electronic systems. While power efficient ASIC's with dedicated architectures have addressed the energy efficiency issue for niche applications such as DSP, much of the computation continues to be implemented as software running on programmable processors such as microprocessors, microcontrollers, and programmable DSP's. Not only is this true for general purpose computation on personal computers and workstations, but also for portable devices, application-specific systems etc. In fact, firmware and embedded software executing on RISC and DSP processor cores that are embedded in ASIC's has emerged as a leading implementation methodology for speech coding, modem functionality, video compression, communication protocol processing etc. This paper describes architectural techniques for energy efficient implementation of programmable computation, particularly focussing on the computation needed in portable devices where event-driven user interfaces, communication protocols, and signal processing play a dominant role. Two key approaches described here are predictive system shutdown and extended voltage scaling. Results indicate that a large reduction in power consumption can be achieved over current day solutions with little or no loss in system performance.
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paper_title: A predictive system shutdown method for energy saving of event-driven computation

paper_content:

This paper presents a system-level power management technique for energy savings of event-driven application. We present a new predictive system-shutdown method to exploit sleep mode operations for energy saving. We use an exponential-average approach to predict the upcoming idle period. We introduce two mechanisms, prediction-miss correction and prewake-up, to improve the hit ratio and to reduce the delay overhead. Experiments on four different event-driven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of energy with low delay penaties.
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paper_title: Competitive randomized algorithms for nonuniform problems

paper_content:

Competitive analysis is concerned with comparing the performance of on-line algorithms with that of optimal off-line algorithms. In some cases randomization can lead to algorithms with improved performance ratios on worst-case sequences. In this paper we present new randomized on-line algorithms for snoopy caching and the spin-block problem. These algorithms achieve competitive ratios approachinge/(eź1) ź 1.58 against an oblivious adversary. These ratios are optimal and are a surprising improvement over the best possible ratio in the deterministic case, which is 2. We also consider the situation when the request sequences for these problems are generated according to an unknown probability distribution. In this case we show that deterministic algorithms that adapt to the observed request statistics also have competitive factors approachinge/(eź1). Finally, we obtain randomized algorithms for the 2-server problem on a class of isosceles triangles. These algorithms are optimal against an oblivious adversary and have competitive ratios that approache/(eź1). This compares with the ratio of 3/2 that can be achieved on an equilateral triangle.
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paper_title: Precomputation-based sequential logic optimization for low power

paper_content:

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. ::: We present an automatic method of synthesizing precomputational logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay.
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paper_title: Dynamic power management for nonstationary service requests

paper_content:

Dynamic power management (DPM) is a design methodology aimed at reducing power consumption of electronic systems by performing selective shutdown of idle system resources. The effectiveness of a power management scheme depends critically on accurate modeling of service requests and on computation of the control policy. In this work, we present an online adaptive DPM scheme for systems that can be modeled as finite-state Markov chains. Online adaptation is required to deal with initially unknown or nonstationary workloads, which are very common in real-life systems. Our approach moves from exact policy optimization techniques in a known and stationary stochastic environment and extends optimum stationary control policies to handle the unknown and nonstationary stochastic environment for practical applications. We introduce two workload learning techniques based on sliding windows and study their properties. Furthermore, a two-dimensional interpolation technique is introduced to obtain adaptive policies from a precomputed look-up table of optimum stationary policies. The effectiveness of our approach is demonstrated by a complete DPM implementation on a laptop computer with a power-manageable hard disk that compares very favorably with existing DPM schemes.
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paper_title: Policy optimization for dynamic power management

paper_content:

Dynamic power management schemes (also called policies) can be used to control the power consumption levels of electronic systems, by setting their components in different states, each characterized by a performance level and a power consumption. In this paper, we describe power-managed systems using a finite-state, stochastic model. Furthermore, we show that the fundamental problem of finding an optimal policy which maximizes the average performance level of a system, subject to a constraint on the power consumption, can be formulated as a stochastic optimization problem called policy optimization. Policy optimization can be solved exactly in polynomial time (in the number of states of the model). We implemented a policy optimization tool and tested the quality of the optimal policies on a realistic case study.
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paper_title: Dynamic power management based on continuous-time Markov decision processes

paper_content:

This paper introduces a continuous-time, controllable Markov process model of a power-managed system. The system model is composed of the corresponding stochastic models of the service queue and the service provider. The system environment is modeled by a stochastic service request process. The problem of dynamic power management in such a system is formulated as a policy optimization problem and solved using an efficient "policy iteration" algorithm. Compared to previous work on dynamic power management, our formulation allows better modeling of the various system components, the power-managed system as a whole, and its environment. In addition it captures dependencies between the service queue and service provider status. Finally, the resulting power management policy is asynchronous, hence it is more power-efficient and more useful in practice. Experimental results demonstrate the effectiveness of our policy optimization algorithm compared to a number of heuristic (time-out and N-policy) algorithms.
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paper_title: Event-driven power management of portable systems

paper_content:

The policy optimization problem for dynamic power management has received considerable attention in the recent past. We formulate policy optimization as a constrained optimization problem on continuous-time semi-Markov decision processes (SMDP). SMDPs generalize the stochastic optimization approach based on discrete-time Markov decision processes (DTMDP) presented in the earlier work by relaxing two limiting assumptions. In SMDPs, decisions are made at each event occurrence instead of at each discrete time interval as in DTMDP and thus saving power and giving higher performance. In addition, SMDPs can have general inter-state transition time distributions, allowing for greater generality and accuracy in modeling real-life systems where transition times between power states are not geometrically distributed.
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paper_title: Power considerations in the design of the Alpha 21264 microprocessor

paper_content:

Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented.
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paper_title: PowerPC 603, a microprocessor for portable computers

paper_content:

The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking. System-level features include three software-programmable static power management modes and a hardware-programmable phase-lock loop. Operating at 80 MHz, the 603 typically dissipates 2.2 W, while achieving an estimated 75 Specint92 and 85 Specfp92. >
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paper_title: Gated clock routing minimizing the switched capacitance

paper_content:

This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce switched capacitance of the clock tree. This work extends our previous work so as to account for the switched capacitance and the area of the gate control signal routing. Various tradeoffs between power and area for different design options and module activities are discussed and detailed experimental results are presented.
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paper_title: Reducing switching activity on datapath buses with control-signal gating

paper_content:

This paper presents a technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on buses. The focus of the technique is on achieving effective power savings with minimal overhead. When a bus is not going to be used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. The "observability don't-care condition" of a bus is defined to detect unnecessary switching activity on the bus. This condition is used to gate control signals going to the bus-driver modules so that switching activity on the module inputs does not propagate to the bus. A methodology for automatically synthesizing gated control signals from the register transfer level description of a design is presented. The technique has very low area, delay, power, and designer effort overhead. It was applied to one of the integer execution units of a 64-bit, two-way superscalar RISC microprocessor. Experimental results from running various application programs on the microprocessor show an average of 26.6% reduction in dynamic switching power in the execution unit, with no increase in critical path delay and negligible area overhead.
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paper_title: Precomputation-based sequential logic optimization for low power

paper_content:

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. ::: We present an automatic method of synthesizing precomputational logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay.
---
paper_title: Adaptive hard disk power management on personal computers

paper_content:

Dynamic power management can be effective for designing low-power systems. In many systems, requests are clustered into sessions. This paper proposes an adaptive algorithm that can predict session lengths and shut down components between sessions to save power. Compared to other approaches, simulations show that this algorithm can reduce power consumption in hard disks with less impact on performance or reliability.
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paper_title: Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

paper_content:

This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week turn-around-time.
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paper_title: A low-voltage CMOS DC-DC converter for a portable battery-operated system

paper_content:

Motivated by emerging battery-operated applications that demand compact, lightweight, and highly efficient DC-DC power converters, a buck circuit is presented in which all active devices are integrated on a single chip using a standard 1.2 /spl mu/ CMOS process. The circuit delivers 750 mW at 1.5 V from a 6 V battery. To effectively eliminate switching loss at high operating frequencies, the power transistors achieve nearly ideal zero-voltage switching (ZVS) through an adjustable dead-time control scheme. The silicon area and power consumption of the gate-drive buffers are reduced with a tapering factor that minimizes short-circuit current and dynamic dissipation for a given technology and application. Measured results on a prototype IC indicate that on-chip losses at full load can be kept below 8% at 1 MHz. >
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paper_title: Automated low-power technique exploiting multiple supply voltages applied to a media processor

paper_content:

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.
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paper_title: Data driven signal processing: an approach for energy efficient computing

paper_content:

The computational switching activity of digital CMOS circuits can be dynamically minimized by designing algorithms that exploit signal statistics. This results in processors that have time-varying power requirements and perform computation on demand. An approach is presented to minimize the energy dissipation per data sample in variable-load DSP systems by adaptively minimizing the power supply voltage for each sample using a variable switching speed processor. In general, using buffering and filtering, the computation can be spread over multiple samples averaging the workload and lowering energy further. It is also shown that four levels of voltage quantization combined with dithering is sufficient to closely emulate arbitrary voltage levels.
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paper_title: A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS

paper_content:

A 300 MIPS/W RISC core processor with variable supply-voltage (VS) scheme in variable threshold-voltage CMOS (VTCMOS) is presented. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except for substrate contacts for the VTCMOS. From a 3.3 V external power supply the VS scheme automatically generates minimum internal supply voltages which meet the demand on its operation frequency.
---
paper_title: Monitoring system activity for OS-directed dynamic power management

paper_content:

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy , which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of ∼10%, and a 23% reduction in power after policy optimization.
---
paper_title: Quantitative comparison of power management algorithms

paper_content:

Dynamic power management saves power by shutting down idle devices. Several management algorithms have been proposed and demonstrated to be effective in certain applications. We quantitatively compare the power saving and performance impact of these algorithms on hard disks of a desktop and notebook computers. This paper has three contributions. First, we build a framework in Windows NT to implement power managers running realistic workloads and directly interacting with users. Second, we define performance degradation that reflects user perception. Finally, we compare power saving and performance of existing algorithms and analyze the difference.
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paper_title: Software controlled power management

paper_content:

Reducing power consumption is critical in many system designs. Dynamic power management is an effective approach to decrease power without significantly degrading performance. Power management decisions can be implemented in either hardware or software. A recent trend on personal computers is to use software to change hardware power states. This paper presents a software architecture that allows system designers to investigate power management algorithms in a systematic fashion through a template. The architecture exploits the Advanced Configuration and Power Interface (ACPI), a standard for hardware and software. We implement two algorithms for controlling the power states of a hard disk on a personal computer running Microsoft Windows. By measuring the current feeding the hard disk, we show that the algorithms can save up to 25% more energy than the Windows power manager. Our work has two major contributions: a template for software-controlled power management and experimental comparisons of management algorithms for a hard disk.
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paper_title: System-level power estimation and optimization

paper_content:

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of /spl sim/10%, and a 23% reduction in power after policy optimization.
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Title: A Survey of Design Techniques for System-Level Dynamic Power Management

Section 1: Introduction
Description 1: Introduce the significance of high performance and low-power consumption in electronic circuits and system designs.

Section 2: Modeling Power-Managed Systems
Description 2: Explain how power-managed systems are modeled, focusing on the interaction between power-manageable components (PMC's) and power managers (PM's).

Section 3: Dynamic Power Management Techniques
Description 3: Discuss various techniques for controlling the power state of a system and its components, including predictive and stochastic control methods.

Section 4: Implementation of Dynamic Power Management
Description 4: Describe how different DPM schemes are implemented in circuits and systems, focusing on the infrastructure that enables complex power management policies.

Section 5: Conclusion
Description 5: Summarize the significance of DPM in reducing power consumption and the challenges involved in designing power management policies.