Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview
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paper_title: Elitist nondominated sorting genetic algorithm based RF IC optimizer

paper_content:

An optimization tool for radio frequency integrated circuits (RFICs) based on an elitist nondominated sorting genetic algorithm is introduced. It casts RF circuit synthesis as a multi-objective optimization problem and produces multiple solutions along the Pareto optimal front. Optimization is followed by sensitivity assessment wherein Monte Carlo simulations are performed for the Pareto points with respect to process, voltage, and temperature variations. The tool is validated in the synthesis of a 5.2-GHz direct-conversion receiver front-end that includes a common-gate differential low-noise amplifier, I/Q down-conversion mixers, and a quadrature voltage-controlled oscillator in a 250-nm SiGe BiCMOS process.
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paper_title: Global Design of Analog Cells using Statistical Optimization Techniques

paper_content:

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.
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paper_title: CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip

paper_content:

The paper gives an overview of methods and tools that are needed to design and embed analogue and RF blocks in mixed-signal integrated systems on chip (SoC). The design of these SoCs is characterised by growing design complexities and shortening time to market constraints. This requires new mixed-signal design methodologies and flows, including high-level architectural explorations and techniques for analogue behavioural modelling. This also calls for new methods to increase analogue design productivity, such as the reuse of analogue blocks as well as the adoption of analogue and RF circuit and layout synthesis tools. Also, more detailed modelling and verification tools are needed that can analyse signal integrity and crosstalk problems, especially noise coupling problems caused by the embedding of the analogue circuits in a digital environment. Solutions that already exist today are presented, and challenges that still remain to be solved are outlined.
---
paper_title: A novel heuristic for multi-objective optimization of analog circuit performances

paper_content:

We present a novel heuristic for optimizing analog circuit performances. It deals with generating the Pareto front using the topological properties of the feasible solution space. This heuristic allows us generating optimal values of circuit parameters in reduced computation time and memory consumption. Unlike basic metaheuristics, it does not need optimization background from the user in order to be easily adapted to different applications. It can thus be smoothly integrated into an automated design flow. This novel approach enables us to further improve (good) performances that were already reached using other optimizing techniques. Robustness of the algorithm was proved using specific difficult test problems.
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paper_title: Ant Algorithms for Discrete Optimization

paper_content:

This article presents an overview of recent work on ant algorithms, that is, algorithms for discrete optimization that took inspiration from the observation of ant colonies' foraging behavior, and introduces the ant colony optimization (ACO) metaheuristic. In the first part of the article the basic biological findings on real ants are reviewed and their artificial counterparts as well as the ACO metaheuristic are defined. In the second part of the article a number of applications of ACO algorithms to combinatorial optimization and routing in communications networks are described. We conclude with a discussion of related work and of some of the most important aspects of the ACO metaheuristic.
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paper_title: Elitist nondominated sorting genetic algorithm based RF IC optimizer

paper_content:

An optimization tool for radio frequency integrated circuits (RFICs) based on an elitist nondominated sorting genetic algorithm is introduced. It casts RF circuit synthesis as a multi-objective optimization problem and produces multiple solutions along the Pareto optimal front. Optimization is followed by sensitivity assessment wherein Monte Carlo simulations are performed for the Pareto points with respect to process, voltage, and temperature variations. The tool is validated in the synthesis of a 5.2-GHz direct-conversion receiver front-end that includes a common-gate differential low-noise amplifier, I/Q down-conversion mixers, and a quadrature voltage-controlled oscillator in a 250-nm SiGe BiCMOS process.
---
paper_title: Particle swarm optimization

paper_content:

A concept for the optimization of nonlinear functions using particle swarm methodology is introduced. The evolution of several paradigms is outlined, and an implementation of one of the paradigms is discussed. Benchmark testing of the paradigm is described, and applications, including nonlinear function optimization and neural network training, are proposed. The relationships between particle swarm optimization and both artificial life and genetic algorithms are described.
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paper_title: Local Search in Combinatorial Optimization

paper_content:

From the Publisher: ::: In the past three decades local search has grown from a simple heuristic idea into a mature field of research in combinatorial optimization. Local search is still the method of choice for NP-hard problems as it provides a robust approach for obtaining high-quality solutions to problems of a realistic size in a reasonable time. This area of discrete mathematics is of great practical use and is attracting ever increasing attention. The contributions to this book cover local search and its variants from both a theoretical and practical point of view, each with a chapter written by leading authorities on that particular aspect. This book is an important reference volume and an invaluable source of inspiration for advanced students and researchers in discrete mathematics, computer science, operations research, industrial engineering and management science.
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paper_title: Simulated annealing algorithms: an overview

paper_content:

A brief introduction is given to the actual mechanics of simulated annealing, and a simple example from an IC layout is used to illustrate how these ideas can be applied. The complexities and tradeoffs involved in attacking a realistically complex design problem are illustrated by dissecting two very different annealing algorithms for VLSI chip floorplanning. Several current research problems aimed at determining more precisely how and why annealing algorithms work are examined. Some philosophical issues raised by the introduction of annealing are discussed. >
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paper_title: A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology

paper_content:

This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.
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paper_title: Multimode Pareto fronts for design of reconfigurable analogue circuits

paper_content:

Multimode Pareto-optimal fronts are presented. This is a novel concept that can be key in the design of reconfigurable analogue circuits, because it contains information not only on the trade-offs among the circuit performances, but also on its reconfiguration capabilities. A method to generate the front, relying on evolutionary optimisation, and a general dominance sorting algorithm that guides the optimisation, are both described.
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paper_title: Pareto optimization of analog circuits considering variability

paper_content:

The trade-off between competing design objectives is often decided at the beginning of the analog sizing process by assigning weights to the design objectives. Architectural design, however, requires the knowledge of all possible optimal trade-offs of a building block. Methods for Pareto optimization provide the set of all optimal trade-offs, the so-called Pareto front. The next generation of analog Pareto optimization tools additionally has to consider the manufacturing variations. This paper describes an approach to this challenging problem. First, analog Pareto optimization will be developed as a set of specific nonlinear programming problems that provide a discretization of the Pareto front of competing performance features. Second, a general problem formulation to consider manufacturing variations and operating ranges of circuit parameters in analog Pareto optimization will be presented. Third, an efficient solution approach to the resulting tolerance Pareto optimization problem will be described. It is based on a combination of nominal Pareto optimization and realistic worst-case analysis on discrete Pareto points. It provides high efficiency at acceptable loss in accuracy. Copyright © 2008 John Wiley & Sons, Ltd.
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paper_title: A novel heuristic for multi-objective optimization of analog circuit performances

paper_content:

We present a novel heuristic for optimizing analog circuit performances. It deals with generating the Pareto front using the topological properties of the feasible solution space. This heuristic allows us generating optimal values of circuit parameters in reduced computation time and memory consumption. Unlike basic metaheuristics, it does not need optimization background from the user in order to be easily adapted to different applications. It can thus be smoothly integrated into an automated design flow. This novel approach enables us to further improve (good) performances that were already reached using other optimizing techniques. Robustness of the algorithm was proved using specific difficult test problems.
---
paper_title: Elitist nondominated sorting genetic algorithm based RF IC optimizer

paper_content:

An optimization tool for radio frequency integrated circuits (RFICs) based on an elitist nondominated sorting genetic algorithm is introduced. It casts RF circuit synthesis as a multi-objective optimization problem and produces multiple solutions along the Pareto optimal front. Optimization is followed by sensitivity assessment wherein Monte Carlo simulations are performed for the Pareto points with respect to process, voltage, and temperature variations. The tool is validated in the synthesis of a 5.2-GHz direct-conversion receiver front-end that includes a common-gate differential low-noise amplifier, I/Q down-conversion mixers, and a quadrature voltage-controlled oscillator in a 250-nm SiGe BiCMOS process.
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paper_title: Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

paper_content:

Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.
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paper_title: Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming

paper_content:

One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as high gain or low power consumption. In most cases one performance can only be optimized at cost of others, therefore a sizing must aim at an optimal trade-off between the important circuit performances. In this paper we present a new deterministic method to calculate the complete range of performance trade-offs, the so-called Pareto-optimal front, of a given circuit topology. Known deterministic methods solve a set of constrained multi-objective optimization problems independently of each other. The presented method minimizes a set of Goal Attainment (GA) optimization problems simultaneously. In a parallel algorithm, the individual GA optimization processes compare and exchange their iterative solutions. This leads to a significant improvement in the efficiency and quality of analog trade-off design.
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paper_title: Global Design of Analog Cells using Statistical Optimization Techniques

paper_content:

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.
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paper_title: An Efficient Constraint Handling Method for Genetic Algorithms

paper_content:

Many real-world search and optimization problems involve inequality and/or equality constraints and are thus posed as constrained optimization problems. In trying to solve constrained optimization problems using genetic algorithms (GAs) or classical optimization methods, penalty function methods have been the most popular approach, because of their simplicity and ease of implementation. However, since the penalty function approach is generic and applicable to any type of constraint (linear or nonlinear), their performance is not always satisfactory. Thus, researchers have developed sophisticated penalty functions specific to the problem at hand and the search algorithm used for optimization. However, the most difficult aspect of the penalty function approach is to find appropriate penalty parameters needed to guide the search towards the constrained optimum. In this paper, GA's population-based approach and ability to make pair-wise comparison in tournament selection operator are exploited to devise a penalty function approach that does not require any penalty parameter. Careful comparisons among feasible and infeasible solutions are made so as to provide a search direction towards the feasible region. Once sufficient feasible solutions are found, a niching method (along with a controlled mutation operator) is used to maintain diversity among feasible solutions. This allows a real-parameter GA's crossover operator to continuously find better feasible solutions, gradually leading the search near the true optimum solution. GAs with this constraint handling approach have been tested on nine problems commonly used in the literature, including an engineering design problem. In all cases, the proposed approach has been able to repeatedly find solutions closer to the true optimum solution than that reported earlier.
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paper_title: Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier–Motzkin Elimination

paper_content:

This paper presents two simulation-based methods for the calculation of the feasible performance values of analog integrated circuits. The first method computes the Pareto-optimal tradeoffs of competing performances at full simulator accuracy. Additionally, it identifies and evaluates the technological and structural constraints that prevent further performance improvement. The second method computes linear approximations to the feasible performance regions of circuits with a large number of performances. Both techniques allow a comparison of different circuit topologies with respect to their performance capabilities and contribute to hierarchical circuit sizing. The presented methods are validated by experimental results of Pareto-front computation and feasible performance region computation of operational amplifiers and hierarchical sizing of filters.
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paper_title: CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip

paper_content:

The paper gives an overview of methods and tools that are needed to design and embed analogue and RF blocks in mixed-signal integrated systems on chip (SoC). The design of these SoCs is characterised by growing design complexities and shortening time to market constraints. This requires new mixed-signal design methodologies and flows, including high-level architectural explorations and techniques for analogue behavioural modelling. This also calls for new methods to increase analogue design productivity, such as the reuse of analogue blocks as well as the adoption of analogue and RF circuit and layout synthesis tools. Also, more detailed modelling and verification tools are needed that can analyse signal integrity and crosstalk problems, especially noise coupling problems caused by the embedding of the analogue circuits in a digital environment. Solutions that already exist today are presented, and challenges that still remain to be solved are outlined.
---
paper_title: Analog circuit optimization system based on hybrid evolutionary algorithms

paper_content:

This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met, even in highly-constrained situations. Comparisons with available methods like genetic algorithms and differential evolution, which use static penalty functions to handle design constraints, have also been carried out, showing that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.
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paper_title: A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology

paper_content:

This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.
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Title: Applications of Evolutionary Computation Techniques to Analog, Mixed-Signal, and RF Circuit Design - An Overview

Section 1: INTRODUCTION
Description 1: This section introduces strategies for automating the sizing of AMS/RF circuits and outlines the scope of the paper.

Section 2: BASIC EVOLUTIONARY COMPUTATION TECHNIQUES
Description 2: This section covers the fundamental evolutionary computation techniques used in AMS/RF circuit design, including evolutionary algorithms and swarm intelligence algorithms.

Section 3: MULTI-OBJECTIVE OPTIMIZATION
Description 3: This section discusses the application of evolutionary computation techniques to multi-objective optimization in AMS/RF circuit design, with a focus on Pareto-optimal fronts.

Section 4: CONSTRAINT HANDLING
Description 4: This section addresses the methods used for handling constraints in the optimization of AMS/RF circuit designs.

Section 5: CHALLENGES
Description 5: This section identifies and elaborates on the current challenges in applying evolutionary computation techniques to AMS/RF circuit design, including efficiency, accuracy, and handling process variations.