An Overview of Reconfigurable Hardware in Embedded Systems
---
paper_title: Implementation of Multi-Standard Wireless Communication Receivers in a Heterogeneous Reconfigurable System-on-Chip

paper_content:

Future mobile terminals become multi-mode communication systems. In order to handle different standards, we propose to perform baseband processing in heterogeneous reconfigurable hardware. Not only the baseband processing but also error decoding differs for every communication system. We already proposed implementations of the baseband processing part of an OFDM receiver and a Wideband CDMA receiver in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. Now, we also implemented an adaptive Viterbi decoder in the same coarse-grained MONTIUM architecture. The rate, constraint length and decision depth of the decoder can be adjusted to different communication systems. We show that the flexibility in the coarse-grained reconfigurable architecture is more than 200 times as energy-efficient compared to a general purpose solution but only 24 times less efficient compared to a dedicated solution
---
paper_title: Reconfigurable computing: architectures and design methods

paper_content:

Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.
---
paper_title: Hardware software tri-design of encryption for mobile communication units

paper_content:

We explore the design space of field programmable gate arrays (FPGAs), processors and ASICs-hardware-software tri-design-in the framework of encryption for hand-held communication units. The IDEA (International Data Encryption Algorithm) is used to show the tradeoffs for the suggested technologies. The measures for comparing different options are: performance, programmability and power (P/sup 3/). More specifically we use the performance to power, or operations to energy ratio MOPS/Watt and Mbits/s/Watt to compare processors, FPGAs and ASICs. We compare the latest digital signal processor (DSP) from Texas Instruments to Xilinx XC4000 series FPGAs. Many DSP-like applications perform very well on FPGAs. We show the benefits and limitations of FPGA technology for IDEA.
---
paper_title: A pipelined configurable gate array for embedded processors

paper_content:

In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μ m CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.
---
paper_title: Measuring the gap between FPGAs and ASICs

paper_content:

This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed hoices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power onsumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.
---
paper_title: Reconfigurable computing: a survey of systems and software

paper_content:

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.
---
paper_title: Antifuse field programmable gate arrays

paper_content:

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated. >
---
paper_title: Cost-effective strategies for ASIC masks

paper_content:

It is suggested that the high cost of mask sets for 90nm and below technologies may restrict the application of technologies to a handful of high volume chips. Most of the cost for mask production is a result of the increased time to write and inspect (including defect disposition) a mask due to the large files that are created prior to mask writing. Stringent mask specifications needed for low k factor imaging drive protracted and costly yield learning curves for a ::: mask maker. The cost of different steps in the flow from design tape-out to final wafer test are analyzed and it is shown that limiting the reticle field size on critical layers could reduce net costs. The net die cost is lower as long as the number of processed wafers stays below a cutoff number. Costs can be further decreased by reducing the overall "figure count" (and hence writing time) for an ASIC chip by restricting the amount of OPC done on critical layers.
---
paper_title: Seeking solutions in configurable computing

paper_content:

Configurable computing offers the potential of producing powerful new computing systems. Will current research overcome the dearth of commercial applicability to make such systems a reality? Unfortunately, no system to date has yet proven attractive or competitive enough to establish a commercial presence. We believe that ample opportunity exists for work in a broad range of areas. In particular, the configurable computing community should focus on refining the emerging architectures, producing more effective software/hardware APIs, better tools for application development that incorporate the models of hardware reconfiguration, and effective benchmarking strategies.
---
paper_title: Computing Requirements for Self-Repairing Space Systems

paper_content:

The United States recently announced ambitious plans for extended human and robotic exploration of the moon and mars. Coupled with efforts to complete the International Space Station, clearly mankind is destined to deploy increasingly more complex manned systems and for longer periods of time in Space. These systems, however, require fault-tolerant and highly adaptive real-time computer systems to control them. Fortunately, new technologies such as the field programmable gate array (FPGA) offer a flexible platform to develop robust, adaptable, self-repairing systems for space. But this new technology is itself vulnerable and therefore must be used with caution by augmenting existing practices with new techniques. The contribution of this paper is an overview and synthesis of recent developments in FPGA-based reconfigurable real-time system, and a discussion of reconfiguration issues in space applications. From these a system formalization, a proposed set of architectural and operating systems requirements, and suggestions for future work for FPGA-based self-repairing space systems are given.
---
paper_title: The MOLEN processor prototype

paper_content:

We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyping platform. Experimental results prove the viability of the MOLEN concept. More precisely, the MPEG-2 application is accelerated very closely to its theoretical limits by implementing SAD, DCT and IDCT in reconfigurable hardware. The MPEG-2 encoder overall speedup is in the range between 2.80 and 2.96. The speedup of the MPEG-2 decoder varies between 1.56 and 1.63.
---
paper_title: Trends in reconfigurable logic and reconfigurable computing

paper_content:

The paper gives a survey on reconfigurable logic and reconfigurable computing technologies, and on recent R&D trends in these areas. The paper also points out the weaker aspects of recent developments and proposes new directions to follow, driven by technology progress, a growing variety of reconfigurable platforms, and, innovations in EDA. Deep submicron technology allows SoC implementation, and the silicon IP business reduces entry barriers for newcomers and turns infrastructures of existing players into a liability.
---
paper_title: The Roles of FPGAs in Reprogrammable Systems

paper_content:

Reprogrammable systems based on field programmable gate arrays are revolutionizing some forms of computation and digital logic. As a logic emulation system, they provide orders of magnitude faster computation than software simulation. As a custom-computing machine, they achieve the highest performance implementation for many types of applications. As a multimode system, they yield significant hardware savings and provide truly generic hardware. In this paper, we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems.
---
paper_title: Evaluation of a Low-Power Reconfigurable DSP Architecture

paper_content:

Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.
---
paper_title: RECASTER: synthesis of fault-tolerant embedded systems based on dynamically reconfigurable FPGAs

paper_content:

Summary form only given. We present a fault-tolerant embedded system design methodology that uses dynamically reconfigurable FPGAs as spares for several dedicated hardware components. The key advantage is the reduction of area or cost as compared to dedicated spares. During normal operation, each FPGA is dynamically reconfigured with system tasks and can replace any of them if a fault is detected. For a specified coverage, i.e., system tasks that might be affected by a single fault, our algorithm allocates a set of FPGAs and determines schedules, including task executions and FPGA reconfigurations, that provide the required redundancy while satisfying deadlines and minimizing either area or cost. For each task requiring simple redundancy, the algorithm also determines a schedule in which an FPGA replaces this task. Our experimental results indicate that, with a smaller area and cost, this collective redundancy based on dynamically reconfigurable FPGAs allows system recovery from a larger number of single faults, each affecting one task, as compared to the conventional spare approach.
---
paper_title: Architecture of Field-Programmable Gate Arrays

paper_content:

A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed. >
---
paper_title: Implementing an OFDM receiver on the RaPiD reconfigurable architecture

paper_content:

Reconfigurable architectures have been touted as an alternative to ASICs and DSPs for applications that require a combination of high performance and flexibility. However, the use of fine-grained FPGA architectures in embedded platforms is hampered by their very large overhead. This overhead can be reduced substantially by taking advantage of an application domain to specialize the reconfigurable architecture using coarse-grained components and interconnects. This paper describes the design and implementation of an OFDM Receiver using the RaPiD architecture and RaPiD-C programming language. We show a factor of about 6x increase in cost-performance over a DSP implementation and 15x over an FPGA implementation.
---
paper_title: Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture

paper_content:

Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.
---
paper_title: FPGA implementation of an OFDM PHY

paper_content:

Orthogonal frequency division multiplexing (OFDM) based communication is increasingly being used in environments that exhibit severe multipath. While there are ASSP solutions for many common (e.g. 802.11a) and emerging standards, many communication systems, for example a military software radio, demand flexibility. The arithmetic requirements of an OFDM system can be very demanding. Even the ubiquitous 802.11a WLAN system has arithmetic requirements in the billions-of-operations per second region and cannot be satisfied even by high-end DSP microprocessors. This paper reports on the FPGA implementation of an OFDM transceiver. In addition to the FFT based modulator and demodulator, receiver synchronization and channel estimation is discussed. The FPGA resource requirements of the various sub-systems are reported and the design methodology employed for system design, verification and FPGA implementation is described.
---
paper_title: Massively parallel wireless reconfigurable processor architecture and programming

paper_content:

We propose a massively parallel reconfigurable processor architecture targetted for the implementation of advanced wireless communication algorithms featuring matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the space representation of the algorithm in Simulink. The Simulink description is parsed and the algorithm's dependence flow graph is derived, which is scheduled and space-time mapped onto the proposed architecture. The compiler reconfigures the switch boxes of the proposed hierarchical interconnection network in the architecture. An energy consumption model is derived, and design examples are provided that demonstrate the enhanced energy efficiency of the proposed architecture compared to a state of the art programmable DSP.
---
paper_title: A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core

paper_content:

We present a case study involving the implementation of a complete Wideband CDMA (WCDMA) digital receiver part of an AMR channel onto a reconfigurable core. WCDMA is one of the two major standards for the third generation (3G) cellular systems. Traditionally most of the receiver components were confined to ASIC implementation for performance, size and power consumption reasons. The MS1 reconfigurable DSP core provides both a microprocessor and reconfigurable fabric as well as a variety of peripherals. The various functions of the receiver were mapped onto different core components. The complete system was tested both in simulation as well as on a hardware platform comprising a silicon implementation of the MS1 DSP core.
---
paper_title: Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems

paper_content:

The evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. The system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper presents first the major challenges in realizing flexible microelectronic system solutions for future mobile communication applications. Based thereupon, the architecture design of flexible system-on-a-chip solutions in the digital baseband processing for future mobile radio devices is discussed. The focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.
---
paper_title: Parallel-beam backprojection: an FPGA implementation optimized for medical imaging

paper_content:

Medical image processing in general and computerized tomography (CT) in particular can benefit greatly from hardware acceleration. This application domain is marked by computationally intensive algorithms requiring the rapid processing of large amounts of data. To date, reconfigurable hardware has not been applied to this important area. For efficient implementation and maximum speedup, fixed-point implementations are required. The associated quantization errors must be carefully balanced against the requirements of the medical community. Specifically, care must be taken so that very little error is introduced compared to floating-point implementations and the visual quality of the images is not compromised. In this paper, we present an FPGA implementation of the parallel-beam backprojection algorithm used in CT for which all of these requirements are met. We explore a number of quantization issues arising in backprojection and concentrate on minimizing error while maximizing efficiency. Our implementation shows significant speedup over software versions of the same algorithm, and is more flexible than an ASIC implementation. Our FPGA implementation can easily be adapted to both medical sensors with different dynamic ranges as well as tomographic scanners employed in a wider range of application areas including nondestructive evaluation and baggage inspection in airport terminals.
---
paper_title: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration

paper_content:

Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet processing circuits on this platform are implemented as Dynamic Hardware Plugin (DHP) modules that fit within a specific region of an FPGA device. The PARBIT tool has been developed to transform and restructure bitfiles created by standard computer aided design tools into partial bitsteams that program DHPs. The methodology allows the platform to hot-swap application-specific DHP modules without disturbing the operation of the rest of the system.
---
paper_title: Pattern matching in reconfigurable logic for packet classification

paper_content:

We describe a digital circuit synthesis algorithm specialized for the domain of pattern matching circuits implemented in reconfigurable logic. We propose to use this algorithm as part of a system for implementing high-throughput pattern classification, for instance as part of a packet filter in an internetwork router. The goals of the approach are throughputs on the order of 100M classifications per second with reconfiguration times (including all synthesis) being held to a minimum.We evaluate the algorithms using rulesets from a pattern classification problem in networking, IP firewalling (150 rules on 100 bits), and evaluate their fitness to handle the demands placed on them by high-speed networks. In addition we use synthetic rulesets in an attempt to explore the scalability of our algorithm.
---
paper_title: A methodology for synthesis of efficient intrusion detection systems on FPGAs

paper_content:

Intrusion detection for network security is a computation intensive application demanding high system performance. System level design, a relatively unexplored field in this area, allows more efficient communication and extensive reuse of hardware components for dramatic increases in area-time performance. By applying optimization strategies to the entire database, we reduce hardware requirements compared to architectures designed with single pattern matchers in mind. We present a methodology for system-wide integration of graph-based partitioning of large intrusion detection pattern databases. Integrating ruleset-based graph creation and min-cut partitioning, our methodology allows efficient multi-byte comparisons and partial matches for high performance FPGA-based network security. Through pre-processing, this methodology yields designs with competitive clock frequencies that are a minimum of 8x more area efficient than previous non-predecoded shift-and-compare architectures.
---
paper_title: Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware

paper_content:

A library of layered protocol wrappers processes Internet packets in reconfigurable hardware. Collectively, the wrappers simplify and streamline the implementation of high-level networking functions by abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform called the field-programmable port extender (FPX). The library processes asynchronous transfer mode (ATM) cells, ATM adaptation layer 5 (AAL5) frames, Internet protocol (IP) messages, and user datagrarn protocol (UDP) packets directly in hardware. Applications can process data at several layers of the protocol stack using the library of wrappers discussed in this article. Layers are important for networks because they let applications abstract from above and below details of the network protocols. At the lowest layer, networks modify raw data passing between interfaces. At higher levels, the applications process variable length frames or IP packets.A network platform called the field-programmable port extender (FPX) streamlines and simplifies network transmission processing directly in hardware.
---
paper_title: Hardware software tri-design of encryption for mobile communication units

paper_content:

We explore the design space of field programmable gate arrays (FPGAs), processors and ASICs-hardware-software tri-design-in the framework of encryption for hand-held communication units. The IDEA (International Data Encryption Algorithm) is used to show the tradeoffs for the suggested technologies. The measures for comparing different options are: performance, programmability and power (P/sup 3/). More specifically we use the performance to power, or operations to energy ratio MOPS/Watt and Mbits/s/Watt to compare processors, FPGAs and ASICs. We compare the latest digital signal processor (DSP) from Texas Instruments to Xilinx XC4000 series FPGAs. Many DSP-like applications perform very well on FPGAs. We show the benefits and limitations of FPGA technology for IDEA.
---
paper_title: Single-chip FPGA implementation of a cryptographic co-processor

paper_content:

A secure communications protocol contains a symmetric key cryptosystem, a hash algorithm and a method for providing digital signatures and key exchange using public key cryptography. This work presents an implementation of these core ciphers on a single FPGA. A novel architecture combining a symmetric-key and message authentication algorithm is proposed, with FIFO memory-blocks used as buffers to allow them run in parallel from the same data source. The generation of digital signatures and key exchange using a modular exponentiator core block is also considered. The complete design is implemented on a PCI prototyping card containing a Xilinx Virtex-2000E FPGA and SRAM memory banks. To optimise the data transfer rate between the SRAMs and the FPGA. The memory interface and encryption cores are partitioned into separate clock domains. Comparisons are then made between theoretical results from timing analysis reports and implemented results on the prototyping card.
---
paper_title: Recent advances in solar adaptive optics

paper_content:

Solar adaptive optics has become an indispensable tool at ground based solar telescopes. Over the last few years several solar adaptive optics systems have been deployed at major ground based solar telescopes. These systems enable diffraction limited observations of the sun for a significant fraction of the available observing time at these telescopes. New ground breaking scientific results have been achieved with solar adaptive optics. This paper summarizes the recent progress in the field of solar adaptive optics.
---
paper_title: Reconfigurable data acquisition system for weather radar applications

paper_content:

Tornado, hazardous weather and flood detection radars demand high-throughput, high-speed data acquisition and processing. Weather-processing systems need to be capable of implementing powerful signal processing algorithms on the raw data collected by the radars. Following processing, data is distributed to the end-user in real-time for timely and accurate detection of imminent weather disasters. Since physical accessibility to such systems is often limited, remote-user based control and reconfiguration of processing capabilities are also essential. A real-time data acquisition, processing and distribution system for weather radar applications that meets these needs is described in this paper. This FPGA-based system has been successfully integrated with a radar optimized for tornado detection and deployed in the field
---
paper_title: SPIHT image compression on FPGAs

paper_content:

In this paper, we present an implementation of the image compression routine set partitioning in hierarchical trees (SPIHT) in reconfigurable logic. A discussion on why adaptive logic is required, as opposed to an application specific integrated circuit (ASIC), is provided along with background material on the image compression algorithm. We analyzed several discrete wavelet transform (DWT) architectures and selected the folded DWT design. In addition we provide a study on what storage elements are required for each wavelet coefficient. A modification to the original SPIHT algorithm is implemented to parallelize the computation. The architecture of our SPIHT engine is based upon fixed-order SPIHT, developed specifically for use within adaptive hardware. For an N/spl times/N image fixed-order SPIHT may be calculated in N/sup 2//4 cycles. Square images which are powers of 2 up to 1024/spl times/1024 are supported by the architecture. Our system was developed on an Annapolis Microsystems WildStar board populated with Xilinx Virtex-E parts. The system achieves a 450/spl times/ speedup versus a microprocessor solution, with less than a 0.2-db loss in peak signal-to-noise ratio over traditional SPIHT.
---
paper_title: The design of Mars lander cameras for Mars Pathfinder, Mars Surveyor '98 and Mars Surveyor '01

paper_content:

The Mars Pathfinder, Mars Surveyor '98, and Mars Surveyor '01 lander designs all utilize CCD-based cameras to conduct scientific investigations, assist with navigation of surface reverse and/or confirm sample acquisition and delivery by robotic arms. The extreme temperature and pressure environment of the Martian surface, the vibration and shock experienced during launch and landing, and the tight volume, mass, and power budgets challenge the designer and scientist alike to develop instruments and associated electronics that will function properly to provide the desired data. This paper provides an overview of the optical and mechanical design of two of the camera configurations, as well as a detailed description of the camera electronics. The cameras described are a gimbal-mounted stereo multi-spectral imager with 1 mrad/pixel resolution, and a variable focus robotic arm camera capable of 23-/spl mu/m/pixel resolution and provided with a self-contained three-color illumination system. The electronics, housed in the cameras and in separate enclosures, utilizes such subsystems as FPGAs for digital control, VME bus-mapped video memory, and multiplexed stepper motor select/phase driver circuitry.
---
paper_title: Toward on-board synthesis and adaptation of electronic functions: An evolvable hardware approach

paper_content:

Future remote interplanetary space mission will drive the system to higher degrees of autonomy to adapt to new environments and perform new functions, beyond those specified at launch. Adaptation enables long-life meaningful survivability and should include both software and hardware. Reconfigurable hardware could speedup computation intensive tasks by orders of magnitude and could ensure fault-tolerance bypassing faulty cells. Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. The search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Initial experiments demonstrate the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits based on evolution on Programmable Transistor Arrays (PTAs). The approach is illustrated by an experiment showing evolutionary synthesis of a circuit with a desired DC characteristic; evolution using a software model of the PTA took /spl sim/20 minutes on a supercomputer and is expected to be take /spl sim/5 seconds on a PTA chip.
---
paper_title: Smart camera based on reconfigurable hardware enables diverse real-time applications

paper_content:

We demonstrate the use of a "smart camera " to accelerate two very different image processing applications. The smart camera consists of a high quality video camera and frame grabber connected directly to an FPGA processing board. The advantages of this setup include minimizing the movement of large datasets and minimizing the latency by starting to process data before a complete frame has been acquired. The two applications, one from the area of medical image processing and the other from computational fluid dynamics both exhibit speedups of more than 20 times over software implementations on a 1.5 GHz PC. This smart camera setup is enabling image processing implementations that have not, before now, been achievable in real time.
---
paper_title: FPGA-based acceleration of the 3D finite-difference time-domain method

paper_content:

In order to take advantage of the significant benefits afforded by computational electromagnetic techniques, such as the finite-difference time-domain (FDTD) method, solvers capable of analyzing realistic problems in a reasonable time frame are required. Although software-based solvers are frequently used, they are often too slow to be of practical use. To speed up computations, hardware-based implementations of the FDTD method have been recently proposed. In this paper, we present our most recent progress in the area of FPGA-based 3D FDTD accelerators. Three aspects of the design are discussed, including the host-PC interface, memory hierarchy, and computational datapath. Implementation and benchmarking results are also presented, demonstrating that this accelerator is capable of at least three-fold speedups over thirty-node PC clusters.
---
paper_title: Reconfigurable computing: architectures and design methods

paper_content:

Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.
---
paper_title: Reconfigurable computing: a survey of systems and software

paper_content:

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.
---
paper_title: Seeking solutions in configurable computing

paper_content:

Configurable computing offers the potential of producing powerful new computing systems. Will current research overcome the dearth of commercial applicability to make such systems a reality? Unfortunately, no system to date has yet proven attractive or competitive enough to establish a commercial presence. We believe that ample opportunity exists for work in a broad range of areas. In particular, the configurable computing community should focus on refining the emerging architectures, producing more effective software/hardware APIs, better tools for application development that incorporate the models of hardware reconfiguration, and effective benchmarking strategies.
---
paper_title: Trends in reconfigurable logic and reconfigurable computing

paper_content:

The paper gives a survey on reconfigurable logic and reconfigurable computing technologies, and on recent R&D trends in these areas. The paper also points out the weaker aspects of recent developments and proposes new directions to follow, driven by technology progress, a growing variety of reconfigurable platforms, and, innovations in EDA. Deep submicron technology allows SoC implementation, and the silicon IP business reduces entry barriers for newcomers and turns infrastructures of existing players into a liability.
---
paper_title: The Roles of FPGAs in Reprogrammable Systems

paper_content:

Reprogrammable systems based on field programmable gate arrays are revolutionizing some forms of computation and digital logic. As a logic emulation system, they provide orders of magnitude faster computation than software simulation. As a custom-computing machine, they achieve the highest performance implementation for many types of applications. As a multimode system, they yield significant hardware savings and provide truly generic hardware. In this paper, we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems.
---
paper_title: Architecture of Field-Programmable Gate Arrays

paper_content:

A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed. >
---
paper_title: Object oriented circuit-generators in Java

paper_content:

Generators, parameterized code which produces a digital design, have long been a staple of the VLSI community. In recent years, several field programmable gate array (FPGA) design tools have adopted generators, as it is a convenient way to specify reusable designs in a familiar programming environment. We have built a generator framework in Java as a basis for programming reconfigurable devices and as a tool to be embedded in larger development systems. In addition to the conventional benefits of generators, this powerful framework allows for partial evaluation, simulation, specialization, and easy inclusion of other automatic services. In order to verify the utility of this system, we have implemented several applications using this framework and compared them with implementations using schematic capture and HDL synthesis. Our system runs significantly faster and produces comparable or superior results when mapped to a target FPGA.
---
paper_title: Performance modeling of reconfigurable SoC architectures and energy-efficient mapping of a class of application

paper_content:

Reconfigurable system-on-chip (RSoC) devices are being used to implement many battery-operated systems, where energy efficiency is a major concern. RSoCs incorporate may different components, such as processor core, reconfigurable logic, memory, etc. various power management techniques can be applied to these components. Tasks within an application can be mapped onto different components for execution. The communication and reconfiguration costs incurred under different mappings significantly impact the overall system energy dissipation. In order to achieve energy-efficient designs on RSoCs, we develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient mapping problem for a class of applications, and (c) a dynamic programming algorithm that minimizes the system energy dissipation. We illustrate our approach by mapping two beamforming applications onto Xilinx Virtex-II Pro. For these two applications, our approach leads to an average 52% energy reduction over a greedy algorithm.
---
paper_title: Implementing logic in FPGA memory arrays: heterogeneous memory architectures

paper_content:

It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement logic. In this paper we investigate how the architecture of the FPGA embedded arrays affects their ability to implement logic. Specifically, we focus on architectures which contain more than one size of memory array. We show that these heterogeneous architectures result in significantly denser implementations of logic than architectures with only one size of memory array. We also show that the best heterogeneous architecture contains both 2048 bit arrays and 128 bit arrays.
---
paper_title: Design patterns for reconfigurable computing

paper_content:

It is valuable to identify and catalog design patterns for reconfigurable computing. These design patterns are canonical solutions to common and recurring design challenges which arise in reconfigurable systems and applications. The catalog can form the basis for creating designs, for educating new designers, for understanding the needs of tools and languages, and for discussing reconfigurable design. Tying application and implementation lessons to the expansion and refinement of this catalog make those lessons more relevant to the design community. In this paper, we articulate this role for design patterns in reconfigurable computing, provide a few example patterns, offer a starting point for the contents of the catalog, and discuss the potential benefits of this effort.
---
paper_title: QuickRoute: a fast routing algorithm for pipelined architectures

paper_content:

As interconnect delays begin to dominate logic delays in large circuits, pipelined interconnects will be needed to achieve the highest performance. In FPGAs, this pipelining will be provided by the configurable interconnect architecture itself. This changes the routing problem substantially since the shortest path problem, which is at the core of any router, becomes NP-hard when latency constraints are added. That is, if signals must be routed through a given number of registers between source and destination, an efficient shortest path algorithm like Djikstra's algorithm is no longer an option. We propose here an approximate algorithm that uses simple heuristics to solve the pipelined shortest path problem efficiently. We have incorporated QuickRoute in the PathFinder router to route pipelined interconnects. We present the results achieved with QuickRoute for several circuits with heavily pipelined interconnect which show an improvement over a previously described algorithm.
---
paper_title: A study of the scalability of on-chip routing for just-in-time FPGA compilation

paper_content:

Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously introduced the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to a field-programmable gate array (FPGA). Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step. As FPGAs continue to increase in size, a JIT FPGA compiler must be capable of efficiently mapping increasingly larger hardware circuits. In this paper, we analyze the scalability of our lean on-chip router, the Riverside on-chip router (ROCR), for routing increasingly large hardware circuits. We demonstrate that ROCR scales well in terms of execution time, memory usage and circuit quality, and we compare the scalability of ROCR to the well known versatile place and route (VPR) timing-driven routing algorithm, comparing to both their standard routing algorithm and their fast routing algorithm. Our results show that on average ROCR executes 3 times faster using 18 times less memory than VPR. ROCR requires only 1% more routing resources, while creating a critical path 30% longer VPR's standard timing-driven router. Furthermore, for the largest hardware circuit, ROCR executes 3 times faster using 14 times less memory, and results in a critical path 2.6% shorter than VPR's fast timing-driven router.
---
paper_title: Fast timing-driven partitioning-based placement for island style FPGAs

paper_content:

In this paper we propose a partitioning-based algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR according to V. Betz and J. Rose (1997). As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization. An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase. Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime.
---
paper_title: Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

paper_content:

Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to effectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the pre-defined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the pre-designed dual-Vdd layout pattern introduces non-negligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs. To our best knowledge, it is the first in-depth study on applying both dual-Vdd and dual-Vt to FPGA considering circuits, fabrics and CAD algorithms.
---
paper_title: Reconfigurable computing: a survey of systems and software

paper_content:

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.
---
paper_title: Resource-aware run-time elaboration of behavioural FPGA specifications

paper_content:

The Circal process algebra is being used to explore the behavioural specification of systems that are mapped to field programmable logic circuits. In this paper we report on the implementation and performance of an interpreter for system specifications given in the Circal language. In contrast to the typical design flow for field programmable technology in which designs are statically partitioned, synthesised, and mapped to pre-allocated resources, in this system the specified circuits are extracted from behavioural specifications that are partitioned, elaborated, mapped, and configured at run time as control passes through them. We report on the details of a design that targets the Celoxica RC1000 co-processor and assess preliminary performance results for this implementation. The results clearly demonstrate our method is a practical approach to overcome resource constraints, particularly in applications where these change at run time. The results also establish a benchmark against which to measure future improvements and alternative methods.
---
paper_title: Power-aware RAM mapping for FPGA embedded memory blocks

paper_content:

Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance.
---
paper_title: A detailed power model for field-programmable gate arrays

paper_content:

Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.
---
paper_title: The Multiple Wordlength Paradigm

paper_content:

This paper presents a paradigm for the design of multiple wordlength parallel processing systems for DSP applications based on varying the wordlength and scaling of each signal in a DSP block diagram. A technique for estimating the observable effects of truncation and roundoff error is illustrated, and used to form the basis of an optimization algorithm to automate the design of such multiple wordlength systems. Results from implementation on a reconfigurable computing platform show that significant logic usage savings and increased clock rates can be obtained by customizing the datapath precision to the algorithm according to the techniques described in this paper. On selected DSP benchmarks, we obtain up to 45% area reduction and up to 39% speed increase over standard design techniques.
---
paper_title: Hardware-assisted fast routing

paper_content:

To fully realize the benefits of partial and rapid reconfiguration of field-programmable devices, we often need to dynamically schedule computing tasks and generate instance-specific configurations-new graphs which must be routed during program execution. Consequently, route time can be a significant overhead cost reducing the achievable net benefits of dynamic configuration generation. BY adding hardware to accelerate routing, we show that it is possible to compute routes in one thousandth the time of a traditional, software router and achieve routes that are within 5% of the state-of-the-art offline routing algorithms for a sample set of application netlists and within 25% for a set of difficult synthetic benchmarks. We further outline how strategic use of parallelism can allow the total route time to scale substantially less than linearly in graph size. We detail the source of the benefits in our approach and survey a range of options for hardware assistance that van, from a speedup of over 10/spl times/ with modest hardware overhead to speedups in excess of 1000/spl times/.
---
paper_title: The Chimaera reconfigurable functional unit

paper_content:

By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself with direct access to the host processor's register file, the system enables the creation of multi-operand instruction and a speculative execution model key to high performance, general-purpose reconfigurable computing. It also supports multi-output functions, and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, this system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.
---
paper_title: FELIX: using rewriting-logic for generating functionally equivalent implementations

paper_content:

FELIX is a new design space exploration tool and graphical integrated development environment (IDE) for the programming of coarse-grained reconfigurable architectures. Its main and novel advantage is the use of rewriting rules and logical strategies for the automated generation of alternative functionally equivalent implementations from a single mathematical specification. The user selection of the rewriting logic strategies to be applied determines the resulting implementations, making it possible to quickly generate, simulate and evaluate alternative implementations that are logically equivalent. The FELIX system includes an interface to the KressArray Xplorer for hardware design-space exploration. The current version of the tool is targeted for the pact extreme processing platform (XPP), with support for additional architectures planned in future versions.
---
paper_title: Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits

paper_content:

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components, called bit-slices, it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. This work describes such an FPGA logic block architecture, called a multi-bit logic block, which employs configuration memory sharing to exploit datapath regularity. It is experimentally shown that, comparing to conventional FPGA logic blocks, the multi-bit logic blocks can achieve 18% to 26% logic block area reduction for implementing datapath circuits, which represents an overall FPGA area saving of 5% to 13%. A packing algorithm for the multi-bit logic block architecture is also proposed in this paper; and it is used to empirically find the best values for several important architectural parameters of the new architecture, including the most area efficient granularity values and the most area efficient amount of configuration memory sharing.
---
paper_title: Hardware assisted two dimensional ultra fast placement

paper_content:

Summary form only given. Placement time is an overhead on the application execution time in an online placement system. In a partially reconfigurable system, the inherent parallelism of the reconfigurable hardware can be explored to speed up the placement process. We present three different architectures for two dimensional online placement. Each architecture makes different trade-offs between area usage, memory requirement and execution time. These architectures are capable of achieving very fast placement while using a very small number of hardware resources.
---
paper_title: Technology mapping for FPGAs with embedded memory blocks

paper_content:

Modern field programmable gate arrays (FPGAs) provide embedded memory blocks (EMBs) to be used as on-chip memories. In this paper, we explore the possibility of using EMBs to implement logic functions when they are not used as on-chip memory. We propose a general technology mapping problem for FPGAs with EMBs for area and delay minimization and develop an efficient algorithm based on the concepts of Maximum Fanout Free Cone (MFFC) [3] and Maximum Fanout Free Subgraph (MFFS) [7], named EMB_Pack, which minimizes the area after or before technology mapping by using EMBs while maintaining the circuit delay. We have tested EMB_Pack on MCNC benchmarks on Altera's FLEX10K device family [1]. The experimental results show that compared with the original mapped circuits generated from CutMap [5] without using EMBs, EMB_Pack as postprocessing can further reduce up to 10% of the area on the mapped circuits while maintaining the layout delay by making efficient use of available EMB resources. Compared with CutMap-e without using EMBs, EMB_Pack as pre-mapping processing followed by CutMap-e can reduce 6% of the area while maintaining the circuit optimal delay.
---
paper_title: Virtex-4 family overview

paper_content:

An apparatus for automatically controlling tunnel face hydraulic pressure in a hydraulic chamber defined by a rotary cutter head and bulkhead in a shield type excavator used in hydraulic tunnel boring system including a pipe for feeding a hydraulic material with a feeding pump from a reservoir to the chamber and a pipe for discharging a mixture of the fed hydraulic material with ground formations excavated by the cutter head from the chamber to the reservoir with a discharging pump. The apparatus substantially comprises a pressure gauge for measuring actual hydraulic pressure in the chamber, a pressure regulating valve in the feeding pipe as disposed close to the chamber, a first pressure regulator in which a predetermined feeding pressure is preset for comparing the actual pressure measured by the gauge with the predetermined feeding pressure and controllably operating the valve responsive to any difference between the pressures compared in the first regulator, and a second pressure regulator in which a predetermined pumping pressure is preset for comparing the actual pressure with the predetermined pumping pressure and controlling pumping rate of the feeding pump responsive to any difference between the pressures compared in the second regulator. The predetermined pumping pressure preset in the second regulator is preferrably made slightly higher than the predetermined feeding pressure preset in the first regulator.
---
paper_title: Hardware-assisted simulated annealing with application for fast FPGA placement

paper_content:

To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; late-bound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an FPGA LUT from a design netlist. We demonstrate that our technique approaches the same quality point as traditional simulated annealing as measured by a simple linear wirelength metric. Experimental results look ahead to compare quality against VPR's fast placer when considering the minimum channel width required to route as the primary optimization criteria. Preliminary results from an FPGA implementation show the feasibility of accelerating simulated annealing by three orders of magnitude using this approach. This means we can place the largest design in the University of Toronto's "FPGA Placement and Routing Challenge" in around 4ms.
---
paper_title: Combined word-length optimization and high-level synthesis of digital signal processing systems

paper_content:

Conventional approaches for fixed-point implementation of digital signal processing algorithms require the scaling and word-length (WL) optimization at the algorithm level and the high-level synthesis for functional unit sharing at the architecture level. However, the algorithm-level WL optimization has a few limitations because it can neither utilize the functional unit sharing information for signal grouping nor estimate the hardware cost for each operation accurately. In this study, we develop a combined WL optimization and high-level synthesis algorithm not only to minimize the hardware implementation cost, but also to reduce the optimization time significantly. This software initially finds the WL sensitivity or minimum WL of each signal throughout fixed-point simulations of a signal flow graph, performs the WL conscious high-level synthesis where signals having the similar WL sensitivity are assigned to the same functional unit, and then conducts the final WL optimization by iteratively modifying the WLs of the synthesized hardware model. A list-scheduling-based and an integer linear-programming-based algorithms are developed for the WL conscious high-level synthesis. The hardware cost function to minimize is generated by using a synthesized hardware model. Since fixed-point simulation is used to measure the performance, this method can be applied to general, including nonlinear and time-varying, digital signal processing systems. A fourth-order infinite-impulse response filter, a fifth-order elliptic filter, and a 12th-order adaptive least mean square filter are implemented using this software.
---
paper_title: Evaluation of low-leakage design techniques for field programmable gate arrays

paper_content:

In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15%-30%.
---
paper_title: An FPGA architecture with enhanced datapath functionality

paper_content:

Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems).We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standard-cell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priority.
---
paper_title: Energy-efficient signal processing using FPGAs

paper_content:

In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations and through low-level simulation. For FFT, our designs dissipated an average of 60% less energy than the design from the Xilinx library and 56% less than the DSP. Our designs showed a factor of 10 improvement over the embedded processor. These results provide concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that FPGAs can achieve this performance while still dissipating less energy than the other two types of devices.
---
paper_title: Data wordlength reduction for low-power signal processing software

paper_content:

Reducing power consumption prolongs battery life and increases integration. In digital CMOS designs, switching activity is closely connected with the total power consumption. Switching activity on programmable processors implementing linear filters, fast Fourier transforms, and other signal processing operations is dominated by the hardware multiplier. In this paper, we employ wordlength reduction of multiplicands to reduce switching activity in hardware multipliers using truncation and signed right shift methods. For 32 bit /spl times/ 32 bit Wallace and radix-4 modified Booth multipliers, truncation by 16 bits achieves a 4:1 and 2:1 reduction, respectively, in switching activity, whereas signed right shift gives little or no reduction. The key contribution of this paper is the reduction of power consumption by altering multiplicands in software without any hardware modifications.
---
paper_title: Placement and routing for non-rectangular embedded programmable logic cores in SoC design

paper_content:

As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after fabrication. In many cases, non-rectangular programmable logic cores are required, either to better mesh with the other IP cores, or because of I/O constraints. In order to use programmable logic cores, placement and routing algorithms are required to implement user circuits on the core. Existing placement and routing algorithms that target programmable logic were optimized for stand-alone FPGAs which are invariably square or rectangular. We show that these algorithms do not work well when targetting non-rectangular programmable logic cores, and we present enhancements to existing placement and routing algorithms that allow the algorithms to better target these cores. It is shown that the new algorithms lead to a 12% critical path improvement for "U"-shaped cores, and a 4% improvement for "O"-shaped cores. The density and speed penalty for using these non-rectangular cores is significant, compared to square cores, however, we show that the penalty would be significantly larger if the original algorithms were used.
---
paper_title: Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs

paper_content:

A new architecture is proposed for configurable blocks which can be used to dynamically construct multipliers. An array of these blocks is capable of being configured to perform any 8m by 8n bits signed/unsigned binary multiplication. The new design is based on the radix-4 overlapped multiple-bit scanning algorithm. This yields excellent multiplication times, at the same time allowing multiply accumulate (MAC) operations, without modification. The new design is compared to our previous scheme, and shown to be both faster and require fewer transistors.
---
paper_title: Architecture and CAD for Deep-Submicron FPGAs

paper_content:

From the Publisher: ::: Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes. Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert.
---
paper_title: Compiling run-time parametrisable designs

paper_content:

This paper explores representations and compilation of run-time parametrisable FPGA designs. We develop methods to produce designs with many run-time parameters, which would otherwise require an impractical number of bitstreams to be generated at compile time. Run-time parametrisation facilitates specialisation, which can be used to remove logic to produce a smaller and faster design. Our approach involves a source description based on Structural VHDL that allows designers to specify what parameters are available at compile time and at run time. Using this approach, converting a compile-time parameter into a run-time parameter or vice versa is straightforward. The source description does not contain explicit information on how to modify the design at run time. We describe a compilation scheme that can be used to extract this information, generate a run-time representation of the design and rapidly instantiate this representation at run time. We present techniques that allow a parametrised design to be incrementally modified in order to minimise the reconfiguration overhead Our compiler implementation generates a Java program that uses the JBits AN to implement the runtime representation and functions to incrementally modify the design. DES and AES encryption designs are used to illustrate our approach.
---
paper_title: Performance and area modeling of complete FPGA designs in the presence of loop transformations

paper_content:

Selecting which program transformations to apply when mapping computations to FPGA-based architectures leads to prohibitively long design exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to understand the impact and interaction of the transformations. In this paper we present a combined analytical performance and area modeling for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of these computations. Our preliminary results reveal that our modeling is very accurate allowing a compiler tool to quickly explore a very large design space resulting in the selection of a feasible high-performance design.
---
paper_title: Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture

paper_content:

Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.
---
paper_title: Interface synthesis using memory mapping for an FPGA platform

paper_content:

Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable coprocessor to reduce the computational load on the main processor core. We present an interface synthesis approach that forms part of our hardware-software codesign methodology for such an FPGA-based platform. The approach is based on a novel memory mapping algorithm that maps data used by both the hardware and the software to shared memories on the reconfigurable fabric. The memory mapping algorithm couples with a high-level synthesis tool and uses scheduling information to map variables, arrays and complex data structures to the shared memories in a way that minimizes the number of registers and multiplexers used in the hardware interface. We also present three software schemes that enable the application software to communicate with this hardware interface. We demonstrate the utility of our approach and study the trade-offs involved using a case study of the codesign of a computationally expensive portion of the MPEG-1 multimedia application on to the Altera Nios platform.
---
paper_title: Reconfigurable computing: architectures and design methods

paper_content:

Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.
---
paper_title: Reconfigurable computing: a survey of systems and software

paper_content:

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.
---
paper_title: Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

paper_content:

Coarse-grained reconfigurable architectures have seen growing importance recently. Design tools and methodology are essential to their success. Based on our previous work on modulo scheduling algorithms and a novel architecture with tightly coupled VLIW/reconfigurable matrix, we present a C-based design flow using an MPEG-2 decoder as a design example. The application is mapped to the architecture in less than one person-week starting from a software implementation. The kernel and overall speedup over the reference VLIW are 4.84 and 3.05 respectively. The case study shows that our methodology and architecture can deliver a competitive package in terms of design efforts and performance over other programmable architectures.
---
paper_title: The effect of reconfigurable units in superscalar processors

paper_content:

This paper describes OneChip, a third generation reconfigurable processor architecture that integrates a Reconfigurable Functional Unit (RFU) into a superscalar Reduced Instruction Set Computer (RISC) processor's pipeline. The architecture allows dynamic scheduling and dynamic reconfiguration. It also provides support for pre-loading configurations and for Least Recently Used (LRU) configuration management. ::: To evaluate the performance of the OneChip architecture, several off-the-shelf software applications were compiled and executed on Sim-OneChip, an architecture simulator for OneChip that includes a software environment for programming the system. The architecture is compared to a similar one but without dynamic scheduling and without an RFU. OneChip achieves a performance improvement and shows a speedup range from 2.16 up to 32 for the different applications and data sizes used. The results show that dynamic scheduling helps performance the most on average, and that the RFU will always improve performance the best when most of the execution is in the RFU.
---
paper_title: A high-performance microarchitecture with hardware-programmable functional units

paper_content:

This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC—a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language compilation techniques that are needed to successfully build PRISC and, we present performance results from a proof-of-concept study. With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor performance on the SPECint92 benchmarks.
---
paper_title: Totem: Custom Reconfigurable Array Generation

paper_content:

Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case, and miss optimization opportunities present if characteristics of the desired application set are known. We can therefore increase efficiency by restricting the structure to support a class or a specific set of algorithms, while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA. However, the manual creation of these customized reprogrammable architectures would be a labor-intensive process, leading to high design costs. Instead, we propose automatic reconfigurable architecture generation specialized to given application sets. The Totem custom reconfigurable array generator is our initial step in this direction.
---
paper_title: The Chimaera reconfigurable functional unit

paper_content:

By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself with direct access to the host processor's register file, the system enables the creation of multi-operand instruction and a speculative execution model key to high performance, general-purpose reconfigurable computing. It also supports multi-output functions, and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, this system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.
---
paper_title: OneChip: an FPGA processor with reconfigurable logic

paper_content:

This paper describes a processor architecture called OneChip, which combines a fixed-logic processor core with reconfigurable logic resources. Using the programmable components of this the performance of speed-critical can be improved by customizing OneChip's execution units, or flexibility can be added to the glue logic interfaces of embedded controller applications. OneChip eliminates the shortcomings of other custom compute machines by tightly integrating its reconfigurable resources into a MIPS-like processor. Speedups of close to 50 over strict software implementations on a MIPS R4400 are achievable for computing the DCT.
---
paper_title: The MOLEN processor prototype

paper_content:

We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyping platform. Experimental results prove the viability of the MOLEN concept. More precisely, the MPEG-2 application is accelerated very closely to its theoretical limits by implementing SAD, DCT and IDCT in reconfigurable hardware. The MPEG-2 encoder overall speedup is in the range between 2.80 and 2.96. The speedup of the MPEG-2 decoder varies between 1.56 and 1.63.
---
paper_title: Virtex-4 family overview

paper_content:

An apparatus for automatically controlling tunnel face hydraulic pressure in a hydraulic chamber defined by a rotary cutter head and bulkhead in a shield type excavator used in hydraulic tunnel boring system including a pipe for feeding a hydraulic material with a feeding pump from a reservoir to the chamber and a pipe for discharging a mixture of the fed hydraulic material with ground formations excavated by the cutter head from the chamber to the reservoir with a discharging pump. The apparatus substantially comprises a pressure gauge for measuring actual hydraulic pressure in the chamber, a pressure regulating valve in the feeding pipe as disposed close to the chamber, a first pressure regulator in which a predetermined feeding pressure is preset for comparing the actual pressure measured by the gauge with the predetermined feeding pressure and controllably operating the valve responsive to any difference between the pressures compared in the first regulator, and a second pressure regulator in which a predetermined pumping pressure is preset for comparing the actual pressure with the predetermined pumping pressure and controlling pumping rate of the feeding pump responsive to any difference between the pressures compared in the second regulator. The predetermined pumping pressure preset in the second regulator is preferrably made slightly higher than the predetermined feeding pressure preset in the first regulator.
---
paper_title: Heterogeneous reconfigurable systems

paper_content:

The continually increasing integration density of integrated circuits portrays important paradigm shifts in next-generation designs, especially in the direction of systems-on-a-chip. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. This opens the door for creative high-performance low-energy solutions to the programming problem using techniques such as reconfiguration to construct optimized architectures for a given computational problem. Exploiting the opportunities offered by these architectural innovations obviously requires a clear understanding of the trade-off's offered by the various architectural models and styles, as well as a well-thought out design methodology, combining high-level prediction and analysis tools with partitioning, optimization and mapping techniques. This paper presents an overview of opportunities of these reconfigurable architectures in the architecture domain.
---
paper_title: Trends in reconfigurable logic and reconfigurable computing

paper_content:

The paper gives a survey on reconfigurable logic and reconfigurable computing technologies, and on recent R&D trends in these areas. The paper also points out the weaker aspects of recent developments and proposes new directions to follow, driven by technology progress, a growing variety of reconfigurable platforms, and, innovations in EDA. Deep submicron technology allows SoC implementation, and the silicon IP business reduces entry barriers for newcomers and turns infrastructures of existing players into a liability.
---
paper_title: Using Reconfigurable Hardware to Speed up Product Development and Performance.

paper_content:

Harp1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware. It includes a transputer closely-coupled to a Field-Programmable Gate Array (FPGA). The whole system can be regarded as an instance of a process in the theory of Communicating Sequential Processes (CSP). The major elements themselves can also be viewed in the same way: both the transputer and the FPGA can implement many parallel communicating sub-processes. The Harp1 design includes memory banks, a programmable frequency synthesizer and several communication ports. The latter supports the use of parallel arrays of Harp1 boards, as well as interfacing to external hardware. Harp1 is the target of mathematical tools based upon the Ruby and occam languages, which enable unusual and novel applications to be produced and demonstrated correctly and rapidly; the aim is to produce high quality designs at low costs and with reduced development time.
---
paper_title: PipeRench: A virtualized programmable datapath in 0.18 micron technology

paper_content:

PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managed dynamic reconfiguration. This capability provides application portability and scalability without redesign or recompilation. This paper describes the implementation of PipeRench in a 0.18 micron process. The implementation has 3.65 million transistors and runs at 120 MHz. Performance is competitive with high-end commercial DSP architectures and more than five times faster than a commercial microprocessor. Executing at 33 MHz, an FIR filter without virtualization consumes 519 mW. When virtualization is required, the implementation consumes approximately 675 mW.
---
paper_title: A reconfigurable unit for a clustered programmable-reconfigurable processor

paper_content:

In a clustered programmable-reconfigurable processor, multiple programmable processors and blocks of reconfigurable logic communicate through a register-based communication mechanism, which reduces the impact of wire delay on clock cycle time. In this paper, we present a circuit-level design for the reconfigurable clusters used on the Amalgam programmable-reconfigurable processor. We outline our interleaved reconfigurable array design, which provides high bandwidth to and from the register file without requiring large amounts of register control logic. We characterize the latency of operations in our array, and present results that show the impact that this latency has on overall system performance in a range of fabrication processes. Finally, we present a pipelining scheme that enables the array to operate at clock rates closer to those of programmable processors and allows for better scaling in future technologies.
---
paper_title: Garp: a MIPS processor with a reconfigurable coprocessor

paper_content:

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.
---
paper_title: Reconfigurable data acquisition system for weather radar applications

paper_content:

Tornado, hazardous weather and flood detection radars demand high-throughput, high-speed data acquisition and processing. Weather-processing systems need to be capable of implementing powerful signal processing algorithms on the raw data collected by the radars. Following processing, data is distributed to the end-user in real-time for timely and accurate detection of imminent weather disasters. Since physical accessibility to such systems is often limited, remote-user based control and reconfiguration of processing capabilities are also essential. A real-time data acquisition, processing and distribution system for weather radar applications that meets these needs is described in this paper. This FPGA-based system has been successfully integrated with a radar optimized for tornado detection and deployed in the field
---
paper_title: Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification

paper_content:

This paper describes a real time vision system that allows us to localize faces in video sequences and verify their identity. These processes are image processing techniques based on the radial basis function (RBF) neural network approach. The robustness of this system has been evaluated quantitatively on eight video sequences. We have adapted our model for an application of face recognition using the Olivetti Research Laboratory (ORL), Cambridge, UK, database so as to compare the performance against other systems. We also describe three hardware implementations of our model on embedded systems based on the field programmable gate array (FPGA), zero instruction set computer (ZISC) chips, and digital signal processor (DSP) TMS320C62, respectively. We analyze the algorithm complexity and present results of hardware implementations in terms of the resources used and processing speed. The success rates of face tracking and identity verification are 92% (FPGA), 85% (ZISC), and 98.2% (DSP), respectively. For the three embedded systems, the processing speeds for images size of 288 /spl times/ 352 are 14 images/s, 25 images/s, and 4.8 images/s, respectively.
---
paper_title: Implementation of Multi-Standard Wireless Communication Receivers in a Heterogeneous Reconfigurable System-on-Chip

paper_content:

Future mobile terminals become multi-mode communication systems. In order to handle different standards, we propose to perform baseband processing in heterogeneous reconfigurable hardware. Not only the baseband processing but also error decoding differs for every communication system. We already proposed implementations of the baseband processing part of an OFDM receiver and a Wideband CDMA receiver in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. Now, we also implemented an adaptive Viterbi decoder in the same coarse-grained MONTIUM architecture. The rate, constraint length and decision depth of the decoder can be adjusted to different communication systems. We show that the flexibility in the coarse-grained reconfigurable architecture is more than 200 times as energy-efficient compared to a general purpose solution but only 24 times less efficient compared to a dedicated solution
---
paper_title: Hardware software tri-design of encryption for mobile communication units

paper_content:

We explore the design space of field programmable gate arrays (FPGAs), processors and ASICs-hardware-software tri-design-in the framework of encryption for hand-held communication units. The IDEA (International Data Encryption Algorithm) is used to show the tradeoffs for the suggested technologies. The measures for comparing different options are: performance, programmability and power (P/sup 3/). More specifically we use the performance to power, or operations to energy ratio MOPS/Watt and Mbits/s/Watt to compare processors, FPGAs and ASICs. We compare the latest digital signal processor (DSP) from Texas Instruments to Xilinx XC4000 series FPGAs. Many DSP-like applications perform very well on FPGAs. We show the benefits and limitations of FPGA technology for IDEA.
---
paper_title: A pipelined configurable gate array for embedded processors

paper_content:

In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μ m CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.
---
paper_title: Performance modeling of reconfigurable SoC architectures and energy-efficient mapping of a class of application

paper_content:

Reconfigurable system-on-chip (RSoC) devices are being used to implement many battery-operated systems, where energy efficiency is a major concern. RSoCs incorporate may different components, such as processor core, reconfigurable logic, memory, etc. various power management techniques can be applied to these components. Tasks within an application can be mapped onto different components for execution. The communication and reconfiguration costs incurred under different mappings significantly impact the overall system energy dissipation. In order to achieve energy-efficient designs on RSoCs, we develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient mapping problem for a class of applications, and (c) a dynamic programming algorithm that minimizes the system energy dissipation. We illustrate our approach by mapping two beamforming applications onto Xilinx Virtex-II Pro. For these two applications, our approach leads to an average 52% energy reduction over a greedy algorithm.
---
paper_title: Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

paper_content:

Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to effectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the pre-defined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the pre-designed dual-Vdd layout pattern introduces non-negligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs. To our best knowledge, it is the first in-depth study on applying both dual-Vdd and dual-Vt to FPGA considering circuits, fabrics and CAD algorithms.
---
paper_title: Energy-Efficiency of the Montium Reconfigurable Tile Processor

paper_content:

Primary requirements of wireless multimedia handheld computers are high-performance, flexibility, energy-efficiency and low costs. A compromise for these contradicting requirements can be found in a heterogeneous SoC. Besides conventional architectures such a SoC contains domain specific coarse grain reconfigurable processors and fine-grain reconfigurable entities. The MONTIUM is a prototype of a novel coarsegrain reconfigurable processor. The SoC template offers a balance between flexibility, efficiency and performance. In this paper the energy and performance characteristics of the MONTIUM are compared with the characteristics of other state-of-the-art (reconfigurable) architectures.
---
paper_title: Power-aware RAM mapping for FPGA embedded memory blocks

paper_content:

Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance.
---
paper_title: A detailed power model for field-programmable gate arrays

paper_content:

Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.
---
paper_title: Virtex-4 family overview

paper_content:

An apparatus for automatically controlling tunnel face hydraulic pressure in a hydraulic chamber defined by a rotary cutter head and bulkhead in a shield type excavator used in hydraulic tunnel boring system including a pipe for feeding a hydraulic material with a feeding pump from a reservoir to the chamber and a pipe for discharging a mixture of the fed hydraulic material with ground formations excavated by the cutter head from the chamber to the reservoir with a discharging pump. The apparatus substantially comprises a pressure gauge for measuring actual hydraulic pressure in the chamber, a pressure regulating valve in the feeding pipe as disposed close to the chamber, a first pressure regulator in which a predetermined feeding pressure is preset for comparing the actual pressure measured by the gauge with the predetermined feeding pressure and controllably operating the valve responsive to any difference between the pressures compared in the first regulator, and a second pressure regulator in which a predetermined pumping pressure is preset for comparing the actual pressure with the predetermined pumping pressure and controlling pumping rate of the feeding pump responsive to any difference between the pressures compared in the second regulator. The predetermined pumping pressure preset in the second regulator is preferrably made slightly higher than the predetermined feeding pressure preset in the first regulator.
---
paper_title: Evaluation of low-leakage design techniques for field programmable gate arrays

paper_content:

In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15%-30%.
---
paper_title: Energy-efficient signal processing using FPGAs

paper_content:

In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations and through low-level simulation. For FFT, our designs dissipated an average of 60% less energy than the design from the Xilinx library and 56% less than the DSP. Our designs showed a factor of 10 improvement over the embedded processor. These results provide concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that FPGAs can achieve this performance while still dissipating less energy than the other two types of devices.
---
paper_title: Evaluation of a Low-Power Reconfigurable DSP Architecture

paper_content:

Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.
---
paper_title: Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction

paper_content:

SRAM based FPGA are subjected to ion radiation in many operating environments. Following the current trend of shrinking device feature size & increasing die area, newer FPGA are more susceptible to radiation induced errors. Single event upsets (SEU), (also known as soft-errors) account for a considerable amount of radiation induced errors. SEU are difficult to detect & correct when they affect memory-elements present in the FPGA, which are used for the implementation of finite state machines (FSM). Conventional practice to improve FPGA design reliability in the presence of soft-errors is through configuration memory scrubbing, and through component redundancy. Configuration memory scrubbing, although suitable for combinatorial logic in an FPGA design, does not work for sequential blocks such as FSM. This is because the state-bits stored in flip-flops (FF) are variable, and change their value after each state transition. Component redundancy, which is also used to mitigate soft-errors, comes at the expense of significant area overhead, and increased power consumption compared to nonredundant designs. In this paper, we propose an alternate approach to implement the FSM using synchronous embedded memory blocks to enhance the runtime reliability without significant increase in power consumption. Experiments conducted on various benchmark FSM show that this approach has higher reliability, lower area overhead, and consumes less power compared to a component redundancy technique.
---
paper_title: Reconfigurable computing in space: from current technology to reconfigurable systems-on-a-chip

paper_content:

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based FPGAs make them very interesting for high-speed, on-orbit data processing, but, because the current generation of radiation-tolerant SRAM-based FPGAs are derived directly from COTS versions of the chips, several issues must be dealt with for space, including SEU sensitivities, power consumption, thermal problems, and support logic. This paper will discuss Los Alamos National Laboratory's approach to using the Xilinx XQVR1000 FPGAs for on-orbit processing in the Cibola Flight Experiment (CFE) as well as the possibilities and challenges of using newer, system-on-a-reprogrammable-chip FPGAs, such as Virtex I1 Pro, in space-based reconfigurable computing. The reconfigurable computing payload for CFE includes three processing boards, each having three radiation-tolerant Xilinx XQVRl 000 FPGAs. The reconfigurable computing architecture for this project is intended for in-flight, real-time processing of two radio fi-equency channels, each producing 12-bit samples at 100 million samples/second. In this system, SEU disruptions in data path operations can be tolerated while disruptions in the control path are much less tolerable. With this system in mind, LANL has developed an SEU management scheme with strategies for handling upsets in all of the FPGA resources known to be sensitive to radiation-induced SEUs. While mitigation schemes for many resources will be discussed, the paper will concentrate on SEU management strategies and tools developed at LANL for the configuration bitstream and 'half latches'. To understand the behavior of specific designs under SEUs in the configuration bitstream, LANL and Brigham Young University have developed an SEU simulator using ISI's SLAACl-V reconfigurable computing board. The simulator can inject single-bit upsets into a design's configuration bitstream to simulate SEUs and observe how these simulated SEUs affect the design's operation. Using fast partial configuration, the simulator can cover the entire bitstream of a Xilinx XQVRl 000 FPGA, which has 6 million configuration bits, in about 30 minutes. Instead of using a combination of TMR and configuration scrubbing for bitstream SEU mitigation, the approach developed for CFE uses minimal logic redundancy along with an SEU detection and correction scheme to handle bitstream SEUs. Though this approach allows some SEUs to affect less critical user logic, it requires considerably fewer FPGA resources than TMR and allows bitstream SEU rates to be monitored. 'Half latches', another class of SEU sensitive FPGA state elements, are used to provide logic constants in user FPGA designs but are not explicitly controlled by the configuration bitstream. Upsets in half latches cannot be detected by readback nor corrected via configuration repair or scrubbing - only a full reconfiguration can reliably restore their state. We have created a tool, called RadDRC, which can replace all critical half latches with more visible and correctable constant sources. Lastly, in looking forward, this paper will briefly consider the possible benefits and risks of using reconfigurable system-on-a-chip FPGAs, such as the Virtex II Pro, for reconfigurable computing in space. The paper concludes with a summary of challenges for using reconfigurable computing in space and a summary of future research at LANL in this area.
---
paper_title: Computing Requirements for Self-Repairing Space Systems

paper_content:

The United States recently announced ambitious plans for extended human and robotic exploration of the moon and mars. Coupled with efforts to complete the International Space Station, clearly mankind is destined to deploy increasingly more complex manned systems and for longer periods of time in Space. These systems, however, require fault-tolerant and highly adaptive real-time computer systems to control them. Fortunately, new technologies such as the field programmable gate array (FPGA) offer a flexible platform to develop robust, adaptable, self-repairing systems for space. But this new technology is itself vulnerable and therefore must be used with caution by augmenting existing practices with new techniques. The contribution of this paper is an overview and synthesis of recent developments in FPGA-based reconfigurable real-time system, and a discussion of reconfiguration issues in space applications. From these a system formalization, a proposed set of architectural and operating systems requirements, and suggestions for future work for FPGA-based self-repairing space systems are given.
---
paper_title: Yield enhancements of design-specific FPGAs

paper_content:

The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the development of Design-Specific FPGAs. These parts offer cost reductions by limiting manufacturing tests and improving the number of working devices in a wafer. This paper addresses the issue of yield enhancement in Design-Specific FPGAs. In this paper, an analytical model predicting the probability of mapping a specific design onto potentially defective FPGAs is developed. When combined with existing yield modelling techniques, a quantitative measure of the potential yield improvements of the Design-Specific FPGA approach is reported for current and future technology nodes. It is found that this approach, while beneficial with current manufacturing technology, may not be suitable for 22nm technology or beyond.
---
paper_title: Efficiently supporting fault-tolerance in FPGAs

paper_content:

While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of realiability with low timing and hardware overhead.
---
paper_title: RECASTER: synthesis of fault-tolerant embedded systems based on dynamically reconfigurable FPGAs

paper_content:

Summary form only given. We present a fault-tolerant embedded system design methodology that uses dynamically reconfigurable FPGAs as spares for several dedicated hardware components. The key advantage is the reduction of area or cost as compared to dedicated spares. During normal operation, each FPGA is dynamically reconfigured with system tasks and can replace any of them if a fault is detected. For a specified coverage, i.e., system tasks that might be affected by a single fault, our algorithm allocates a set of FPGAs and determines schedules, including task executions and FPGA reconfigurations, that provide the required redundancy while satisfying deadlines and minimizing either area or cost. For each task requiring simple redundancy, the algorithm also determines a schedule in which an FPGA replaces this task. Our experimental results indicate that, with a smaller area and cost, this collective redundancy based on dynamically reconfigurable FPGAs allows system recovery from a larger number of single faults, each affecting one task, as compared to the conventional spare approach.
---
paper_title: Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

paper_content:

Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.
---
paper_title: Soft error rate estimation and mitigation for SRAM-based FPGAs

paper_content:

FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods.In this paper, we present an analytical approach to estimate the failure rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than fault injection method while is very accurate. We also present a high-reliable low-cost mitigation technique which can significantly improve the availability of FPGA-based designs. This technique is able to tolerate SEUs in both user and configuration bits of mapped designs.
---
paper_title: Hardware support for dynamic Reconfiguration in reconfigurable SoC architectures

paper_content:

Dynamic reconfiguration of digital hardware enables systems to adapt to changing demands of the applications and of the environment. This paper concentrates on a core element of a reconfigurable hardware architecture, which supports a Real-time Operating System in reconfiguring the hardware – the Run-time Reconfiguration (RTR) Manager. The RTR-Manager has been developed to control, monitor and execute dynamic reconfiguration. It enables a fast adaptation of the SoC architecture through context switching between different configurations. Configuration code analysis and observation of the reconfiguration process guarantee a correct reconfiguration and increase the safety of the system. The system was successfully implemented and evaluated by means of the Rapid Prototyping System RAPTOR2000.
---
paper_title: Satisfying real-time constraints with custom instructions

paper_content:

Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).
---
paper_title: Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks

paper_content:

Today's reconfigurable hardware devices have huge densities and are partially reconfigurable, allowing for the configuration and execution of hardware tasks in a true multitasking manner. This makes reconfigurable platforms an ideal target for many modern embedded systems that combine high computation demands with dynamic task sets. A rather new line of research is engaged in the construction of operating systems for reconfigurable embedded platforms. Such an operating system provides a minimal programming model and a runtime system. The runtime system performs online task and resource management. In this paper, we first discuss design issues for reconfigurable hardware operating systems. Then, we focus on a runtime system for guarantee-based scheduling of hard real-time tasks. We formulate the scheduling problem for the 1D and 2D resource models and present two heuristics, the horizon and the stuffing technique, to tackle it. Simulation experiments conducted with synthetic workloads evaluate the performance and the runtime efficiency of the proposed schedulers. The scheduling performance for the 1D resource model is strongly dependent on the aspect ratios of the tasks. Compared to the 1D model, the 2D resource model is clearly superior. Finally, the runtime overhead of the scheduling algorithms is shown to be acceptably low.
---
paper_title: Periodic real-time scheduling for FPGA computers

paper_content:

Todays reconfigurable hardware devices, such as FPGAs, have high densities and allow for the execution of several hardware tasks in parallel. This paper deals with scheduling periodic real-time tasks to such an architecture, a problem which has not been considered before. We formalize the real-time scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known earliest deadline first (EDF) technique to the FPGA execution model. The algorithm reveals good scheduling performance; task sets with system utilizations of up to 85% can be feasibly scheduled. However, the EDF approach is practical only for a small number of tasks, since there is no efficient schedulability test. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method can only feasibly schedule task sets with a system utilization of up to some 50%, it is applicable to large tasks sets as the schedulability test runs in polynomial time. Equally important, the method requires only a small number of FPGA configurations which directly translates into reduced memory requirements.
---
paper_title: Exploring the design space of LUT-based transparent accelerators

paper_content:

Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. With instruction set customization, specialized accelerators are added to a conventional processor to atomically execute dataflow subgraphs. Accelerators that are exploited without explicit changes to the instruction set architecture of the processor are said to be transparent. Transparent acceleration relies on a light-weight hardware engine to dynamically generate control signals for the accelerator, using subgraphs delineated by a compiler. The design of transparent subgraph accelerators is challenging, as critical subgraphs need to be supported efficiently while maintaining area and timing constraints. Additionally, more complex accelerators require more sophisticated control generation engines. These factors must be carefully balanced. In this work, we investigate the design of subgraph accelerators using configurable lookup table structures. These designs provide an effective paradigm to execute a wide range of subgraphs involving arithmetic and logic operations. We describe why lookup table designs are effective, how they fit into a transparent acceleration framework, and evaluate the effectiveness of a wide range of de-signs using both simulation and logic synthesis.
---
paper_title: Instruction generation and regularity extraction for reconfigurable processors

paper_content:

The increasing demand for complex and specialized embedded hardware must be met by processors which are optimized for performance, yet are also extremely flexible. In our work, we explore the tradeoff between flexibility and performance in the domain of reconfigurable processor design. Specifically, we seek to identify regularly occurring, computation-heavy patterns in an application or set of applications. These patterns become candidates for hard-logic implementation, potentially embedded in the flexible reconfigurable fabric as special optimized instructions. In this work we present an extension to previous work in instruction generation: an algorithm that identifies parallel templates. We discuss the advantages of parallel templates, and prove the correctness of our algorithm. We introduce an All-Pairs Common Slack Graph (APCSG) as an effective tool for parallel template generation. Finally, we demonstrate the effectiveness of our algorithm on several applicationse dataflow graphs, reducing latency on average by 51.98%, without unreasonably increasing chip area.
---
paper_title: Exploring RTOS issues with a high-level model of a reconfigurable SoC platform

paper_content:

Reconfigurable resources are more and more envisaged inside System-on-Chip designs for facing with embedded computing power constraints. Moreover, a high level of flexibility of such platforms is required and can only be achieved with embedded software and real-time operating systems (RTOS) services. Unfortunately, this leads to very complex and heterogeneous platforms that cannot be easily validated nor modeled with classical design tools. This paper presents the objective and the proposed methodology of the OVERSOC project. This project aims at developing a global methodology and the associated tools for a design space exploration of interactions between embedded real-time operating systems and reconfigurable SoC platforms.
---
paper_title: Dynamically configurable security for SRAM FPGA bitstreams

paper_content:

FPGAs are becoming increasingly attractive – thanks to the improvement of their capacities and their performances. Today, FPGAs represent an efficient design solution for numerous systems. Moreover, since FPGAs are important for the electronics industry, it becomes necessary to improve their security, particularly for SRAM FPGAs, since they are more vulnerable than other FPGA technologies. This paper proposes a solution to improve the security of SRAM FPGAs through flexible bitstream encryption. This proposition is distinct from other works because it uses the latest capabilities of SRAM FPGAs like partial dynamic reconfiguration and self-reconfiguration. It does not need an external battery to store the secret key. It opens a new way of application partitioning oriented by the security policy.
---
paper_title: Secure configuration of Field Programmable Gate arrays

paper_content:

Although SRAM programmed Field Programmable Gate Arrays (FPGA's) have come to dominate the industry due to their density and performance advantages over non-volatile technologies they have a serious weakness in that they are vulnerable to piracy and reverse engineering of the user design. This is becoming increasingly important as the size of chips - and hence the value of customer designs - increases. FPGA's are now being used in consumer products where piracy is more common. Further, reconfiguration of FPGA's in the field is becoming increasingly popular particularly in networking applications and it is vital to provide security against malicious parties interfering with equipment functionality through this mechanism.
---
paper_title: Fast Template Placement for Reconfigurable Computing Systems

paper_content:

This article presents fast online placement methods for dynamically reconfigurable systems, as well as offline 3D placement algorithms for statically reconfigurable architectures.
---
paper_title: DPGA utilization and application

paper_content:

Dynamically Programmable Gate Arrays (DPGAs) are programmable arrays which allow the strategic reuse of limited resources. In so doing, DPGAs promise greater capacity, and in some cases higher performance, than conventional programmable device architectures where all array resources are dedicated to a single function for an entire operational epoch. This paper examines several usage patterns for DPGAs including temporal pipelining, utility functions, multiple function accommodation, and state-dependent logic. In the process, it offers insight into the application and technology space where DPGA-style reuse techniques are most beneficial.
---
paper_title: Configuration relocation and defragmentation for run-time reconfigurable computing

paper_content:

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. By mapping the compute-intensive sections of an application to reconfigurable hardware, custom computing systems exhibit significant speedups over traditional microprocessors. However, this potential acceleration is limited by the requirement that the speedups provided must outweigh the considerable cost of reconfiguration. The ability to relocate and defragment configurations on field programmable gate arrays (FPGAs) can dramatically decrease the overall reconfiguration overhead incurred by the use of the reconfigurable hardware. We therefore present hardware solutions to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA, as well as software algorithms for controlling this hardware. This results in factors of 8 to 12 improvement in the configuration overheads displayed by traditional serially programmed FPGAs.
---
paper_title: Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation

paper_content:

One of the major overheads for reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedup possible in this paradigm. In this paper we explore configuration prefetching techniques for reducing this overhead. By overlapping the configuration loadings with the computation on the host processor the reconfiguration overhead can be reduced. Our prefetching techniques target to the reconfigurable systems containing a Partial Reconfigurable FPGA with Relocation + Defragmentation (R+D model) since the R+D FPGA showed high hardware utilization. We have investigated various techniques including static configuration prefetching, dynamic configuration pre-fetching, and hybrid prefetching. We have developed prefetching algorithms that significantly reduce the reconfiguration overhead.
---
paper_title: Resource-aware run-time elaboration of behavioural FPGA specifications

paper_content:

The Circal process algebra is being used to explore the behavioural specification of systems that are mapped to field programmable logic circuits. In this paper we report on the implementation and performance of an interpreter for system specifications given in the Circal language. In contrast to the typical design flow for field programmable technology in which designs are statically partitioned, synthesised, and mapped to pre-allocated resources, in this system the specified circuits are extracted from behavioural specifications that are partitioned, elaborated, mapped, and configured at run time as control passes through them. We report on the details of a design that targets the Celoxica RC1000 co-processor and assess preliminary performance results for this implementation. The results clearly demonstrate our method is a practical approach to overcome resource constraints, particularly in applications where these change at run time. The results also establish a benchmark against which to measure future improvements and alternative methods.
---
paper_title: The NAPA adaptive processing architecture

paper_content:

The National Adaptive Processing Architecture (NAPA) is a major effort to integrate the resources needed to develop teraops class computing systems based on the principles of adaptive computing. The primary goals for this effort include: (1) the development of an example NAPA component which achieves an order of magnitude cost/performance improvement compared to traditional FPGA based systems, (2) the creation of a rich but effective application development environment for NAPA systems based on the ideas of compile time functional partitioning and (3) significantly improve the base infrastructure for effective research in reconfigurable computing. This paper emphasizes the technical aspects of the architecture to achieve the first goal while illustrating key architectural concepts motivated by the second and third goals.
---
paper_title: Hardware support for dynamic Reconfiguration in reconfigurable SoC architectures

paper_content:

Dynamic reconfiguration of digital hardware enables systems to adapt to changing demands of the applications and of the environment. This paper concentrates on a core element of a reconfigurable hardware architecture, which supports a Real-time Operating System in reconfiguring the hardware – the Run-time Reconfiguration (RTR) Manager. The RTR-Manager has been developed to control, monitor and execute dynamic reconfiguration. It enables a fast adaptation of the SoC architecture through context switching between different configurations. Configuration code analysis and observation of the reconfiguration process guarantee a correct reconfiguration and increase the safety of the system. The system was successfully implemented and evaluated by means of the Rapid Prototyping System RAPTOR2000.
---
paper_title: A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning

paper_content:

In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.
---
paper_title: The Chimaera reconfigurable functional unit

paper_content:

By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself with direct access to the host processor's register file, the system enables the creation of multi-operand instruction and a speculative execution model key to high performance, general-purpose reconfigurable computing. It also supports multi-output functions, and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, this system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.
---
paper_title: Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems

paper_content:

The need for flexible computational power has motivated many researchers to incorporate run-time reconfigurable logic into their architectures. Most contemporary experiments include commercial FPGA’s serving as reconfigurable hardware. Unfortunately, the FPGA does not exhibit the same run-time flexibility as the Instruction Set Processor (ISP) e.g. when it comes to ease and speed of setting up a task. In addition, FPGA’s tend to be less suited than traditional ISP’s to accommodate control-flow dominated tasks. Obviously, it is possible to alleviate some of these issues by using a reconfiguration hierarchy (e.g. placing and configuring an ASIP or coarse grain reconfigurable block into the FPGA). This paper illustrates how our operating system transparently manages the complexity of hierarchical reconfiguration. In addition, this paper highlights the benefits and drawbacks of employing multiple hierarchical levels of configuration. As a proof of concept, we developed a filtering application on top of an in-house 16 bit microcontroller and a parameterizable filter block, both instantiated inside an FPGA.
---
paper_title: On the placement and granularity of FPGA configurations

paper_content:

Dynamic FPGA reconfiguration represents an overhead that can be critical to the performance of a realised circuit. To address this problem, This work presents a technique that is applicable at the times of loading the configuration data on the device. The technique involves reusing the on-chip configuration fragments to implement the next configuration thereby reducing the amount of data that must be externally transferred to the configuration memory. This work provides an analysis of the effect of circuit placement and configuration granularity on configuration reuse. The problem of finding placements of each circuit in a sequence of circuits so as to maximize configuration re-use is considered in detail. A greedy solution to this NP complete problem was found to reduce configuration overheads by less than 5% for a benchmark set. The effect of configuration granularity on configuration reuse was also considered and it was found that reducing the size of the unit of configuration allowed us to reduce the size of the benchmark configurations by 41%.
---
paper_title: Configuration Caching Techniques for FPGA

paper_content:

Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of hardware configuration. In this paper, we explore the idea of configuration caching. We present techniques to carefully manage the configurations present on the reconfigurable hardware throughout program execution. Through the use of the presented strategies, we show that the number of required reconfigurations is reduced, lowering the configuration overhead. We extend these techniques to a number of different FPGA programming models, and develop both lower bound and realistic caching algorithms for these structures.
---
paper_title: Hardware/software codesign: a systematic approach targeting data-intensive applications

paper_content:

This article presents a systematic approach to hardware/software codesign targeting data-intensive applications. It focuses on the application processes that can be represented in directed acrylic graphs (DAGs) and use a synchronous dataflow (SDF) model, the popular form of dataflow employed in DSP systems when running the process. The codesign system is based on the ultrasonic reconfigurable platform, a system designed jointly at Imperial College and the SONY Broadcast Laboratory. This system is modeled as a loosely coupled structure consisting of a single instruction processor and multiple reconfigurable hardware elements. The paper also introduces and demonstrates a task-based hardware/software codesign environment specialized for real-time video applications. Both the automated partitioning and scheduling environment and the task manager program help to provide a fast robust for supporting demanding applications in the codesign system.
---
paper_title: The swappable logic unit: a paradigm for virtual hardware

paper_content:

Swappable Logic Units (SLUs) were introduced by the author previously (1996) to play a role in virtual hardware subsystems that is analogous to the role of pages or segments in virtual memory subsystems. The intention is that a conventional operating system can be extended to manage SLU circuitry implemented using FPGA real estate. In order to minimise operating system overheads, two particular SLU-based virtual hardware models were deemed practical: a "sea of accelerators" model and a "parallel harness" model. This paper looks in some detail at how SLUs will fit within the overall environment of a fairly conventional hardware/software system. First, there is a discussion of the FPGA-based hardware environment for SLUs, followed by a discussion of the software environment from which SLUs might be used. After this, there is a description of the operational properties that SLUs can have, and how these fit in with the two virtual hardware models. Finally, proposals for standard interfaces between SLUs and their environment are discussed. These interfaces can be regarded as constraints on the designers of SLU circuitry or, more positively, as suppliers of an enriched context within which such circuitry operates. The overall impact of the work presented in the paper is to show that it is feasible to incorporate configurable hardware within traditional computer systems that use high-level language programs and computer operating systems. That is, it should not always be necessary to devise special-purpose hardware/software systems to realise custom computing.
---
paper_title: Resource estimation and task scheduling for multithreaded reconfigurable architectures

paper_content:

Reconfigurable computing is an emerging paradigm of research that offers cost-effective solutions for computationally intensive applications through hardware reuse. There is a growing need in this domain for techniques to exploit parallelism inherent in the target application and to schedule the parallelized application. This paper proposes a method to estimate the optimal number of resources through critical path analysis while keeping resource utilization near optimal. We also propose an algorithm to optimally schedule the parallel threads of execution in linear time. Our algorithm is based on the idea of enhanced partial critical path (ePCP) and handles memory latencies and reconfiguration overheads. Results obtained show the effectiveness of our approach over other critical path based methods.
---
paper_title: Task scheduling for heterogeneous reconfigurable computers

paper_content:

We consider the problem of executing a dynamically changing set of tasks on a reconfigurable system, made upon a processor and a reconfigurable device. Task execution on such a platform is managed by a scheduler that can allocate tasks either to the processor or to the reconfigurable device. The scheduler can be seen as part of an operating system running on the software or as core in the reconfigurable device. For each tasks to be executed on reconfigurable device, an equivalent implementation exists as rectangular block in a database. This block has to be placed on the device at run-time. A placer is responsible for the placement of tasks received from the scheduler on the reconfigurable device. However, the placement of tasks on the reconfigurable device cannot be successful if enough space is not available on the device to hold the task. In this case, the scheduler receive an acknowledgment from the placer and decide either to preempt a running task or to run the task on software. We present in this work an implementation of a placer module as well as investigations on task preemption. The two modules are part of an operating system for reconfigurable system currently under development.
---
paper_title: Kernel scheduling in reconfigurable computing

paper_content:

Reconfigurable computing is a flexible way of facing with a single device a wide range of applications with a good level of performance. This area of computing involves different issues and concepts when compared with conventional computing systems. One of these concepts is context lending. The context refers to the coded configuration information to implement a particular circuit behaviour. An important problem for reconfigurable computing is the scheduling of a group of kernels (sub-tasks) that constitute a complex application for minimum execution time. In this paper, we show how the different execution orders for these sub-tasks may result in varying levels of performance. We formulate an analytical approach and present a solution for this new problem through this work.
---
paper_title: A Streaming Multi-Threaded Model

paper_content:

We present SCORE (Stream Computations Organized for Reconfigurable Execution), a multi-threaded model that relies on streams to expose thread parallelism and to enable efficient scheduling, low-overhead communication, and scalability. We present work to-date on SCORE for scalable reconfigurable logic, as well as implementation ideas for SCORE for processor architectures. We demonstrate that streams can be exposed as a clean architectural feature that supports forward compatibility to larger, more parallel hardware.
---
paper_title: A Virtual Hardware Operating System for the Xilinx XC6200

paper_content:

Computer operating systems relieve a user of the responsibility for managing physical resources, such as processors, memory and input/output devices. The evolution of FPGA technology means that a new resource is available — it is accessed like memory, but can behave like a flexible processor or input/output device. There is a role for an operating system in making this resource easy to use, by managing it on behalf of a user. This paper explores the issues involved in such management, in particular the problems involved in presenting a software-oriented user with a larger virtual hardware resource that is implemented using smaller physical FPGA hardware. A prototype operating system, that demonstrates operational solutions to the problems using the Xilinx XC6200 FPGA, is described.
---
paper_title: Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks

paper_content:

Today's reconfigurable hardware devices have huge densities and are partially reconfigurable, allowing for the configuration and execution of hardware tasks in a true multitasking manner. This makes reconfigurable platforms an ideal target for many modern embedded systems that combine high computation demands with dynamic task sets. A rather new line of research is engaged in the construction of operating systems for reconfigurable embedded platforms. Such an operating system provides a minimal programming model and a runtime system. The runtime system performs online task and resource management. In this paper, we first discuss design issues for reconfigurable hardware operating systems. Then, we focus on a runtime system for guarantee-based scheduling of hard real-time tasks. We formulate the scheduling problem for the 1D and 2D resource models and present two heuristics, the horizon and the stuffing technique, to tackle it. Simulation experiments conducted with synthetic workloads evaluate the performance and the runtime efficiency of the proposed schedulers. The scheduling performance for the 1D resource model is strongly dependent on the aspect ratios of the tasks. Compared to the 1D model, the 2D resource model is clearly superior. Finally, the runtime overhead of the scheduling algorithms is shown to be acceptably low.
---
paper_title: An execution environment for reconfigurable computing

paper_content:

Although many studies have demonstrated the benefits of reconfigurable computing, it has not yet penetrated the mainstream. One of the biggest unsolved problems is the management of the reconfigurable hardware in a multi-threaded environment. Most research in reconfigurable computing has assumed a single-threaded model, but this is unrealistic for personal computing and many types of embedded computing. In these cases, there may be several different threads or processes running simultaneously, each wishing to use the reconfigurable hardware. The operating system must decide how to allocate the hardware at run-time based on the status of the system. The system status could also influence the choice of different implementations for each circuit based on area/speed tradeoffs. This paper examines reconfigurable computing as it could be used in mainstream systems, focusing on a proposed scheduling algorithm to allocate the reconfigurable hardware. Our initial tests indicate that reconfigurable computing with our scheduler can easily achieve at least a 20% system-level speedup.
---
paper_title: Multitasking on FPGA Coprocessors

paper_content:

Multitasking on an FPGA-based processor is one possibility to explore the efficacy of reconfigurable computing. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture allows investigating the problems of implementing realistic multitasking. This paper explores the control software required to support task switching for an application split over the host processor - coprocessor boundary as well as the requirements and features of context saving and restoring in the FPGA coprocessor context. An FPGA coprocessor designed especially to support multitasking of such applications is described.
---
paper_title: Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine

paper_content:

The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition of a computation abstracted from the detailed size of the physical hardware. When the number of physical compute pages is smaller than the number of virtual compute pages in the abstract computation graph, the design is time-multiplexed onto the available physical hardware. A key component of this strategy is an automatic scheduler that selects the temporal sequencing of virtual resources onto the physical device. We describe a quasi-static scheduling strategy that retains the full semantic power of the dynamic SCORE flow graph while taking advantage of static scheduling techniques at program load time to hoist most of the computational work out of the inner scheduling loops. This strategy reduces online scheduling work per reconfiguration epoch by an order of magnitude. In addition, a more global perspective available from offline-scheduling improves schedule quality, resulting in a net reduction of total execution time by 46--81%.
---
paper_title: Dynamic hardware/software partitioning: a first approach

paper_content:

Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded systems. Meanwhile, dynamic software optimization methods have shown the usefulness and feasibility of runtime program optimization, but those optimizations do not achieve as much as partitioning. We introduce a first approach to dynamic hardware/software partitioning. We describe our system architecture and initial on-chip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic partitioning of real benchmarks. We show speedups averaging 2.6 for five benchmarks taken from Powerstone, NetBench, and our own benchmarks.
---
paper_title: Configuration Compression for Virtex FPGAs

paper_content:

Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of configuration of the hardware. Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the compute power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. In this paper, we explore the idea of configuration compression and develop algorithms for reconfigurable systems. These algorithms, targeted to Xilinx Virtex series FPGAs with minimum modification of hardware, can significantly reduce the amount of data needed to transfer during configuration. In this work we have extensively researched the current compression techniques, including the Huffman coding, the Arithmetic coding and LZ coding. We have also developed different algorithms targeting different hardware structures. Our readback algorithm allows certain frames to be reused as a dictionary and sufficiently utilize the regularities within the configuration bitstream. In addition, we have developed frame reordering techniques that better uses the regularities by shuffling the sequence of the configuration. We have also developed the wildcard approach that can be used for true partial reconfiguration. The simulation results demonstrate that a factor of 4 compression ratio can be achieved.
---
paper_title: Dynamic Scheduling of Tasks on Partially Reconfigurable FPGAs

paper_content:

Field-programmable gate arrays (FPGAs) which allow partial reconfiguration at run time can be shared among multiple independent tasks. When the sequence of tasks to be performed is unpredictable, the FPGA controller needs to make allocation decisions online. Since online allocation suffers from fragmentation, tasks can end up waiting despite there being sufficient, albeit noncontiguous, resources available to service them. The time to complete tasks is consequently longer and the utilisation of the FPGA is lower than it could be. It is proposed that a subset of the tasks executing on the FPGA be rearranged when to do so allows the next pending task to be processed sooner. Methods are described and evaluated for overcoming the NP-hard problems of identifying feasible rearrangements and scheduling the rearrangements when moving tasks are reloaded from off-chip.
---
paper_title: Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling

paper_content:

Dynamic scheduling for system-on-chip (SoC) platforms has become an important field of research due to the emerging range of applications with dynamic behavior (e.g., MPEG-4). Dynamically reconfigurable architectures are an interesting solution for this type of applications. Scheduling for dynamically reconfigurable architectures might be classified in two major broad categories: (1) static scheduling techniques or (2) use of an operating system (OS) for reconfigurable computing. However, research efforts demonstrate a trend to move tasks traditionally assigned to the OS into hardware (thus increasing performance and reducing power).In this paper, we introduce a methodology for dynamically reconfigurable architectures. The dynamic scheduling of tasks to several reconfigurable units is performed by a hardware-based multitasking support unit. Two different versions of the microarchitecture are possible (with or without a hardware configuration prefetch unit). The dynamic scheduling algorithms are also explained. Both algorithms try to minimize the reconfiguration overhead by overlapping the execution of tasks with device reconfigurations.An exhaustive study (using the developed simulation and performance analysis framework) of this novel proposal is presented, and the effect of the microarchitecture parameters has been studied. Results demonstrate the benefits of our approach (achieving similar performance to a static configuration solution but using half of the resources). The hardware configuration prefetch unit is useful (i.e., minimize the execution time) in applications with low level of parallelism.
---
paper_title: PipeRench: A virtualized programmable datapath in 0.18 micron technology

paper_content:

PipeRench is a programmable datapath that can be used to accelerate numerically intensive applications. The unique aspect of PipeRench is its ability to virtualize hardware through self-managed dynamic reconfiguration. This capability provides application portability and scalability without redesign or recompilation. This paper describes the implementation of PipeRench in a 0.18 micron process. The implementation has 3.65 million transistors and runs at 120 MHz. Performance is competitive with high-end commercial DSP architectures and more than five times faster than a commercial microprocessor. Executing at 33 MHz, an FIR filter without virtualization consumes 519 mW. When virtualization is required, the implementation consumes approximately 675 mW.
---
paper_title: Temporal partitioning and scheduling data flow graphs for reconfigurable computers

paper_content:

FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of S/sub RPU/ and a computational task represented by an acyclic data flow graph G=(V, E). Computations with logic area requirements that exceed S/sub RPU/ cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a temporal partitioning of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a k-way partitioning of G=(V, E) such that each partitioned segment will not exceed S/sub RPU/ in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in {s/sub 1/,s/sub 2/,...,s/sub k/}, scheduling assigns a unique ordering S/sub i/-j,1/spl les/i/spl les/k,1/spl les/j/spl les/k, such that the computation would execute in proper sequential order as defined by the flow graph G=(V, E).
---
paper_title: Garp: a MIPS processor with a reconfigurable coprocessor

paper_content:

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.
---
paper_title: Runtime assignment of reconfigurable hardware components for image processing pipelines

paper_content:

The combination of hardware acceleration and flexibility make FPGAs (field programmable gate arrays) important to image processing applications. There is also a need for efficient, flexible hardware/software codesign environments that can balance the benefits and costs of using FPGAs. Image processing applications often consist of pipeline of components where each component applies a different processing algorithm. Components can be implemented for FPGAs or software. Such systems enable an image analyst to work with either FPGA or software implementations of image processing algorithms for a given problem. The pipeline assignment problem chooses from alternative implementations of pipeline components to yield the fastest pipeline. Our codesign system solves the pipeline assignment problem to provide the most effective implementation automatically, so the image analyst can focus solely on choosing components, which make up the pipeline. However, the pipeline assignment problem is NP complete. An efficient, dynamic solution to the pipeline assignment problem is a desirable enabler of codesign systems which use both FPGA and software implementations. This paper is concerned with solving pipeline assignment in this context. Consequently, we focus on optimal and heuristic methods for fast (fixed time limit) runtime pipeline assignment are investigated. We present experimental finding for pipelines of twenty or fewer components, which show that in our environment, optimal runtime solutions are possible for smaller pipelines and nearly optimal heuristic solutions are possible for larger pipelines.
---
paper_title: Automatic task scheduling/loop unrolling using dedicated RTR controllers in coarse grain reconfigurable architectures

paper_content:

When designing a SoC, matching the required performance both in terms of processing power and power consumption tends to become more and more challenging. Moreover, since the range of targeted applications for every single product is growing rapidly, employing reconfigurable accelerators makes more and more sense to this purpose. Coarse grain reconfigurable architectures bring an alternative providing interesting performance/flexibility trade-offs over traditional approaches. This paper presents an original method allowing to efficiently exploit dynamical parallelism at both loop-level and task-level, which remains rarely used. This method called DHM (dynamic hardware multiplexing) is based upon the use of a hardwired controller dedicated to run-time task scheduling and automatic loop unrolling. This paper shows that significant performance improvements can be achieved through combining both intra and inter-task parallelism. Principles and validations are exposed through a case study on a coarse grain reconfigurable architecture.
---
paper_title: Compiling run-time parametrisable designs

paper_content:

This paper explores representations and compilation of run-time parametrisable FPGA designs. We develop methods to produce designs with many run-time parameters, which would otherwise require an impractical number of bitstreams to be generated at compile time. Run-time parametrisation facilitates specialisation, which can be used to remove logic to produce a smaller and faster design. Our approach involves a source description based on Structural VHDL that allows designers to specify what parameters are available at compile time and at run time. Using this approach, converting a compile-time parameter into a run-time parameter or vice versa is straightforward. The source description does not contain explicit information on how to modify the design at run time. We describe a compilation scheme that can be used to extract this information, generate a run-time representation of the design and rapidly instantiate this representation at run time. We present techniques that allow a parametrised design to be incrementally modified in order to minimise the reconfiguration overhead Our compiler implementation generates a Java program that uses the JBits AN to implement the runtime representation and functions to incrementally modify the design. DES and AES encryption designs are used to illustrate our approach.
---
paper_title: Context saving and restoring for multitasking in reconfigurable systems

paper_content:

Today's Field Programmable Gate Arrays (FPGAs) can be reconfigured partially, which makes it possible to share resources between various functional modules (hardware tasks) over time. This concept is well known in the area of conventional operating systems. However, in order to transfer resource sharing concepts to operating systems on FPGAs, several underlying mechanisms have to be developed. One of these mechanisms is to suspend hardware tasks and restart them at another time and/or another area of the FPGA. Addressing this problem, this paper discusses ways to save and restore the state information of a hardware task. Afterwards, an implementation of a state relocation mechanisms is presented that uses the standard configuration port. In contrast to similar approaches, we significantly reduce the amount of readback data by reading only those configuration frames that contain state information. We finally determine the time overhead for task relocation, which is essential for most multitasking concepts, like defragmentation.
---
paper_title: Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading

paper_content:

While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability is now required. Two dominant configurable hardware platforms are processors and FPGAs. However, for compute-intensive applications, neither platform delivers the needed performance at the desired low power. The need thus arises for custom, application-specific configurable (ASC) hardware. This paper addresses the optimization of ASC hardware. Our target application areas are multimedia and communication where an incoming packet (task) is processed independently of other packets. We innovatively utilize two concepts: external profiling and hardware threading. We utilize an M/M/c queueing model to profile task arrival patterns and show how profiling guides design decisions. We introduce the novel concept of hardware threading which allows on-the-fly borrowing of unutilized hardware, thus maximizing task-level parallelism, to either boost performance or to lower power consumption. We present a scheduling algorithm that synthesizes a hardware-threaded architecture, and discuss experimental results that illustrate adaptability to different workloads, and performance/power trade-offs.
---
paper_title: Interface synthesis using memory mapping for an FPGA platform

paper_content:

Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable coprocessor to reduce the computational load on the main processor core. We present an interface synthesis approach that forms part of our hardware-software codesign methodology for such an FPGA-based platform. The approach is based on a novel memory mapping algorithm that maps data used by both the hardware and the software to shared memories on the reconfigurable fabric. The memory mapping algorithm couples with a high-level synthesis tool and uses scheduling information to map variables, arrays and complex data structures to the shared memories in a way that minimizes the number of registers and multiplexers used in the hardware interface. We also present three software schemes that enable the application software to communicate with this hardware interface. We demonstrate the utility of our approach and study the trade-offs involved using a case study of the codesign of a computationally expensive portion of the MPEG-1 multimedia application on to the Altera Nios platform.
---
paper_title: Stream-oriented FPGA computing in the Streams-C high level language

paper_content:

Stream oriented processing is an important methodology used in FPGA-based parallel processing. Characteristics of stream-oriented computing include high-data-rate flow of one or more data sources; fixed size, small stream payload (one byte to one word); compute-intensive operations, usually low precision fixed point, on the data stream; access to small local memories holding coefficients and other constants; and occasional synchronization between computational phases. We describe language constructs, compiler technology, and hardware/software libraries embodying the Streams-C system which has been developed to support stream-oriented computation on FPGA-based parallel computers. The language is implemented as a small set of library functions callable from a C language program. The Streams-C compiler synthesizes hardware circuits for multiple FPGAs as well as a multi-threaded software program for the control processor. Our system includes a functional simulation environment based on POSIX threads, allowing the programmer to simulate the collection of parallel processes and their communication at the functional level. Finally we present an application written both in Streams-C and hand-coded in VHDL. Compared to the hand-crafted design, the Streams-C-generated circuit takes 3x the area and runs at 1/2 the clock rate. In terms of time to market, the hand-done design took a month to develop by an experienced hardware developer. The Streams-C design rook a couple of days, for a productivity increase of 10x.
---
paper_title: Design patterns for reconfigurable computing

paper_content:

It is valuable to identify and catalog design patterns for reconfigurable computing. These design patterns are canonical solutions to common and recurring design challenges which arise in reconfigurable systems and applications. The catalog can form the basis for creating designs, for educating new designers, for understanding the needs of tools and languages, and for discussing reconfigurable design. Tying application and implementation lessons to the expansion and refinement of this catalog make those lessons more relevant to the design community. In this paper, we articulate this role for design patterns in reconfigurable computing, provide a few example patterns, offer a starting point for the contents of the catalog, and discuss the potential benefits of this effort.
---
paper_title: Programming models for hybrid CPU/FPGA chips

paper_content:

Designers of embedded and real-time systems are continually challenged to meet tighter system requirements at better price-performance ratios. Best-practice methods have long promoted the use of commercial-off-the-shelf components to reduce design costs and time to market, but creating COTS components that are reusable in a wide range of applications remains difficult. In part, the challenge lies in satisfying the contradictory design forces of generalization and specialization. Systems designers are all too familiar with the tension these opposing forces cause in trying to balance cost versus performance. Adopting COTS components reduces costs and time to market but often fails to meet the most demanding performance requirements; custom-designed components can achieve significantly higher performance but at greater development costs and longer times to market. Emerging hybrid chips containing both CPU and field-programmable gate array (FPGA) components are an exciting new development. They promise COTS economies of scale while also supporting significant hardware customization. Components that combine a CPU and reconfigurable logic gates need a programming model that abstracts the computational hardware.
---
paper_title: A data-flow oriented co-design for reconfigurable systems

paper_content:

Multi FPGA systems are mainly composed of programmable logic devices and external memory. Up to date FPGAs also contain embedded static RAMs, which have shorter access time than the external SRAMs. The paper presents a dataflow oriented algorithm that makes use of the small embedded memories as local caches for data processing. The algorithm offers a high level of parallelism and efficient use of processing resources. This is done in the context of hardware-software co-design. The objective is to automatically implement parts of C code requiring high processing rates on a reconfigurable system. An example of implementation on a 400 Kgates 8 Mbytes multi FPGA system is described.
---
paper_title: Dynamic interconnection of reconfigurable modules on reconfigurable devices

paper_content:

This article presents two approaches to solving the problem of communication between components dynamically placed at runtime on a reconfigurable device. The first is a circuit-routing approach designed for existing FPGAs. This approach uses the reconfigurable multiple bus (RMB). The second, network-based approach targets devices with unlimited reconfiguration capability such as coarse-grained reconfigurable devices. We introduce the dynamic network on chip (DyNoC) as a viable communication infrastructure for communication on dynamically reconfigurable devices. For prototyping the DyNoC on FPGAs, we design and implement an unrestricted communication model for a columnwise-reconfigurable chip. For the DyNoC, as well as for the RMB on chip (RMBoC), we provide algorithms and implementation results from real-life problems.
---
paper_title: Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation

paper_content:

The range of distributed real-time and embedded (DRE) system applications has continued to expand at a vigorous rate. Designers of DRE systems are constantly challenged to provide new capabilities to meet expanding requirements and increased computational needs, while under pressure to provide constantly improving price/performance ratios and shorter times to market. Recently emerging hybrid chips containing both CPUs and FPGA components have the potential to enjoy significant economies of scale, while enabling system designers to include a significant amount of specialization within the FPGA component. However, realizing the promise of these new hybrid CPU/FPGA chips will require programming models supporting a far more integrated view of CPU and FPGA based application components than that provided by current methods. This paper describes methods we are developing for supporting a multithreaded programming model providing strongly integrated interface to CPU and FPGA based component threads.
---
paper_title: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

paper_content:

Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability. Such architectures impose strict placement constraints that lead to implementation infeasibility of even optimal scheduling formulations that ignore the nature of these constraints. We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. With our exact formulation, we prove the critical nature of placement constraints. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and a popular, but placement-uanaware scheduling heuristic for larger tests. With a case study, we demonstrate extension of our approach to handle heterogenous architectures with specialized resources distributed between general purpose programmable logic columns. The execution time of our heuristic is very reasonable- task graphs with hundreds of nodes are processed in a couple of minutes.
---
paper_title: Hardware/software codesign: a systematic approach targeting data-intensive applications

paper_content:

This article presents a systematic approach to hardware/software codesign targeting data-intensive applications. It focuses on the application processes that can be represented in directed acrylic graphs (DAGs) and use a synchronous dataflow (SDF) model, the popular form of dataflow employed in DSP systems when running the process. The codesign system is based on the ultrasonic reconfigurable platform, a system designed jointly at Imperial College and the SONY Broadcast Laboratory. This system is modeled as a loosely coupled structure consisting of a single instruction processor and multiple reconfigurable hardware elements. The paper also introduces and demonstrates a task-based hardware/software codesign environment specialized for real-time video applications. Both the automated partitioning and scheduling environment and the task manager program help to provide a fast robust for supporting demanding applications in the codesign system.
---
paper_title: Hardware synthesis from C/C++ models

paper_content:

Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of flexibility and fast simulation of models described with programming languages. At the same time, the mismatch (of software languages) in expressing power (for hardware systems) has caused several difficulties. In the recent past, novel approaches have helped in reducing the semantic gap, and in easing the creation of design flows that support system-level specifications in C/C++.
---
paper_title: On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures

paper_content:

Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration capabilities, provides an attractive solution to save silicon area. Architectural synthesis for dynamically reconfigurable FPGA-based digital systems needs to consider the case of reducing the number of temporal partitions (reconfigurations) by enabling sharing of some functional units in the same temporal partition. This paper proposes a novel algorithm for automated datapath design from behavioral input descriptions (represented by an acyclic dataflow graph), which simultaneously performs temporal partitioning and sharing of functional units. The proposed algorithm attempts to minimize both the number of temporal partitions and the execution latency of the generated solution. Temporal partitioning, resource sharing, scheduling, and a simple form of allocation and binding are all integrated in a single task. The algorithm is based on heuristics and on a new concept of construction by gradually enlarging timing slots. Results show the efficiency and effectiveness of the algorithm when compared to existent approaches.
---
paper_title: A Streaming Multi-Threaded Model

paper_content:

We present SCORE (Stream Computations Organized for Reconfigurable Execution), a multi-threaded model that relies on streams to expose thread parallelism and to enable efficient scheduling, low-overhead communication, and scalability. We present work to-date on SCORE for scalable reconfigurable logic, as well as implementation ideas for SCORE for processor architectures. We demonstrate that streams can be exposed as a clean architectural feature that supports forward compatibility to larger, more parallel hardware.
---
paper_title: Developing and debugging FPGA applications in hardware with JHDL

paper_content:

JHDL is a Java-based suite of design tools developed at Brigham Young University to aid in the design and development of high-performance FPGA applications. The suite consists of a set of JHDL circuit libraries, simulator, schematic generator, hardware debugger and other tools that can be used to design, develop and debug designs. JHDL is a unique design tool that unifies simulation and hardware execution into a single environment. Designers can easily select either simulation or execution and all of the circuit verification and visualization tools are fully usable whether in simulation or hardware execution mode. Because of its unified simulation/execution design environment, JHDL is the first tool that directly supports symbolic debugging of a user design in the original design context while the design is actually executing in FPGA hardware. JHDL allows designers to exploit the immediate availability of FPGA hardware making it possible to test and symbolically debug designs at hardware speeds that run several orders of magnitude faster than simulation. JHDL also supports end-to-end application development of the user circuitry including any control code and any user interface software including graphical user interfaces (GUIs). User circuitry is designed using JHDL libraries while control software and user interface software is written using standard Java libraries such as Swing, for example. This paper gives an overview of the JHDL tool suite and presents a tutorial on JHDL syntax.
---
paper_title: Extended genetic algorithm for codesign optimization of DSP systems in FPGAs

paper_content:

The multiobjective genetic algorithm is an effective solution to the complex problem of hardware-software codesign. An extended genetic algorithm (EGA) has been developed that implements a novel selection method with function scaling, adaptive crossover and mutation. This EGA is applied in a codesign optimization stage for dataflow oriented applications and synthesis on field-programmable gate arrays (FPGAs). Its effectiveness is illustrated on the problem of codesign of a self-tuning regulator considering area and performance.
---
paper_title: An Automated Process for Compiling Dataflow Graphs into Reconfigurable Hardware

paper_content:

We describe a system, developed as part of the Cameron project, which compiles programs written in a single-assignment subset of C called SA-C into dataflow graphs and then into VHDL. The primary application domain is image processing. The system consists of an optimizing compiler which produces dataflow graphs and a dataflow graph to VHDL translator. The method used for the translation is described here, along with some results on an application. The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, thereby extending the realm of hardware design to the application programmer.
---
paper_title: The Codesign of Embedded Systems: A Unified Hardware/Software Representation

paper_content:

Current practice dictates the separation of the hardware and software development paths early in the design cycle. These paths remain independent with very little interaction occurring between them until system integration. In particular, hardware is often specified without fully appreciating the computational requirements of the software. Also, software development does not influence hardware development and does not track changes made during the hardware design phase. Thus, the ability to explore hardware/software tradeoffs is restricted, such as the movement of functionality from the software domain to the hardware domain (and vice-versa) or the modification of the hardware/software interface. As a result, problems that are encountered during system integration may require modification of the software and/or hardware, resulting in potentially significant cost increases and schedule overruns. To address the problems described above, a cooperative design approach, one that utilizes a unified view of hardware and software, is described. This approach is called hardware/software codesign. The Codesign of Embedded Systems develops several fundamental hardware/software codesign concepts and a methodology that supports them. A unified representation, referred to as a decomposition graph, is presented which can be used to describe hardware or software using either functional abstractions or data abstractions. Using a unified representation based on functional abstractions, an abstract hardware/software model has been implemented in a common simulation environment called ADEPT (Advanced Design Environment Prototyping Tool). This model permits early hardware/software evaluation and tradeoff exploration. Techniques have been developed which support the identification of software bottlenecks and the evaluation of design alternatives with respect to multiple metrics. The application of the model is demonstrated on several examples. A unified representation based on data abstractions is also explored. This work leads to investigations regarding the application of object-oriented techniques to hardware design. The Codesign of Embedded Systems: A Unified Hardware/Software Representation describes a novel approach to a topic of immense importance to CAD researchers and designers alike.
---
paper_title: DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

paper_content:

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare dataflow for scheduling. Architecture abstraction generates an internal graph representation from a concrete architecture description. A modulo scheduling algorithm is key to exploit parallelism and achieve high performance. The experimental results show up to 28.7 instructions per cycle (IPC) over tested kernels.
---
paper_title: Temporal partitioning and scheduling data flow graphs for reconfigurable computers

paper_content:

FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of S/sub RPU/ and a computational task represented by an acyclic data flow graph G=(V, E). Computations with logic area requirements that exceed S/sub RPU/ cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a temporal partitioning of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a k-way partitioning of G=(V, E) such that each partitioned segment will not exceed S/sub RPU/ in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in {s/sub 1/,s/sub 2/,...,s/sub k/}, scheduling assigns a unique ordering S/sub i/-j,1/spl les/i/spl les/k,1/spl les/j/spl les/k, such that the computation would execute in proper sequential order as defined by the flow graph G=(V, E).
---
paper_title: Very Large Scale Spatial Computing

paper_content:

The early decades of computing were marked by limited resources. However, as we enter the twenty-first century, silicon is offering enormous computing resources on a single die and molecular-scale devices appear plausible offering a path to even greater capacities. Exploiting the capacities of these modern and future devices demands different computational models and radical shifts in the way we organize, capture, and optimize computations. A key shift is towardspatially organized computation. A natural consequence is that the dominant effects which govern our computing space change from the total number of operations and temporal locality to interconnect complexity andspatial locality. Old computational models which hide, ignore, or obfuscate communication andemphasize temporal sequences inhibit the exploitation of these modern capacities, motivating the needfor new models which make communication andspatial organization more apparent.
---
paper_title: An automated exploration framework for FPGA-based soft multiprocessor systems

paper_content:

FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA. The multiprocessor can be customized for a target application to achieve high performance. Modern FPGAs provide the capacity to build a variety of micro-architectures composed of 20-50 processors, complex memory hierarchies, heterogeneous interconnection schemes and custom co-processors for performance critical operations. However, the diversity in the architectural design space makes it difficult to realize the performance potential of these systems. In this paper we develop an exploration framework to build efficient FPGA multiprocessors for a target application. Our main contribution is a tool based on Integer Linear Programming to explore micro-architectures and allocate application tasks to maximize throughput. Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.
---
paper_title: Application-specific customization of soft processor microarchitecture

paper_content:

A key advantage of soft processors (processors built on an FPGA programmable fabric) over hard processors is that they can be customized to suit an application program's specific software. This notion has been exploited in the past principally through the use of application-specific instructions. While commercial soft processors are now widely deployed, they are available in only a few microarchitectural variations. In this work we explore the advantage of tuning the processor's microarchitecture to specific software applications, and show that there are significant advantages in doing so.Using an infrastructure for automatically generating soft processors that span the area/speed design space (while remaining competitive with Altera's Nios II variations), we explore the impact of tuning several aspects of microarchitecture including: (i) hardware vs software multiplication support; (ii) shifter implementation; and (iii) pipeline depth, organization, and forwarding. We find that the processor design that is fastest overall (on average across our embedded benchmark applications) is often also the fastest design for an individual application. However, in terms of area efficiency (i.e., performance-per-area), we demonstrate that a tuned microarchitecture can offer up to 30% improvement for three of the benchmarks and on average 11.4% improvement over the fastest-on-average design. We also show that our benchmark applications use only 50% of the available instructions on average, and that a processor customized to support only that subset of the ISA for a specific application can on average offer 25% savings in both area and energy. Finally, when both techniques for customization are combined we obtain an average improvement in performance-per-area of 25%.
---
paper_title: Exploring the design space of LUT-based transparent accelerators

paper_content:

Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. With instruction set customization, specialized accelerators are added to a conventional processor to atomically execute dataflow subgraphs. Accelerators that are exploited without explicit changes to the instruction set architecture of the processor are said to be transparent. Transparent acceleration relies on a light-weight hardware engine to dynamically generate control signals for the accelerator, using subgraphs delineated by a compiler. The design of transparent subgraph accelerators is challenging, as critical subgraphs need to be supported efficiently while maintaining area and timing constraints. Additionally, more complex accelerators require more sophisticated control generation engines. These factors must be carefully balanced. In this work, we investigate the design of subgraph accelerators using configurable lookup table structures. These designs provide an effective paradigm to execute a wide range of subgraphs involving arithmetic and logic operations. We describe why lookup table designs are effective, how they fit into a transparent acceleration framework, and evaluate the effectiveness of a wide range of de-signs using both simulation and logic synthesis.
---
paper_title: Instruction generation and regularity extraction for reconfigurable processors

paper_content:

The increasing demand for complex and specialized embedded hardware must be met by processors which are optimized for performance, yet are also extremely flexible. In our work, we explore the tradeoff between flexibility and performance in the domain of reconfigurable processor design. Specifically, we seek to identify regularly occurring, computation-heavy patterns in an application or set of applications. These patterns become candidates for hard-logic implementation, potentially embedded in the flexible reconfigurable fabric as special optimized instructions. In this work we present an extension to previous work in instruction generation: an algorithm that identifies parallel templates. We discuss the advantages of parallel templates, and prove the correctness of our algorithm. We introduce an All-Pairs Common Slack Graph (APCSG) as an effective tool for parallel template generation. Finally, we demonstrate the effectiveness of our algorithm on several applicationse dataflow graphs, reducing latency on average by 51.98%, without unreasonably increasing chip area.
---
paper_title: Xtensa: A Configurable and Extensible Processor

paper_content:

System designers can optimize Xtensa for their embedded application by sizing and selecting features and adding new instructions. Xtensa provides an integrated solution that allows easy customization of both hardware and software. This process is simple, fast, and robust.
---
paper_title: Sequential synthesizable embedded programmable logic cores for system-on-chip

paper_content:

Previous work has suggested that "soft" synthesizable programmable logic cores can efficiently provide small amounts of post-fabrication flexibility to integrated circuits. Previous architectures restrict the circuitry assigned to the core to be combinational. We present two methods to enhance these architectures to support sequential logic. We apply these methods to a previously developed fabric, and optimize and compare them. We also describe a proof-of-concept chip employing one of our techniques.
---
paper_title: Design, layout and verification of an FPGA using automated tools

paper_content:

Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately 50 to 200 person years from architecture definition to tape-out for a new FPGA family. Such a lengthy development time is necessary because the process is primarily done manually. Simplifying and shortening the design process would be advantageous since it could reduce the time to market for new FPGAs while also enhancing architecture explorations. One way to accomplish this is through automation and, in this paper, we describe our efforts to automate the entire process by making use of a previously developed set of tools that assist in the creation of the repeatable FPGA tile [25]. Our aim is to demonstrate the feasibility of a CAD flow that uses an input FPGA architecture description to generate a layout that can be sent for fabrication. We prove the feasibility of this proposition by actually designing and fabricating a complete FPGA. Initial functional testing of the FPGA appears promising but is inconclusive at this time. Through this architecture to layout process, we investigate the issues that are faced in the architecture selection, circuit design, layout and verification of such an automatically produced FPGA. We found that there are significant savings in design time. As well, we demonstrate that we can produce a layout using automated tools that is only 36% larger than a commercial FPGA device layout. Given the significant time savings and the relatively minor area penalty, we feel that this work demonstrates that automated layout of FPGAs is practical and advantageous.
---
paper_title: Architectures and algorithms for synthesizable embedded programmable logic cores

paper_content:

As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a "hard" layout. In this paper, we focus on an alternative approach: vendors supply a synthesizable version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC. For very small amounts of logic, this ease of use may be more important than the increased overhead. This paper presents two synthesizable programmable logic core architectures, describes the associated place and route CAD tools, and compares the two architectures to each other, and to a "hard" programmable logic core. It also shows how these cores can be made more efficient by creating a non-rectangular architecture, an option not available to "hard" core vendors.
---

Title: An Overview of Reconfigurable Hardware in Embedded Systems

Section 1: Introduction
Description 1: Provide a brief introduction to reconfigurable hardware (RH) and its relevance in embedded systems.

Section 2: Applications of Reconfigurable Hardware
Description 2: Discuss the various applications of RH in embedded systems, such as software-defined radio, medical imaging, networking, encryption, scientific data acquisition and analysis, spacecraft, robotics, automotive, and image/video processing.

Section 3: Reconfigurable Logic Design
Description 3: Explore the architectural aspects of RH, detailing different design structures and their suitability for embedded systems.

Section 4: System-Level Integration
Description 4: Examine how RH is integrated at the system level within embedded systems, discussing different coupling styles and example systems.

Section 5: Important Design Issues
Description 5: Address critical design considerations, including low-power operation, fault tolerance, and real-time support, and their relevance to RH in embedded systems.

Section 6: Configuration Overhead
Description 6: Discuss the challenges and strategies for managing configuration overhead in reconfigurable computing.

Section 7: Design Tools
Description 7: Highlight the tools available to assist in the design of reconfigurable embedded systems and applications.

Section 8: Future Directions
Description 8: Present future challenges and potential research directions in the field of reconfigurable hardware for embedded systems.

Section 9: Conclusion
Description 9: Summarize the key points discussed in the paper and the benefits of using RH in embedded system design.