A Survey of Network-On-Chip Tools
---
paper_title: Survey of Network on Chip (NoC) Architectures & Contributions

paper_content:

Multiprocessor architectures and platforms have been introduced to extend the applicability of Moore’s law. They depend on concurrency and synchronization in both software and hardware to enhance the design productivity and system performance. These platforms will also have to incorporate highly scalable, reusable, predictable, cost- and energy-efficient architectures. With the rapidly approaching billion transistors era, some of the main problems in deep sub-micron technologies which are characterized by gate lengths in the range of 60-90 nm, will arise from non-scalable wire delays, errors in signal integrity and unsynchronized communications. These problems may be overcome by the use of Network on Chip (NOC) architecture. In this paper, we have summarized over sixty research papers and contributions in NOC area.
---
paper_title: Survey of Network-on-chip Proposals

paper_content:

New substituted urea compounds of formula I, or a pharmaceutically acceptable salt thereof: I wherein A is wherein R3 is an oxadiazol, substituted with C1-8-alkyl, C2-8-alkenyl, C2-8 alkynyl, C3-7 cycloalkyl, benzyl, phenyl, C1-6-alkoxy, C1-6-alkylthio, amino or alkylamino; R2 is -H or lower alkyl; X is O or S; and R1 is a group of formula II, III, IV or V II III IV where n is 2 or 3, p is 1 or 2, q is 1 to 3, r is 1-3 and R4 and R5 are H, C1-7 alkyl or C3-6 cycloalkyl; and N-oxides thereof. The compounds are useful in pharmaceutical preparations for treating psychotic disorders, nausea and vomiting.
---
paper_title: Thousand core chips: a technology perspective

paper_content:

This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.
---
paper_title: On network-on-chip comparison

paper_content:

This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are currently evaluated, and shows which aspects have been covered and those needing more research effort. No single article can cover all the aspects, and therefore, possibility to compare results from various sources must be ensured by proper scientific reporting. Basic guidelines for achieving that are given.
---
paper_title: An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

paper_content:

This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8 x 10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a bisection bandwidth of 2 Terabits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm 2 custom design contains 100 M transistors. The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of bench-marks while dissipating 97 W at 4.27 GHz and 1.07 V supply.
---
paper_title: A survey of research and practices of Network-on-chip

paper_content:

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
---
paper_title: Survey of Network-on-chip Proposals

paper_content:

New substituted urea compounds of formula I, or a pharmaceutically acceptable salt thereof: I wherein A is wherein R3 is an oxadiazol, substituted with C1-8-alkyl, C2-8-alkenyl, C2-8 alkynyl, C3-7 cycloalkyl, benzyl, phenyl, C1-6-alkoxy, C1-6-alkylthio, amino or alkylamino; R2 is -H or lower alkyl; X is O or S; and R1 is a group of formula II, III, IV or V II III IV where n is 2 or 3, p is 1 or 2, q is 1 to 3, r is 1-3 and R4 and R5 are H, C1-7 alkyl or C3-6 cycloalkyl; and N-oxides thereof. The compounds are useful in pharmaceutical preparations for treating psychotic disorders, nausea and vomiting.
---
paper_title: Networks on Chips: from research to products

paper_content:

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
---
paper_title: Impact of virtual channels and adaptive routing on application performance

paper_content:

Research on multiprocessor interconnection networks has primarily focused on wormhole switching, virtual channel flow control, and routing algorithms to enhance their performance. The rationale behind this research is that by alleviating the network latency for high network loads, the overall system performance would improve. Many studies have used synthetic workloads to support this claim. However, such workloads may not necessarily capture the behavior of real applications. In this paper, we have used parallel applications for a closer examination of the network behavior. In particular, the performance benefit from enhancing a 2D mesh with virtual channels (VCs) and a fully adaptive routing algorithm is examined with a set of shared-memory and message passing applications. Execution time and average message latency of shared memory applications are measured using execution-driven simulation and by varying many architectural attributes that affect the network workload. The communication traces of message passing applications, collected on an IBM-SP2, are used to run a trace-driven simulation of the mesh architecture to obtain message latency. Simulation results show that VCs and adaptive routing can reduce the network latency to varying degrees depending on the application. However, these modest benefits do not translate to significant improvements in the overall execution time because the load on the network is not high enough to exploit the advantages of the network enhancements. Moreover, this benefit may be negated if the architectural enhancements increase the network cycle time. Rather, emphasis should be placed on improving the raw network bandwidth and faster network interfaces. Index Terms—Adaptive routing, architectural simulation, interconnection network, mesh network, performance evaluation, virtual channels. E
---
paper_title: A generic architecture for on-chip packet-switched interconnections

paper_content:

This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not meet the performance requirements of tomorrow's systems. We present an alternative interconnection in the form of switching networks. This technology originates in parallel computing, but is also well suited for heterogeneous communication between embedded processors and addresses many of the deep submicron integration issues. We discuss the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services. Eventually we present our first results on the cost/performance assessment of an integrated switching network.
---
paper_title: A survey of research and practices of Network-on-chip

paper_content:

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
---
paper_title: Survey of Network-on-chip Proposals

paper_content:

New substituted urea compounds of formula I, or a pharmaceutically acceptable salt thereof: I wherein A is wherein R3 is an oxadiazol, substituted with C1-8-alkyl, C2-8-alkenyl, C2-8 alkynyl, C3-7 cycloalkyl, benzyl, phenyl, C1-6-alkoxy, C1-6-alkylthio, amino or alkylamino; R2 is -H or lower alkyl; X is O or S; and R1 is a group of formula II, III, IV or V II III IV where n is 2 or 3, p is 1 or 2, q is 1 to 3, r is 1-3 and R4 and R5 are H, C1-7 alkyl or C3-6 cycloalkyl; and N-oxides thereof. The compounds are useful in pharmaceutical preparations for treating psychotic disorders, nausea and vomiting.
---
paper_title: Networks on Chips: from research to products

paper_content:

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
---
paper_title: Survey of Network on Chip (NoC) Architectures & Contributions

paper_content:

Multiprocessor architectures and platforms have been introduced to extend the applicability of Moore’s law. They depend on concurrency and synchronization in both software and hardware to enhance the design productivity and system performance. These platforms will also have to incorporate highly scalable, reusable, predictable, cost- and energy-efficient architectures. With the rapidly approaching billion transistors era, some of the main problems in deep sub-micron technologies which are characterized by gate lengths in the range of 60-90 nm, will arise from non-scalable wire delays, errors in signal integrity and unsynchronized communications. These problems may be overcome by the use of Network on Chip (NOC) architecture. In this paper, we have summarized over sixty research papers and contributions in NOC area.
---
paper_title: Survey of Network-on-chip Proposals

paper_content:

New substituted urea compounds of formula I, or a pharmaceutically acceptable salt thereof: I wherein A is wherein R3 is an oxadiazol, substituted with C1-8-alkyl, C2-8-alkenyl, C2-8 alkynyl, C3-7 cycloalkyl, benzyl, phenyl, C1-6-alkoxy, C1-6-alkylthio, amino or alkylamino; R2 is -H or lower alkyl; X is O or S; and R1 is a group of formula II, III, IV or V II III IV where n is 2 or 3, p is 1 or 2, q is 1 to 3, r is 1-3 and R4 and R5 are H, C1-7 alkyl or C3-6 cycloalkyl; and N-oxides thereof. The compounds are useful in pharmaceutical preparations for treating psychotic disorders, nausea and vomiting.
---
paper_title: Networks on Chips: from research to products

paper_content:

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
---
paper_title: On network-on-chip comparison

paper_content:

This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are currently evaluated, and shows which aspects have been covered and those needing more research effort. No single article can cover all the aspects, and therefore, possibility to compare results from various sources must be ensured by proper scientific reporting. Basic guidelines for achieving that are given.
---
paper_title: A survey of research and practices of Network-on-chip

paper_content:

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
---
paper_title: AEthereal network on chip: concepts, architectures, and implementations

paper_content:

The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best-effort services.
---
paper_title: The aethereal network on chip after ten years: goals, evolution, lessons, and future

paper_content:

The goals for the AEthereal network on silicon, as it was then called, were set in 2000 and its concepts were defined early 2001. Ten years on, what has been achieved? Did we meet the goals, and what is left of the concepts? In this paper we answer those questions, and evaluate different implementations, based on a new performance: cost analysis. We discuss and reflect on our experiences, and conclude with open issues and future directions.
---
paper_title: A generic architecture for on-chip packet-switched interconnections

paper_content:

This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not meet the performance requirements of tomorrow's systems. We present an alternative interconnection in the form of switching networks. This technology originates in parallel computing, but is also well suited for heterogeneous communication between embedded processors and addresses many of the deep submicron integration issues. We discuss the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services. Eventually we present our first results on the cost/performance assessment of an integrated switching network.
---
paper_title: QNoC: QoS architecture and design process for network on chip

paper_content:

We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process. SoC inter-module communication traffic is classified into four classes of service: signaling (for inter-module control signals); real-time (representing delay-constrained bit streams); RD/WR (modeling short data access) and block-transfer (handling large data bursts). Communication traffic of the target SoC is analyzed (by means of analytic calculations and simulations), and QoS requirements (delay and throughput) for each service class are derived. A customized Quality-of-Service NoC (QNoC) architecture is derived by modifying a generic network architecture. The customization process minimizes the network cost (in area and power) while maintaining the required QoS.The generic network is based on a two-dimensional planar mesh and fixed shortest path (X-Y based) multiclass wormhole routing. Once communication requirements of the target SoC are identified, the network is customized as follows: The SoC modules are placed so as to minimize spatial traffic density, unnecessary mesh links and switching nodes are removed, and bandwidth is allocated to the remaining links and switches according to their relative load so that link utilization is balanced. The result is a low cost customized QNoC for the target SoC which guarantees that QoS requirements are met.
---
paper_title: Thousand core chips: a technology perspective

paper_content:

This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.
---
paper_title: Networks on Chips: from research to products

paper_content:

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
---
paper_title: Networks-on-Chips: Theory and Practice

paper_content:

This book addresses many challenging topics related to the NoC research area. It starts by studying 3D NoC architectures and progresses to a discussion of NoC resource allocation, processor traffic modeling, and formal verification. NoC protocols are examined at different layers of abstraction. Also, several emerging research issues in NoC are highlighted in this book, such as NoC Quality of Service (QoS), testing and verification methodologies, NoC security requirements, and real-time monitoring. The book also tackles power and energy issues in NoC-based designs, as power constraints are currently considered among the bottlenecks that limit embedding more processing elements on a single chip.
---
paper_title: An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

paper_content:

This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8 x 10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a bisection bandwidth of 2 Terabits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm 2 custom design contains 100 M transistors. The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of bench-marks while dissipating 97 W at 4.27 GHz and 1.07 V supply.
---
paper_title: Using the NS-2 Network Simulator for Evaluating Multi Protocol Label Switching in Network-on-Chip

paper_content:

Networks-on-chips (NoC) have been introduced as a remedy for the growing problems of current interconnection VLSI chips. Being a relatively new domain in research, simulation tools for NoC are scarce. To fill the gap, we use network simulator NS-2 for simulating multi protocol label switching in NoC, especially at high level chip design. The huge library of network elements with its flexibility to accommodate customized designs like (ASIC), caused to network simulator 2 (NS-2) becomes a viable choice for NoC. We also carry out the NS-2 to simulate MPLS resource reservation mechanism and types of services in NOC.
---
paper_title: Using the NS-2 Network Simulator for Evaluating Network on Chips (NoC)

paper_content:

Networks on chips (NoCs) have been introduced as a remedy for the growing problems of current interconnects in VLSI chips. Being a relatively new domain in research, simulation tools for NoCs are scarce. To fill the gap, we use network simulator NS-2 for simulating NoCs, especially at high level chip design. The huge library of network elements along with its flexibility to accommodate customized designs, NS-2 becomes a viable choice for NoCs. We have used NS-2 to simulate our prototype of a fault tolerant protocol for NoCs
---
paper_title: NoC Design and Implementation in 65nm Technology

paper_content:

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-chip (NoCs) have been proposed as a scalable solution to both physical design issues and increasing bandwidth demands. However, this claim has not been fully validated yet, since the design properties and tradeoffs of NoCs have not been studied in detail below the 100 nm threshold. This work is aimed at shedding light on the opportunities and challenges, both expected and unexpected, of NoC design in nanometer CMOS. We present fully working 65 nm NoC designs, a complete NoC synthesis flow and detailed scalability analysis
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paper_title: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

paper_content:

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but also the constraints imposed by the 3-D technology is a significant challenge. In this paper, we present a design tool, SunFloor 3D, to synthesize application-specific 3-D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components to the 3-D layers, and places them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3-D and 2-D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3-D NoC when compared to the corresponding 2-D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.
---
paper_title: ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration

paper_content:

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes -- the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip -- we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validation against the two Intel chips confirms a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [23] confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.
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paper_title: Orion: a power-performance simulator for interconnection networks

paper_content:

With the prevalence of server blades and systems-on-a-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limited tool support available for their design. While performance simulators have been built that enable performance estimation while varying network parameters, these cover only one metric of interest in modern designs. System power consumption is increasingly becoming equally, if not more important than performance. It is now critical to get detailed power-performance tradeoff information early in the microarchitectural design cycle. This is especially so as interconnection networks consume a significant fraction of total system power. It is exactly this gap that the work presented in this paper aims to fill.We present Orion, a power-performance interconnection network simulator that is capable of providing detailed power characteristics, in addition to performance characteristics, to enable rapid power-performance trade-offs at the architectural-level. This capability is provided within a general framework that builds a simulator starting from a microarchitectural specification of the interconnection network. A key component of this construction is the architectural-level parameterized power models that we have derived as part of this effort. Using component power models and a synthesized efficient power (and performance) simulator, a microarchitect can rapidly explore the design space. As case studies, we demonstrate the use of Orion in determining optimal system parameters, in examining the effect of diverse traffic conditions, as well as evaluating new network microarchitectures. In each of the above, the ability to simultaneously monitor power and performance is key in determining suitable microarchitectures.
---
paper_title: Survey of Network-on-chip Proposals

paper_content:

New substituted urea compounds of formula I, or a pharmaceutically acceptable salt thereof: I wherein A is wherein R3 is an oxadiazol, substituted with C1-8-alkyl, C2-8-alkenyl, C2-8 alkynyl, C3-7 cycloalkyl, benzyl, phenyl, C1-6-alkoxy, C1-6-alkylthio, amino or alkylamino; R2 is -H or lower alkyl; X is O or S; and R1 is a group of formula II, III, IV or V II III IV where n is 2 or 3, p is 1 or 2, q is 1 to 3, r is 1-3 and R4 and R5 are H, C1-7 alkyl or C3-6 cycloalkyl; and N-oxides thereof. The compounds are useful in pharmaceutical preparations for treating psychotic disorders, nausea and vomiting.
---
paper_title: Three-Dimensional Network-on-Chip Architecture

paper_content:

On-chip interconnects are predicted to be a fundamental issue in designing multi-core chip multiprocessors (CMPs) and system-on-chip (SoC) architectures with numerous homogeneous and heterogeneous cores and functional blocks. To mitigate the interconnect crisis, one promising option is network-on-chip (NoC), where a general purpose on-chip interconnection network replaces the traditional design-specific global on-chip wiring by using switching fabrics or routers to connect IP cores or processing elements. Such packet-based communication networks have been gaining wide acceptance due to their scalability and have been proposed for future CMPs and SoC design. In this chapter, we study the combination of both three-dimensional integrated circuits and NoCs, since both are proposed as solutions to mitigate the interconnect scaling challenges. This chapter will start with a brief introduction on network-on-chip architecture and then discuss design space exploration for various network topologies in 3D NoC design, as well as different techniques on 3D on-chip router design. Finally, it describes a design example of using 3D NoC with memory stacked on multi-core CMPs.
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paper_title: Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures

paper_content:

In this paper we evaluate the compromising effect of energy saving and throughput degradation on a fully asynchronous NoC architecture with regards to the dynamic voltage scaling guidelines. The investigated fully asynchronous NoC architecture is suitable for GALS-based MPSoCs architectures. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations, where the energy/throughput trade-off is reported and analyzed. Our results indicate that, although lower power may also be achieved by dynamic throughput scaling, this technique yields negligible energy saving for our asynchronous NoC. Therefore, we suggest a dynamic voltage scaling for this architecture which can save 40% energy at the expense of 13% throughput degradation.
---
paper_title: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

paper_content:

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but also the constraints imposed by the 3-D technology is a significant challenge. In this paper, we present a design tool, SunFloor 3D, to synthesize application-specific 3-D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components to the 3-D layers, and places them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3-D and 2-D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3-D NoC when compared to the corresponding 2-D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.
---
paper_title: GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links

paper_content:

In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. For instance, the results of our evaluation show that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire. As a general rule, when the number of bits to be transmitted increases, the wire overhead decreases and the gate overhead remains almost the same.
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paper_title: Hybrid network on chip (HNoC): local buses with a global mesh architecture

paper_content:

Network on chip (NoC) is often implemented with packet-based communication rather than bus connections between cores. Although NoC is a good solution for long-distance communication, local buses are more efficient for short-distance connections. In this paper, we propose a hybrid network on chip (HNoC) fabric that uses local buses for nearest-neighbor communication and the standard NoC topology for global interconnection. Local buses carry all the nearest-neighbor traffic, reducing traffic on the global network, which results in increased throughput and reduced energy consumption. Based on a communication probability density (CPD) function derived from Rent's rule, it is shown that in a 25-core chip multiprocessor, HNoC can remove up to 78% of the traffic from the global NoC topology, which results in 4.6x higher throughput and a 58% reduction in energy consumption compared to a conventional NoC topology.
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paper_title: Reconfigurable Networks on Chip: DRNoC architecture

paper_content:

To cover the complexity of future systems, where thousands and hundreds of heterogeneous cores have to be interconnected, new on-chip communication solutions are being searched. In this context, Networks on Chip (NoCs) have been studied as bus alternative. However, the inclusion of NoCs' broad design space increases even more the complexity of design flows. Additionally, today electronic industry demands drastic time to market reduction and improved device diversity. On the other side, reconfigurable devices have had an impressive evolution and now, they are complex heterogeneous platforms which include a broad variety of embedded cores. Furthermore, today it is possible to embed reconfigurable arrays in application-specific integrated circuits and thus create highly flexible systems. These tendencies provide support to the idea of reconfigurable on-chip communication, which can reduce the system design time and permit to adapt their characteristics to currently running applications. This paper overviews some reconfigurable NoCs' state of the art solutions and describes a reconfigurable on-chip communication approach, called DRNoC, which explores the highest possible flexibility and is not limited to NoCs. An important aspect considered in this paper is real implementations and therefore, all the solutions discussed along it, including DRNoC, have been validated on FPGAs. The paper also highlights some technology restrictions of currently available FPGA reconfiguration techniques that do not permit to test real-live examples on such systems.
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paper_title: A Latency Simulator for Many-core Systems

paper_content:

In this paper we present MCoreSim, an open-source simulation framework for massively parallel and many-core computing systems based on OMNeT++. The simulator supports tile-based architectures with distributed memory and mesh-based interconnects. Its primary purpose is to allow for investigations on the impact of the heterogeneous in-chip communication latencies, as arising due to the network-on-a-chip structure of future and emerging many-core processors, on the performance of the hosted applications. We plan to use MCoreSim to study the variety of possible choices in realizing a suitable software stack for these systems, especially in terms of the choices at the kernel design level.
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paper_title: A Flexible Parallel Simulator for Networks-on-Chip With Error Control

paper_content:

This paper presents a flexible parallel simulator to evaluate the impact of different error control methods on the performance and energy consumption of networks-on-chip (NoCs). Various error control schemes can be inserted into the simulator in a plug-and-play manner for evaluation. Moreover, a highly tunable fault injection feature is developed for modeling various fault injection scenarios, including different fault injection rates, fault types, fault injection locations, and faulty flit types. Case studies performed in the proposed flexible simulation environment are presented to demonstrate the impact of a set of error control schemes on NoC performance and energy in different noise scenarios. This paper also uses the simulator to provide design guidelines for NoCs with error control capabilities.
---

Title: A Survey of Network-On-Chip Tools

Section 1: INTRODUCTION
Description 1: Introduce the evolution of integration capacities in recent platforms, innovations and advancements in both hardware and software, and the emergence of NoC to solve intra-communication problems.

Section 2: THE NOC CONCEPT
Description 2: Introduce the NoC concept, its principal characteristics, and a comparison between classical buses and Network-On-Chips.

Section 3: NOC DEDICATED TOOLS
Description 3: Present the various NoC dedicated tools used for synthesizing and simulating NoC architectures, including commercial and academic tools.

Section 4: NOC EVALUATION METHODS
Description 4: Discuss the criteria or metrics used to evaluate NoC architectures such as area consumption, power consumption, and latency, along with other auxiliary metrics.

Section 5: RELATED WORKS
Description 5: Review the significant works and developments in the NoC area, including proposals for sophisticated architectures, advancements, and the integration of classical bus concepts with NoC.

Section 6: FINAL REMARKS AND CONCLUSION
Description 6: Summarize the survey's findings, emphasizing the importance of NoC in recent SoCs, and acknowledge that the list of NoC tools presented is not exhaustive.