Memristor Threshold Logic: An Overview to Challenges and Applications
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paper_title: A Survey of Memristive Threshold Logic Circuits

paper_content:

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore’s law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO2, ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.
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paper_title: Resistance switching memories are memristors

paper_content:

All 2-terminal non-volatile memory devices based on resistance switching are memristors, regardless of the device material and physical operating mechanisms. They all exhibit a distinctive “fingerprint” characterized by a pinched hysteresis loop confined to the first and the third quadrants of the v–i plane whose contour shape in general changes with both the amplitude and frequency of any periodic “sine-wave-like” input voltage source, or current source. In particular, the pinched hysteresis loop shrinks and tends to a straight line as frequency increases. Though numerous examples of voltage vs. current pinched hysteresis loops have been published in many unrelated fields, such as biology, chemistry, physics, etc., and observed from many unrelated phenomena, such as gas discharge arcs, mercury lamps, power conversion devices, earthquake conductance variations, etc., we restrict our examples in this tutorial to solid-state and/or nano devices where copious examples of published pinched hysteresis loops abound. In particular, we sampled arbitrarily, one example from each year between the years 2000 and 2010, to demonstrate that the memristor is a device that does not depend on any particular material, or physical mechanism. For example, we have shown that spin-transfer magnetic tunnel junctions are examples of memristors. We have also demonstrated that both bipolar and unipolar resistance switching devices are memristors.
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paper_title: Memristor-The missing circuit element

paper_content:

A new two-terminal circuit element-called the memristorcharacterized by a relationship between the charge q(t)\equiv \int_{-\infty}^{t} i(\tau) d \tau and the flux-linkage \varphi(t)\equiv \int_{- \infty}^{t} v(\tau) d \tau is introduced as the fourth basic circuit element. An electromagnetic field interpretation of this relationship in terms of a quasi-static expansion of Maxwell's equations is presented. Many circuit-theoretic properties of memistors are derived. It is shown that this element exhibits some peculiar behavior different from that exhibited by resistors, inductors, or capacitors. These properties lead to a number of unique applications which cannot be realized with RLC networks alone. Although a physical memristor device without internal power supply has not yet been discovered, operational laboratory models have been built with the help of active circuits. Experimental results are presented to demonstrate the properties and potential applications of memristors.
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paper_title: Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

paper_content:

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/semiconductor surface. The combination of these two memristive effects into multiterminal metal-oxide-semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal-oxide-semiconductor (CMOS) cofabrication with a CMOS-compatible process.
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paper_title: Neuromorphic Character Recognition System With Two PCMO Memristors as a Synapse

paper_content:

Using memristor devices as synaptic connections has been suggested with different neural architectures in the literature. Most of the published works focus on simulating some plasticity mechanism for changing memristor conductance. This paper presents a neural architecture of a character recognition neural system using Al/Pr0.7Ca0.3MnO3 (PCMO) memristors. The PCMO memristor has an inhomogeneous barrier at the aluminum and PCMO interface which gives rise to an asymmetrical behavior when moving from high resistance to low resistance and vice versa. This paper details the design and simulations for solving this asymmetrical memristor behavior. Also, a general memory read/write framework is used to describe the running and plasticity of neural systems. The proposed neural system can be produced in hardware using a small 1 K crossbar memristor grid and CMOS neural nodes as presented in the simulation results.
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paper_title: Hardware realization of BSB recall function using memristor crossbar arrays

paper_content:

The Brain-State-in-a-Box (BSB) model is an auto-associative neural network that has been widely used in optical character recognition and image processing. Traditionally, the BSB model was realized at software level and carried out on high-performance computing clusters. To improve computation efficiency and reduce resources requirement, we propose a hardware realization by utilizing memristor crossbar arrays. In this work, we explore the potential of a memristor crossbar array as an auto-associative memory. More specificly, the recall function of a multi-answer character recognition based on BSB model was realized. The robustness of the proposed BSB circuit was analyzed and evaluated based on massive Monte-Carlo simulations, considering input defects, process variations, and electrical fluctuations. The physical constrains when implementing a neural network with memristor crossbar array have also been discussed. Our results show that the BSB circuit has a high tolerance to random noise. Comparably, the correlations between memristor arrays introduces directional noise and hence dominates the quality of circuits.
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paper_title: Cognitive Memory Network

paper_content:

A resistive memory network that has no crossover wiring is proposed to overcome the hardware limitations to size and functional complexity that is associated with conventional analogue neural networks. The proposed memory network is based on simple network cells that are arranged in a hierarchical modular architecture. Cognitive functionality of this network is demonstrated by an example of character recognition. The network is trained by an evolutionary process to completely recognise characters deformed by random noise, rotation, scaling and shifting.
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paper_title: Memristor-CMOS hybrid integrated circuits for reconfigurable logic

paper_content:

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.
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paper_title: Resistive Threshold Logic

paper_content:

We report a resistance-based threshold logic family useful for mimicking brain-like large variable logic functions in VLSI. A universal boolean logic cell based on an analog resistive divider and threshold logic circuit is presented. The resistive divider is implemented using memristors, and provides output voltage as a summation of weighted product of input voltages. The output of the resistive divider is converted into a binary value by a threshold operation implemented by CMOS inverter and/or Opamp. A universal cell structure is presented to decrease the overall implementation complexity and number of components. When the number of input variables becomes very high, the proposed cell offers advantages of smaller area and design simplicity in comparison with CMOS-based logic circuits.
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paper_title: Resistive MOSFET brain-inspired threshold logic gates

paper_content:

The concept of a pseudo-resistive threshold logic circuit that uses a combination of CMOS inverter and bulk driven MOSFET pseudo-resistive divider circuit for designing a universal NOR gate is presented. Inspired from the neuronal firing mechanisms, the inverter implements the binary threshold decision, while pseudo-resistive circuit provides the summation of normalised weighted inputs. The proposed logic gate when tested using the TSMC 0.18 µm low voltage process show an overall improved performances in terms of area, delay and power in comparison with CMOS and pseudo NMOS logic.
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paper_title: Edge detection using resistive threshold logic networks with CMOS flash memories

paper_content:

Purpose – The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture. Design/methodology/approach – A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system. Findings – The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction ...
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paper_title: Intraoperative cardiac MRI processing using threshold logic cells

paper_content:

Intraoperative MRI is gaining importance in surgery as it enables surgeons to have a look on real-time MRI scans during the surgery. In addition to the large spatial and temporal resolution of the MRI scans, the process of crunching medical data in real-time can be very challenging and crucial. This paper presents a hardware based approach for processing real-time MRI with an application to heart rate analysis. Keywords—Intraoperative MRI, Memory Cell, Threshold Logic Cells.
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paper_title: Parallel Realization of Cognitive Cells on Film Mammography

paper_content:

High speed detection of breast masses from mammography images at an affordable cost is a problem of practical significance in large volume real-time processing and diagnostic assessments. In this paper, we present a new approach to real-time detection of breast masses by introducing the concept of cognitive cells that has a fully parallel high speed computing architecture realised in a low cost hardware. The prototype system was tested using the Compute Unified Device Architecture (CUDA) that achieved an average speed of 6 ms for processing a single 1024x1024 pixels mammography image. Initial results shows feasibility of using cognitive cells for suspicious breast cancer mass detection in mammograms with superior performances in speed in comparison to other standard methods. We report specificity of 95.25% and the cancer false positives per image as 2.275 for MISC, ASYM, CIRC and SPIC cases, while a relatively lower specificity of 70% and the false positives per image as 2.25 is reported for CALC and ARCH cases of abnormalities.
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paper_title: Directional edge detection using parallel cognitive logic cells

paper_content:

This paper presents a novel edge detection method based on parallel cognitive cells which also supports an implementation in high speed hardware. The paper develops directional edge detection strategies that utilize the cognitive cells using the relative neighbourhood-pixel intensity variations in the images. The proposed edge detection method has been implemented in CUDA. The running time for a serial implementation and an equivalent parallel implementation are also reported.
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paper_title: Resistive Threshold Logic

paper_content:

We report a resistance-based threshold logic family useful for mimicking brain-like large variable logic functions in VLSI. A universal boolean logic cell based on an analog resistive divider and threshold logic circuit is presented. The resistive divider is implemented using memristors, and provides output voltage as a summation of weighted product of input voltages. The output of the resistive divider is converted into a binary value by a threshold operation implemented by CMOS inverter and/or Opamp. A universal cell structure is presented to decrease the overall implementation complexity and number of components. When the number of input variables becomes very high, the proposed cell offers advantages of smaller area and design simplicity in comparison with CMOS-based logic circuits.
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paper_title: Memristive Threshold Logic Circuit Design of Fast Moving Object Detection

paper_content:

Real-time detection of moving objects involves memorization of features in the template image and their comparison with those in the test image. At high sampling rates, such techniques face the problems of high algorithmic complexity and component delays. We present a new resistive switching-based threshold logic cell which encodes the pixels of a template image. The cell comprises a voltage divider circuit that programs the resistances of the memristors arranged in a single-node threshold logic network, and the output is encoded as a binary value by using a CMOS inverter gate. When a test image is applied to the template-programmed cell, a mismatch in the respective pixels is seen as a change in the output voltage of the cell. The proposed cell when compared with CMOS equivalent implementation shows improved performance in area, leakage power, power dissipation, and delay.
---
paper_title: Cognitive Memory Network

paper_content:

A resistive memory network that has no crossover wiring is proposed to overcome the hardware limitations to size and functional complexity that is associated with conventional analogue neural networks. The proposed memory network is based on simple network cells that are arranged in a hierarchical modular architecture. Cognitive functionality of this network is demonstrated by an example of character recognition. The network is trained by an evolutionary process to completely recognise characters deformed by random noise, rotation, scaling and shifting.
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paper_title: Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication

paper_content:

Brain-inspired circuits can provide an alternative solution to implement computing architectures taking advantage of fault tolerance and generalization ability of logic gates. In this brief, we advance over the memristive threshold circuit configuration consisting of memristive averaging circuit in combination with operational amplifier and/or CMOS inverters in application to realizing complex computing circuits. The developed memristive threshold logic gates are used for designing fast Fourier transform and multiplication circuits useful for modern microprocessors. Overall, the proposed threshold logic outperforms previous memristive-CMOS logic cells on every aspect, however, they indicate a lower chip area, lower total harmonic distortion, and controllable leakage power, but a higher power dissipation with respect to CMOS logic.
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paper_title: Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition

paper_content:

In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance.
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paper_title: Memristor pattern recogniser: isolated speech word recognition

paper_content:

A memristor-based pattern-matching circuit for realising a hardware oriented approach to isolated speech word recognition is introduced. As distinct from algorithmic solutions, the approach takes advantage of the memristor to memorise and match speech templates in a fast, parallel, low-power and scalable architecture. When tested for isolated word recognition by simulations on the benchmark (TIMIT) and Massachusetts Institute of Technology database, recognition accuracies of 94.5% on clean words and 88% on words with a SNR of 5 dB were achieved.
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paper_title: Memristive threshold logic face recognition

paper_content:

This paper presents a face recognition method implemented using reconfigurable network of memristive threshold logic cells that can be practically realised in a secondary plane to the pixel arrays. Among the most distinguishing features of the presented system are a) an early detection and storage of only the relevant information directly from the sensors, b) a parallel, scalable information storage and detection architecture in hardware, as opposed to an algorithmic approach, and c) a fast and robust face recognition system. The threshold logic cell is inspired from a simplistic cortical neuron model that has multiple inputs with corresponding input memristors and one binary output. These cells when used with a set of input memristors are able to detect significant pixel variations in the incoming video frame and memorize the output template depending on the logic of selection of the resistor values. The implemented face recognition circuit shows small chip area, low power dissipation and ability to scale the networks with increase in image resolutions.
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paper_title: A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits

paper_content:

Hierarchical Temporal Memory (HTM) is a machine learning algorithm that is inspired from the working principles of the neocortex, capable of learning, inference, and prediction for bit-encoded inputs. Spatial pooler is an integral part of HTM that is capable of learning and classifying visual data such as objects in images. In this paper, we propose a memristor-CMOS circuit design of spatial pooler and exploit memristors capabilities for emulating the synapses, where the strength of the weights is represented by the state of the memristor. The proposed design is validated on a challenging application of single image per person face recognition problem using AR database resulting in a recognition accuracy of 80%.
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paper_title: ReRAM-based synaptic device for neuromorphic computing

paper_content:

To compete with nonvolatile FLASH memory technology, we need to develop stackable, cross-point ReRAM device. Although various materials have been reported, it is difficult to meet device criteria such as high speed operation, low power switching, switching uniformity, endurance, long-term retention and selection device for cross-point array. We have investigated various ReRAM devices to meet the nonvolatile memory requirements. We developed wafer scale PCMO-ReRAM devices which exhibit excellent switching uniformity and analog memory behavior. Using PCMO-ReRAM, we can implement analog artificial synapse characteristics for neuromorphic systems. We demonstrated the optimum ReRAM synapse characteristics which are suitable for the neuromorphic application. We compared the time series prediction and face recognition function with varying potentiation and depression characteristics of ReRAM synapse.
---
paper_title: A Survey of Memristive Threshold Logic Circuits

paper_content:

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore’s law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO2, ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.
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paper_title: Memristor models for SPICE simulation of extremely large memristive networks

paper_content:

In order to avoid non-convergence and other numerical problems associated with the simulation of extremely large memristive networks, suitable models of the individual memristors need to be developed. A circuit containing thousands of memristors for finding the shortest path in a complicated maze is a typical example of a numerically challenging simulation. A benchmark circuit for testing the applications of various complexities is used for the transient analysis. It is shown that various commonly used models, from simple behavioral to Pickett models, require special modifications for minimizing the simulation time and improving the convergence issue.
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paper_title: Intraoperative cardiac MRI processing using threshold logic cells

paper_content:

Intraoperative MRI is gaining importance in surgery as it enables surgeons to have a look on real-time MRI scans during the surgery. In addition to the large spatial and temporal resolution of the MRI scans, the process of crunching medical data in real-time can be very challenging and crucial. This paper presents a hardware based approach for processing real-time MRI with an application to heart rate analysis. Keywords—Intraoperative MRI, Memory Cell, Threshold Logic Cells.
---
paper_title: Memristive Threshold Logic Circuit Design of Fast Moving Object Detection

paper_content:

Real-time detection of moving objects involves memorization of features in the template image and their comparison with those in the test image. At high sampling rates, such techniques face the problems of high algorithmic complexity and component delays. We present a new resistive switching-based threshold logic cell which encodes the pixels of a template image. The cell comprises a voltage divider circuit that programs the resistances of the memristors arranged in a single-node threshold logic network, and the output is encoded as a binary value by using a CMOS inverter gate. When a test image is applied to the template-programmed cell, a mismatch in the respective pixels is seen as a change in the output voltage of the cell. The proposed cell when compared with CMOS equivalent implementation shows improved performance in area, leakage power, power dissipation, and delay.
---
paper_title: Directional edge detection using parallel cognitive logic cells

paper_content:

This paper presents a novel edge detection method based on parallel cognitive cells which also supports an implementation in high speed hardware. The paper develops directional edge detection strategies that utilize the cognitive cells using the relative neighbourhood-pixel intensity variations in the images. The proposed edge detection method has been implemented in CUDA. The running time for a serial implementation and an equivalent parallel implementation are also reported.
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paper_title: Generalized Memristive Device SPICE Model and its Application in Circuit Design

paper_content:

This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.
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Title: Memristor Threshold Logic: An Overview to Challenges and Applications

Section 1: INTRODUCTION
Description 1: Introduce the basic concepts of memristors, their characteristics, and their potential applications in threshold logic systems.

Section 2: THRESHOLD LOGIC MEMRISTORS IN COMPUTING AND PATTERN RECOGNITION
Description 2: Discuss the use of memristors in various computing and pattern recognition applications, including character recognition, logic gates, image processing, object recognition, signal processing, speech recognition, and face recognition.

Section 3: MEMRISTOR MODELS
Description 3: Review the various models available for memristor simulation in different tools like SPICE, Verilog, MATLAB, and C++, and discuss the challenges associated with these models.

Section 4: DISCUSSION AND CONCLUSIONS
Description 4: Summarize the key points, discuss the ongoing research challenges, and explore the potential future applications and advancements in memristor technology.