Reconfigurable Multiprocessor Systems: A Review
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paper_title: Multiprocessor System-on-Chip (MPSoC) Technology

paper_content:

The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.
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paper_title: An automated exploration framework for FPGA-based soft multiprocessor systems

paper_content:

FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA. The multiprocessor can be customized for a target application to achieve high performance. Modern FPGAs provide the capacity to build a variety of micro-architectures composed of 20-50 processors, complex memory hierarchies, heterogeneous interconnection schemes and custom co-processors for performance critical operations. However, the diversity in the architectural design space makes it difficult to realize the performance potential of these systems. In this paper we develop an exploration framework to build efficient FPGA multiprocessors for a target application. Our main contribution is a tool based on Integer Linear Programming to explore micro-architectures and allocate application tasks to maximize throughput. Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.
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paper_title: An FPGA-based soft multiprocessor system for IPv4 packet forwarding

paper_content:

To realize high performance, embedded applications are deployed on multiprocessor platforms tailored for an application domain. However, when a suitable platform is not available, only few application niches can justify the increasing costs of an IC product design. An alternative is to design the multiprocessor on an FPGA. This retains the programmability advantage, while obviating the risks in producing silicon. This also opens FPGAs to the world of software designers. In this paper, we demonstrate the feasibility of FPGA-based multiprocessors for high performance applications. We deploy IPv4 packet forwarding on a multiprocessor on the Xilinx Virtex-II Pro FPGA. The design achieves a 1.8 Gbps throughput and loses only 2.6X in performance (normalized to area) compared to an implementation on the Intel IXP-28OO network processor. We also develop a design space exploration framework using integer linear programming to explore multiprocessor configurations for an application. Using this framework, we achieve a more efficient multiprocessor design surpassing the performance of our hand-tuned solution for packet forwarding.
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paper_title: Advantages of FPGA-based multiprocessor systems in industrial applications

paper_content:

Today, industrial production machines must be highly flexible in order to competitively account for dynamic and unforeseen changes in the product demands. This paper shows that field-programmable gate arrays (FPGAs) are especially suited to fulfil these requirements; FPGAs are very powerful, relatively inexpensive, and adaptable, since their configuration is specified in an abstract hardware description language. In addition to the benefits resulting from using an FPGA, the case study presented here shows how FPGAs can be used for implementing a sophisticated multiprocessor architecture. In the course of presentation, this paper furthermore argues that due to the excellent tool support and the availability of reusable functional modules (also known as intellectual properties) this approach can be adopted by almost any industrial hardware designer.
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paper_title: An Adaptive Message Passing MPSoC Framework

paper_content:

Multiprocessor Systems-on-Chips (MPSoCs) offer ::: superior performance while maintaining flexibility and reusability ::: thanks to software oriented personalization. While most ::: MPSoCs are today heterogeneous for better meeting the targeted ::: application requirements, homogeneous MPSoCs may become ::: in a near future a viable alternative bringing other benefits ::: such as run-time load balancing and task migration. The work ::: presented in this paper relies on a homogeneous NoC-based ::: MPSoC framework we developed for exploring scalable and ::: adaptive on-line continuous mapping techniques. Each processor ::: of this system is compact and runs a tiny preemptive operating ::: system that monitors various metrics and is entitled to take ::: remapping decisions through code migration techniques. This ::: approach that endows the architecture with decisional capabilities ::: permits refining application implementation at run-time according ::: to various criteria. Experiments based on simple policies are ::: presented on various applications that demonstrate the benefits ::: of such an approach.
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paper_title: Using Mpi: Portable Parallel Programming with the Message Passing Interface

paper_content:

This book offers a thoroughly updated guide to the MPI (Message-Passing Interface) standard library for writing programs for parallel computers. Since the publication of the previous edition of Using MPI, parallel computing has become mainstream. Today, applications run on computers with millions of processors; multiple processors sharing memory and multicore processors with multiple hardware threads per core are common. The MPI-3 Forum recently brought the MPI standard up to date with respect to developments in hardware capabilities, core language evolution, the needs of applications, and experience gained over the years by vendors, implementers, and users. This third edition of Using MPI reflects these changes in both text and example code. The book takes an informal, tutorial approach, introducing each concept through easy-to-understand examples, including actual code in C and Fortran. Topics include using MPI in simple programs, virtual topologies, MPI datatypes, parallel libraries, and a comparison of MPI with sockets. For the third edition, example code has been brought up to date; applications have been updated; and references reflect the recent attention MPI has received in the literature. A companion volume, Using Advanced MPI, covers more advanced topics, including hybrid programming and coping with large data.
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paper_title: A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA

paper_content:

Modern FPGAs are large enough to implement multi-processor systems-on-chip (MPSoCs). Commercial FPGA companies also provide system design tools that abstract sufficient low-level system details to allow non-FPGA experts to design these systems for new applications. The application presented herein was designed by photomask researchers to implement a new technique for measuring the transparency of bimetallic grayscale masks using an FPGA platform. Production of the bimetallic grayscale masks requires a direct-write laser system. Previously, system calibration was determined by writing large rectangles of varying transparency on a mask and then measuring them using a spectrometer. The proposed technique uses the same mask-writing system but adds photodiode sensors connected to a multiprocessor computing system implemented on an FPGA. The added sensors combined with the laser beam's smaller focal point allows the calibration rectangles to be up to 5000 times smaller than those required by the spectrometer. This allows for direct mask verification on a mum-sized scale. Furthermore, the MPSoC design on the FPGA is easily scalable to support an increased number of photodiodes for the future addition of a feedback approach to the project.
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paper_title: An FPGA-based soft multiprocessor system for IPv4 packet forwarding

paper_content:

To realize high performance, embedded applications are deployed on multiprocessor platforms tailored for an application domain. However, when a suitable platform is not available, only few application niches can justify the increasing costs of an IC product design. An alternative is to design the multiprocessor on an FPGA. This retains the programmability advantage, while obviating the risks in producing silicon. This also opens FPGAs to the world of software designers. In this paper, we demonstrate the feasibility of FPGA-based multiprocessors for high performance applications. We deploy IPv4 packet forwarding on a multiprocessor on the Xilinx Virtex-II Pro FPGA. The design achieves a 1.8 Gbps throughput and loses only 2.6X in performance (normalized to area) compared to an implementation on the Intel IXP-28OO network processor. We also develop a design space exploration framework using integer linear programming to explore multiprocessor configurations for an application. Using this framework, we achieve a more efficient multiprocessor design surpassing the performance of our hand-tuned solution for packet forwarding.
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paper_title: A dual-priority real-time multiprocessor system on FPGA for automotive applications

paper_content:

This paper presents the implementation of a dual-priority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. The dual-priority microkernel is supported by a multiprocessor interrupt controller to trigger periodic and aperiodic thread activation and manage context switching. We show how the dual-priority algorithm performs on a real system prototype compared to the theoretical performance simulations with a typical standard workload of automotive applications, underlining where the differences are.1
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paper_title: Multiple Sequence Alignment on an FPGA

paper_content:

Molecular biologists frequently compute multiple sequence alignments (MSAs) to identify similar regions in protein families. Progressive alignment is a widely used approach to compute MSAs. However, aligning a few hundred sequences by popular progressive alignment tools requires several hours on sequential computers. Due to the rapid growth of biological sequence databases biologists have to compute MSAs in a far shorter time. In this paper we present a new approach to MSA on reconfigurable hardware platforms to gain high performance at low cost. To derive an efficient mapping onto this type of architecture, fine-grained parallel processing elements (PEs) have been designed. Using this PE design as a building block we have constructed a linear systolic array to perform a pairwise sequence distance computation using dynamic programming. This results in an implementation with significant runtime savings on a standard off-the-shelf FPGA
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paper_title: MPSoC design of RT control applications based on FPGA SoftCore processors

paper_content:

Field programmable gate array (FPGA) based controller offer advantages such as high-speed complex functionality and low power consumption. According to the controller complexity, the FPGA design can be achieved by a multiprocessor system on chip (MPSoC) architectures with mixed software/hardware solutions. The aim of this paper is to design a full speed real time (RT) motor control drive algorithms for FPGA based MPSoC. To this purpose, a new approach is proposed to test controller design by implementing RT motor emulator linked to its controller drive in the same FPGA target. The gain with using this new approach is the ability to push past the operational limits of a specific environment and to test fault conditions that would otherwise be damaging or dangerous for a real motor. The developed MPSoC architectures consist of two and three SoftCore (MicroBlaze) processors that are linked by FIFO style communication. The implementation results, give an overview of MPSOC FPGA based controller benefits and illustrate the effect of interprocessor communication mode.
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paper_title: A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

paper_content:

A parallel MPEG-4 simple profile encoder for FPGA based multiprocessor system-on-chip (SoC) is presented. The goal is a computationally scalable framework independent of platform. The scalability is achieved by spatial parallelization where images are divided to horizontal slices. Slice coding tasks are mapped to the multiprocessor consisting of four soft-cores arranged into master-slave configuration. Also, the shared memory model is adopted where large images are stored in shared external memory while small on-chip buffers are used for processing. The interconnections between memories and processors are realized with our HIBI network. Our main contributions are the scalable encoder framework as well as methods for coping with limited memory of FPGA. The current software only implementation processes 6 QCIF frames/s with three encoding slaves. In practice, speed-ups of 1.7 and 2.3 have been measured with two and three slaves, respectively. FPGA utilization of current implementation is 59% requiring 24 207 logic elements on Altera Stratix EP1S40.
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paper_title: Advantages of FPGA-based multiprocessor systems in industrial applications

paper_content:

Today, industrial production machines must be highly flexible in order to competitively account for dynamic and unforeseen changes in the product demands. This paper shows that field-programmable gate arrays (FPGAs) are especially suited to fulfil these requirements; FPGAs are very powerful, relatively inexpensive, and adaptable, since their configuration is specified in an abstract hardware description language. In addition to the benefits resulting from using an FPGA, the case study presented here shows how FPGAs can be used for implementing a sophisticated multiprocessor architecture. In the course of presentation, this paper furthermore argues that due to the excellent tool support and the availability of reusable functional modules (also known as intellectual properties) this approach can be adopted by almost any industrial hardware designer.
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paper_title: An MPSoC architecture for the Multiple Target Tracking application in driver assistant system

paper_content:

This article discusses the design of an application specific MPSoC architecture dedicated to multiple target tracking (MTT). This application has its utility in driver assistant systems, more precisely in collision avoidance and warning systems. An automotive-radar is used as the front end sensor in our application. The article examines the tradeoffs that must be taken into consideration in the realization of the entire MTT application in an embedded system. In our implementation of MTT, several independent parallel tasks have been identified and mapped onto a multiprocessor architecture to ensure the deadlines imposed by the application. Our study demonstrates that the joint utilization of reconfigurable circuits (namely FPGA) and MPSoC, facilitates the development of a flexible and efficient MTT system.
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paper_title: MPLEM: An 80-processor FPGA Based Multiprocessor System

paper_content:

Multiprocessor embedded systems (MESes) are a very promising approach for high performance yet relatively low-cost computing. At the same time modern FPGAs provide the silicon capacity to build multiprocessor systems containing 10-100 processors, complex memory systems, heterogeneous interconnection schemes and custom engines executing the performance-critical operations. In this work we present a MES implemented in a state-of-the-art FPGA consisting of up to eighty 32-bit processors. The efficiency of our approach is demonstrated by the fact that our system can execute the BLAST CPU-intensive application, which is the prevalent tool used by molecular biologists for DNA sequence matching and database search, many times faster than a simple PC.
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paper_title: External DDR2-constrained NOC-based 24-processors MPSOC design and implementation on single FPGA

paper_content:

Network on chip (NOC) has been proposed for the connection substrate of multiprocessor system on chip (SoC) due to limited bandwidth of bus based solutions. Although some designs are emerging actual design experiences of NOC based multiprocessor system on chip remain scarce contrary to simulation based studies. However, implementation constraints clearly affects th design and modelling of a complex multiprocessor. In this paper we present the design and implementation of a 24-processors multiprocessor system with 24 processors under the constraints of limited access to 4 external DDR2 memory banks. All the processors and DDR2 memories are connected to a network on chip through open core protocol (OCP) interface. Multiple clock domains result ing from various IP complexities requires global asynchronous local synchronous (GALS) design methodlogy which adds some extra area. The multiprocessor system is fully implemented on Xilinx Virtex-4 FX140 FPGA based board and uses about 90 % of the chip area.
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paper_title: Operating System for Symmetric Multiprocessors on FPGA

paper_content:

Soft-core based multiprocessor systems are getting very popular in the FPGA design world. There are many computer architectures that has been used for building multiprocessor systems on FPGAs, including SMP (symmetric multiprocessor). One of the main drawback of this SMP systems is the unavailability of operating systems that allow programming multi-threaded applications that make good use of the multiple processors of the system. This paper details an operating system designed to be used with SMP systems based on the MicroBlaze soft-core processor. The OS is tested with three different applications on an SMP system which implements all the software and hardware required for the OS to work on different SMP systems.
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paper_title: An Adaptive Message Passing MPSoC Framework

paper_content:

Multiprocessor Systems-on-Chips (MPSoCs) offer ::: superior performance while maintaining flexibility and reusability ::: thanks to software oriented personalization. While most ::: MPSoCs are today heterogeneous for better meeting the targeted ::: application requirements, homogeneous MPSoCs may become ::: in a near future a viable alternative bringing other benefits ::: such as run-time load balancing and task migration. The work ::: presented in this paper relies on a homogeneous NoC-based ::: MPSoC framework we developed for exploring scalable and ::: adaptive on-line continuous mapping techniques. Each processor ::: of this system is compact and runs a tiny preemptive operating ::: system that monitors various metrics and is entitled to take ::: remapping decisions through code migration techniques. This ::: approach that endows the architecture with decisional capabilities ::: permits refining application implementation at run-time according ::: to various criteria. Experiments based on simple policies are ::: presented on various applications that demonstrate the benefits ::: of such an approach.
---
paper_title: Symmetric Multiprocessing on Programmable Chips Made Easy

paper_content:

Vendor-provided softcore processors often support advanced features such as caching that work well in uniprocessor or uncoupled multiprocessor architectures. However, it is a challenge to implement symmetric multiprocessor on a programmable chip (SMPoPC) systems using such processors. This paper presents an implementation of a tightly coupled, cache-coherent symmetric multiprocessing architecture using a vendor-provided softcore processor. Experimental results show that this implementation can be achieved without invasive changes to the vendor-provided softcore processor and without degradation of the performance of the memory system.
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paper_title: Exploring FPGA Capabilities for Building Symmetric Multiprocessor Systems

paper_content:

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.
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paper_title: A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

paper_content:

Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.
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paper_title: New dimensions for multiprocessor architectures: On demand heterogeneity, infrastructure and performance through reconfigurability — the RAMPSoC approach

paper_content:

Multiprocessor hardware architectures enable to distribute tasks of an application to several microprocessors, in order to exploit parallelism for accelerating the performance of computation. Especially for the application domain of image data processing, where computation performance is a crucial factor to keep the real-time requirements, this approach is a promising solution for the assembly of high sophisticated algorithms e.g. for object tracking. Changing requirements and the necessary implementation of the tasks in terms of modified algorithms, precision and communication needs to be handled by software and hardware adaptation in state of the art architectures. Field programmable gate arrays (FPGAs) enable to exploit the adaptation of hardware cores and the software running on embedded microprocessor cores on an integrated multiprocessor system.
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paper_title: Very high-speed computing systems

paper_content:

Very high-speed computers may be classified as follows: 1) Single Instruction Stream-Single Data Stream (SISD) 2) Single Instruction Stream-Multiple Data Stream (SIMD) 3) Multiple Instruction Stream-Single Data Stream (MISD) 4) Multiple Instruction Stream-Multiple Data Stream (MIMD). "Stream," as used here, refers to the sequence of data or instructions as seen by the machine during the execution of a program. The constituents of a system: storage, execution, and instruction handling (branching) are discussed with regard to recent developments and/or systems limitations. The constituents are discussed in terms of concurrent SISD systems (CDC 6600 series and, in particular, IBM Model 90 series), since multiple stream organizations usually do not require any more elaborate components. Representative organizations are selected from each class and the arrangement of the constituents is shown.
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paper_title: Parallel and flexible multiprocessor system-on-chip for adaptive automotive applications based on Xilinx MicroBlaze soft-cores

paper_content:

Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. When designing a system that includes this feature it has to be made sure, that no signal lines cross the border to other reconfigurable regions. The complex modular design flow to generate partial bitstreams and the need of macros for physical interconnection of IP-Cores causes the necessity to investigate in alternatives. This paper describes the design and implementation of a software reconfigurable multiprocessor system, based on Xilinx MicroBlaze softcore processors. A real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA is used to present results.
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paper_title: MPLEM: An 80-processor FPGA Based Multiprocessor System

paper_content:

Multiprocessor embedded systems (MESes) are a very promising approach for high performance yet relatively low-cost computing. At the same time modern FPGAs provide the silicon capacity to build multiprocessor systems containing 10-100 processors, complex memory systems, heterogeneous interconnection schemes and custom engines executing the performance-critical operations. In this work we present a MES implemented in a state-of-the-art FPGA consisting of up to eighty 32-bit processors. The efficiency of our approach is demonstrated by the fact that our system can execute the BLAST CPU-intensive application, which is the prevalent tool used by molecular biologists for DNA sequence matching and database search, many times faster than a simple PC.
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paper_title: Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs

paper_content:

Recent significant advancements in FPGAs have made it viable to explore multiprocessor solutions on a single FPGA chip. An efficient communication architecture that matches the needs of the target application is always critical to the overall performance of multiprocessors. Packet-switching network-on-chip (NoC) approaches are being offered to deal with scalability and complexity challenges coming along with the increasing number of processing elements (PEs). Many FPGA-based NoC designs consume significant resources, leaving little room for PEs. We argue that computation is still the primary task of multiprocessors and sufficient resources should be reserved for PEs. This paper presents our novel design and implementation of a resource-efficient communication architecture for multiprocessors on FPGAs. We reduce not only the required number of routers for a given number of PEs by introducing a new PE-router topology, but also resource requirements of each router, while maintaining good performance for typical injection rates.
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paper_title: External DDR2-constrained NOC-based 24-processors MPSOC design and implementation on single FPGA

paper_content:

Network on chip (NOC) has been proposed for the connection substrate of multiprocessor system on chip (SoC) due to limited bandwidth of bus based solutions. Although some designs are emerging actual design experiences of NOC based multiprocessor system on chip remain scarce contrary to simulation based studies. However, implementation constraints clearly affects th design and modelling of a complex multiprocessor. In this paper we present the design and implementation of a 24-processors multiprocessor system with 24 processors under the constraints of limited access to 4 external DDR2 memory banks. All the processors and DDR2 memories are connected to a network on chip through open core protocol (OCP) interface. Multiple clock domains result ing from various IP complexities requires global asynchronous local synchronous (GALS) design methodlogy which adds some extra area. The multiprocessor system is fully implemented on Xilinx Virtex-4 FX140 FPGA based board and uses about 90 % of the chip area.
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paper_title: HIBI-based multiprocessor SoC on FPGA

paper_content:

An FPGA offers an excellent platform for a system-on-chip consisting of intellectual property (IP) blocks. The problem is that IP blocks and their interconnections are often FPGA vendor dependent. Our HIBI (heterogeneous IP block interconnection) network-on-chip (NoC) scheme solves the problem by providing a flexible interconnection network and IP block integration with an open core protocol (OCP) interface. Therefore, IP components can be of any type: processors; hardware accelerators; communication interfaces; memories. As a proof of concept, a multiprocessor system with eight soft processor cores and HIBI is prototyped on FPGA. The whole system uses 36,402 logic elements, 2.9 Mbits of RAM, and operates at 78 MHz frequency on the Altera Stratix 1S40, which is comparable to other FPGA multiprocessors. The most important benefit is significant reduction of the design effort compared to system specific interconnection networks. HIBI also presents the first OCP compliant IP-block integration in FPGA.
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paper_title: Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs

paper_content:

This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip multiprocessor proposals were designed and compared for Xilinx FPGAs using MicroBlaze processors: one based on NoC and the other based on shared memory/bus. One of the main findings is the communication performance evaluation of NoC for parallel computing applications. The comparison results show that an efficient implementation of NoC on FPGA can improve communication speed by up to seven times with low area overhead, according to the data size and the number of processors connected to the network.
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paper_title: Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform

paper_content:

Multiprocessors on a chip are the reality of these days. Semiconductor industry has recognized this approach as the most efficient in order to exploit chip resources, but the success of this paradigm heavily relies on the efficiency and widespread diffusion of parallel software. Among the many techniques to express the parallelism of applications, this paper focuses on pipelining, a technique well suited to data-intensive multimedia applications. We introduce a prototyping platform (FPGA-based) and a methodology for these applications. Our platform consists of a mix of standard and custom heterogeneous cores. We discuss several case studies, analyzing the interaction of the architecture and applications and we show that multimedia and telecommunication applications with unbalanced pipeline stages can be easily deployed. Our framework eases the development cycle and enables the developers to focus directly on the problems posed by the programming model in the direction of the implementation of a production system.
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paper_title: Generic crossbar network on chip for FPGA MPSoCs

paper_content:

Networks-on-chip (NoCs) have emerged as a new design paradigm to implement MPSoCs that competes with the standard bus approach. They offer more scalability, flexibility, and bandwidth. Nevertheless, FPGA manufacturers still use the bus paradigm in their development frameworks. In this paper, we study the complexity and performances of a FPGA implementation for a crossbar NoC. We propose a generic architecture and characterize its complexity, maximum frequency of operation, and global throughput for NoCs supporting 2 to 8 nodes. Results show that FPGA-based designs would benefit from such architecture when high throughput must be reached. Finally, we present a fully functional 3times3 NoC interconnecting a PowerPC and 2 Xtensa processors implemented in a VirtexII Pro FPGA.
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paper_title: A network on chip architecture and design methodology

paper_content:

We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m/spl times/n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- and architectural-level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.
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paper_title: Symmetric Multiprocessing on Programmable Chips Made Easy

paper_content:

Vendor-provided softcore processors often support advanced features such as caching that work well in uniprocessor or uncoupled multiprocessor architectures. However, it is a challenge to implement symmetric multiprocessor on a programmable chip (SMPoPC) systems using such processors. This paper presents an implementation of a tightly coupled, cache-coherent symmetric multiprocessing architecture using a vendor-provided softcore processor. Experimental results show that this implementation can be achieved without invasive changes to the vendor-provided softcore processor and without degradation of the performance of the memory system.
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paper_title: Evaluating Large System-on-Chip on Multi-FPGA Platform

paper_content:

This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on-Chip architectures on multiple FPGAs with support to Globally Asynchronous Locally Synchronous scheme. It allows early hardware/software co-verification and optimization. The architecture abstracts the underlying hardware details from the processors so that knowledge about the exact locations of individual components are not required for communication. Implemented example architecture contains 58 IP blocks, including 35 Nios II soft processors. As a proof of concept, a MPEG-4 video encoder is run on the example architecture.
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paper_title: Multistage Interconnection Network for MPSoC: Performances study and prototyping on FPGA

paper_content:

Multiprocessor system on chip is a concept that aims to integrate multiple hardware and software in a chip. multistage interconnection network is considered as a promising solution for applications which use parallel architectures integrating a large number of processors and memories. in this paper, we present a model of multistage interconnection network and a design of prototyping on FPGA. This enabled the comparison of the proposed model with the full crossbar network, and the estimation of performance in terms of area, latency and energy consumption. The Multistage Interconnection Networks are well adapted to MPSoC architecture. They meet the needs of intensive signal processing and they are scalable to connect a large number of modules.
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paper_title: Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol

paper_content:

Multiprocessor System-on-Chip is a promising realization alternative for the next generation of computing architectures providing the required data processing performance in high performance computing applications. Numerous scientists from industry and academic institutions investigate and develop novel processing elements and accelerators as can be seen in real devices like IBM's Cell or nVIDIA's Tesla GPU. Nevertheless, the on-chip communication of these multiple processor elements has to be optimized tailored to the actual requirement of the data to be processed. Network-on-Chip (NoC), Bus-based or even heterogeneous communication on chip often suffer from the fact of being inflexible due to their fixed physical realization. This paper presents a novel approach for a NoC, exploiting circuit-and packed-switched communication as well as a run-time adaptive and heterogeneous topology. An application scenario from image processing exploiting the implemented NoC on an FPGA delivers results like performance data and hardware costs.
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paper_title: Exploring FPGA Capabilities for Building Symmetric Multiprocessor Systems

paper_content:

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.
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paper_title: An Interrupt Controller for FPGA-based Multiprocessors

paper_content:

Interrupt-based programming is widely used for interfacing a processor with peripherals and allowing software threads to interact. Many hardware/software architectures have been proposed in the past to support this kind of programming practice. In the context of FPGA-based multiprocessors this topic has not been thoroughly faced yet. This paper presents the architecture of an interrupt controller for a FPGA-based multiprocessor composed of standard off-of-the-shelf softcores. The main feature of this device is to distribute multiple interrupts across the cores of a multiprocessor. In addition, our architecture supports several advanced features like booking, broadcasting and inter-processor interrupt. On the top of this hardware layer, we provide a software library to effectively exploit this mechanism. We realized a prototype of this system. Our experiments show that our interrupt controller efficiently distributes multiple interrupts on the system.
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paper_title: MPLEM: An 80-processor FPGA Based Multiprocessor System

paper_content:

Multiprocessor embedded systems (MESes) are a very promising approach for high performance yet relatively low-cost computing. At the same time modern FPGAs provide the silicon capacity to build multiprocessor systems containing 10-100 processors, complex memory systems, heterogeneous interconnection schemes and custom engines executing the performance-critical operations. In this work we present a MES implemented in a state-of-the-art FPGA consisting of up to eighty 32-bit processors. The efficiency of our approach is demonstrated by the fact that our system can execute the BLAST CPU-intensive application, which is the prevalent tool used by molecular biologists for DNA sequence matching and database search, many times faster than a simple PC.
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paper_title: External DDR2-constrained NOC-based 24-processors MPSOC design and implementation on single FPGA

paper_content:

Network on chip (NOC) has been proposed for the connection substrate of multiprocessor system on chip (SoC) due to limited bandwidth of bus based solutions. Although some designs are emerging actual design experiences of NOC based multiprocessor system on chip remain scarce contrary to simulation based studies. However, implementation constraints clearly affects th design and modelling of a complex multiprocessor. In this paper we present the design and implementation of a 24-processors multiprocessor system with 24 processors under the constraints of limited access to 4 external DDR2 memory banks. All the processors and DDR2 memories are connected to a network on chip through open core protocol (OCP) interface. Multiple clock domains result ing from various IP complexities requires global asynchronous local synchronous (GALS) design methodlogy which adds some extra area. The multiprocessor system is fully implemented on Xilinx Virtex-4 FX140 FPGA based board and uses about 90 % of the chip area.
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paper_title: Lightweight DMA management mechanisms for multiprocessors on FPGA

paper_content:

This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each processor. The system integrates all standard DMA primitives via a fast Application Programming Interface (API) and relies on interrupts having also the possibility to manage a command list. This interface allows to program the embedded multiprocessor architecture on FPGA with simple DMAs using the same DMA techniques adopted on high performance multiprocessors with complex DMA controllers. Several experiments demonstrate the performance of our solution, allowing 57% improvement on the execution time of a selected set of benchmarks. We furthermore show how some DMA programming techniques (double and multi-buffering) can be effectively used within our platform, thus easing the design and development of the hardware and the software in a reconfigurable DMA-based environment.
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paper_title: A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA

paper_content:

Modern FPGAs are large enough to implement multi-processor systems-on-chip (MPSoCs). Commercial FPGA companies also provide system design tools that abstract sufficient low-level system details to allow non-FPGA experts to design these systems for new applications. The application presented herein was designed by photomask researchers to implement a new technique for measuring the transparency of bimetallic grayscale masks using an FPGA platform. Production of the bimetallic grayscale masks requires a direct-write laser system. Previously, system calibration was determined by writing large rectangles of varying transparency on a mask and then measuring them using a spectrometer. The proposed technique uses the same mask-writing system but adds photodiode sensors connected to a multiprocessor computing system implemented on an FPGA. The added sensors combined with the laser beam's smaller focal point allows the calibration rectangles to be up to 5000 times smaller than those required by the spectrometer. This allows for direct mask verification on a mum-sized scale. Furthermore, the MPSoC design on the FPGA is easily scalable to support an increased number of photodiodes for the future addition of a feedback approach to the project.
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paper_title: An automated exploration framework for FPGA-based soft multiprocessor systems

paper_content:

FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA. The multiprocessor can be customized for a target application to achieve high performance. Modern FPGAs provide the capacity to build a variety of micro-architectures composed of 20-50 processors, complex memory hierarchies, heterogeneous interconnection schemes and custom co-processors for performance critical operations. However, the diversity in the architectural design space makes it difficult to realize the performance potential of these systems. In this paper we develop an exploration framework to build efficient FPGA multiprocessors for a target application. Our main contribution is a tool based on Integer Linear Programming to explore micro-architectures and allocate application tasks to maximize throughput. Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.
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paper_title: An FPGA-based soft multiprocessor system for IPv4 packet forwarding

paper_content:

To realize high performance, embedded applications are deployed on multiprocessor platforms tailored for an application domain. However, when a suitable platform is not available, only few application niches can justify the increasing costs of an IC product design. An alternative is to design the multiprocessor on an FPGA. This retains the programmability advantage, while obviating the risks in producing silicon. This also opens FPGAs to the world of software designers. In this paper, we demonstrate the feasibility of FPGA-based multiprocessors for high performance applications. We deploy IPv4 packet forwarding on a multiprocessor on the Xilinx Virtex-II Pro FPGA. The design achieves a 1.8 Gbps throughput and loses only 2.6X in performance (normalized to area) compared to an implementation on the Intel IXP-28OO network processor. We also develop a design space exploration framework using integer linear programming to explore multiprocessor configurations for an application. Using this framework, we achieve a more efficient multiprocessor design surpassing the performance of our hand-tuned solution for packet forwarding.
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paper_title: A dual-priority real-time multiprocessor system on FPGA for automotive applications

paper_content:

This paper presents the implementation of a dual-priority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. The dual-priority microkernel is supported by a multiprocessor interrupt controller to trigger periodic and aperiodic thread activation and manage context switching. We show how the dual-priority algorithm performs on a real system prototype compared to the theoretical performance simulations with a typical standard workload of automotive applications, underlining where the differences are.1
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paper_title: MPSoC design of RT control applications based on FPGA SoftCore processors

paper_content:

Field programmable gate array (FPGA) based controller offer advantages such as high-speed complex functionality and low power consumption. According to the controller complexity, the FPGA design can be achieved by a multiprocessor system on chip (MPSoC) architectures with mixed software/hardware solutions. The aim of this paper is to design a full speed real time (RT) motor control drive algorithms for FPGA based MPSoC. To this purpose, a new approach is proposed to test controller design by implementing RT motor emulator linked to its controller drive in the same FPGA target. The gain with using this new approach is the ability to push past the operational limits of a specific environment and to test fault conditions that would otherwise be damaging or dangerous for a real motor. The developed MPSoC architectures consist of two and three SoftCore (MicroBlaze) processors that are linked by FIFO style communication. The implementation results, give an overview of MPSOC FPGA based controller benefits and illustrate the effect of interprocessor communication mode.
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paper_title: A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

paper_content:

A parallel MPEG-4 simple profile encoder for FPGA based multiprocessor system-on-chip (SoC) is presented. The goal is a computationally scalable framework independent of platform. The scalability is achieved by spatial parallelization where images are divided to horizontal slices. Slice coding tasks are mapped to the multiprocessor consisting of four soft-cores arranged into master-slave configuration. Also, the shared memory model is adopted where large images are stored in shared external memory while small on-chip buffers are used for processing. The interconnections between memories and processors are realized with our HIBI network. Our main contributions are the scalable encoder framework as well as methods for coping with limited memory of FPGA. The current software only implementation processes 6 QCIF frames/s with three encoding slaves. In practice, speed-ups of 1.7 and 2.3 have been measured with two and three slaves, respectively. FPGA utilization of current implementation is 59% requiring 24 207 logic elements on Altera Stratix EP1S40.
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paper_title: Advantages of FPGA-based multiprocessor systems in industrial applications

paper_content:

Today, industrial production machines must be highly flexible in order to competitively account for dynamic and unforeseen changes in the product demands. This paper shows that field-programmable gate arrays (FPGAs) are especially suited to fulfil these requirements; FPGAs are very powerful, relatively inexpensive, and adaptable, since their configuration is specified in an abstract hardware description language. In addition to the benefits resulting from using an FPGA, the case study presented here shows how FPGAs can be used for implementing a sophisticated multiprocessor architecture. In the course of presentation, this paper furthermore argues that due to the excellent tool support and the availability of reusable functional modules (also known as intellectual properties) this approach can be adopted by almost any industrial hardware designer.
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paper_title: An MPSoC architecture for the Multiple Target Tracking application in driver assistant system

paper_content:

This article discusses the design of an application specific MPSoC architecture dedicated to multiple target tracking (MTT). This application has its utility in driver assistant systems, more precisely in collision avoidance and warning systems. An automotive-radar is used as the front end sensor in our application. The article examines the tradeoffs that must be taken into consideration in the realization of the entire MTT application in an embedded system. In our implementation of MTT, several independent parallel tasks have been identified and mapped onto a multiprocessor architecture to ensure the deadlines imposed by the application. Our study demonstrates that the joint utilization of reconfigurable circuits (namely FPGA) and MPSoC, facilitates the development of a flexible and efficient MTT system.
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paper_title: Symmetric Multiprocessing on Programmable Chips Made Easy

paper_content:

Vendor-provided softcore processors often support advanced features such as caching that work well in uniprocessor or uncoupled multiprocessor architectures. However, it is a challenge to implement symmetric multiprocessor on a programmable chip (SMPoPC) systems using such processors. This paper presents an implementation of a tightly coupled, cache-coherent symmetric multiprocessing architecture using a vendor-provided softcore processor. Experimental results show that this implementation can be achieved without invasive changes to the vendor-provided softcore processor and without degradation of the performance of the memory system.
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paper_title: Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol

paper_content:

Multiprocessor System-on-Chip is a promising realization alternative for the next generation of computing architectures providing the required data processing performance in high performance computing applications. Numerous scientists from industry and academic institutions investigate and develop novel processing elements and accelerators as can be seen in real devices like IBM's Cell or nVIDIA's Tesla GPU. Nevertheless, the on-chip communication of these multiple processor elements has to be optimized tailored to the actual requirement of the data to be processed. Network-on-Chip (NoC), Bus-based or even heterogeneous communication on chip often suffer from the fact of being inflexible due to their fixed physical realization. This paper presents a novel approach for a NoC, exploiting circuit-and packed-switched communication as well as a run-time adaptive and heterogeneous topology. An application scenario from image processing exploiting the implemented NoC on an FPGA delivers results like performance data and hardware costs.
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paper_title: Exploring FPGA Capabilities for Building Symmetric Multiprocessor Systems

paper_content:

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.
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paper_title: Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips

paper_content:

Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such architectures in a single chip feasible and very appealing. Although the FPGA chip technology is well developed by companies such as Xilinx and Altera, the concepts and the necessary tool support for building multiprocessor systems on a single FPGA chip are still not mature enough. As a consequence, system designers experience significant difficulties in 1) designing multiprocessor systems on FPGAs in a short amount of time and 2) programming such systems in order to satisfy the performance needs of applications executed on them. In this paper we present our concept for multiprocessor system design, programing, and implementation that addresses and solves the above two problems in a particular way. We have implemented the concept in a tool called ESPAM which is briefly introduced as well. Also, we present some results obtained by applying our concept and ESPAM tool to automatically generate multiprocessor systems that execute a real-life application, namely a Motion-JPEG encoder.
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paper_title: An automated exploration framework for FPGA-based soft multiprocessor systems

paper_content:

FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA. The multiprocessor can be customized for a target application to achieve high performance. Modern FPGAs provide the capacity to build a variety of micro-architectures composed of 20-50 processors, complex memory hierarchies, heterogeneous interconnection schemes and custom co-processors for performance critical operations. However, the diversity in the architectural design space makes it difficult to realize the performance potential of these systems. In this paper we develop an exploration framework to build efficient FPGA multiprocessors for a target application. Our main contribution is a tool based on Integer Linear Programming to explore micro-architectures and allocate application tasks to maximize throughput. Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.
---
paper_title: An FPGA-based soft multiprocessor system for IPv4 packet forwarding

paper_content:

To realize high performance, embedded applications are deployed on multiprocessor platforms tailored for an application domain. However, when a suitable platform is not available, only few application niches can justify the increasing costs of an IC product design. An alternative is to design the multiprocessor on an FPGA. This retains the programmability advantage, while obviating the risks in producing silicon. This also opens FPGAs to the world of software designers. In this paper, we demonstrate the feasibility of FPGA-based multiprocessors for high performance applications. We deploy IPv4 packet forwarding on a multiprocessor on the Xilinx Virtex-II Pro FPGA. The design achieves a 1.8 Gbps throughput and loses only 2.6X in performance (normalized to area) compared to an implementation on the Intel IXP-28OO network processor. We also develop a design space exploration framework using integer linear programming to explore multiprocessor configurations for an application. Using this framework, we achieve a more efficient multiprocessor design surpassing the performance of our hand-tuned solution for packet forwarding.
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paper_title: Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

paper_content:

Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semiautomated, time consuming, and error prone. ::: In this article, we present a design methodology to generate multiprocessor systems in a systematic and fully automated way for multiple use-cases. Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well suited for fast design-space exploration (DSE) in MPSoC systems. Heuristics to partition use-cases are also presented such that each partition can fit in an FPGA, and all use-cases can be catered for. ::: The proposed methodology is implemented into a tool for Xilinx FPGAs for evaluation. The tool is also made available online for the benefit of the research community and is used to carry out a DSE case study with multiple use-cases of real-life applications: H263 and JPEG decoders. The generation of the entire design takes about 100 ms, and the whole DSE was completed in 45 minutes, including FPGA mapping and synthesis. The heuristics used for use-case partitioning reduce the design-exploration time elevenfold in a case study with mobile-phone applications.
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Title: Reconfigurable Multiprocessor Systems: A Review

Section 1: Introduction
Description 1: Introductory background on the evolution and significance of MPSoC, highlighting the transition to FPGA-based multiprocessor designs.

Section 2: Viability of FPGA-Based Multiprocessor Systems
Description 2: Discussion on the advantages, challenges, and specific use cases where FPGA-based multiprocessor systems are beneficial.

Section 3: FPGA-Based Multiprocessor Systems
Description 3: Several examples of FPGA-based multiprocessor systems implemented by the research community.

Section 4: Architecture Background
Description 4: Overview of target application architectures for FPGA-based multiprocessor systems, including Master-Slave, Pipeline, and Net architectures.

Section 5: Classification
Description 5: Traditional classification of MPSoCs into homogeneous and heterogeneous systems and shared-memory versus distributed-memory systems.

Section 6: Heterogeneous FPGA-Based Systems
Description 6: Detailed examples and case studies of application-specific FPGA-based multiprocessor systems and their architectures.

Section 7: Homogeneous FPGA-Based Systems
Description 7: Examples and benefits of homogeneous multiprocessor systems, along with comparisons to heterogeneous systems.

Section 8: Run-Time Reconfigurable Systems
Description 8: Exploration of run-time reconfigurability in multiprocessor systems and new taxonomies for these systems.

Section 9: Design Challenges
Description 9: Critical issues in FPGA-based multiprocessor design, including resource limitations, synchronization, cache coherency, and on-chip communication.

Section 10: Design Methodology
Description 10: Two methodologies for building multiprocessor systems in FPGA: hand-tuned design and automatic synthesis design, along with their respective benefits and limitations.

Section 11: Conclusion
Description 11: Summary of the survey findings, major challenges, and future directions in FPGA-based multiprocessor system design.