Overview of candidate device technologies for storage-class memory
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paper_title: Future Outlook of NAND Flash Technology for 40nm Node and Beyond

paper_content:

The NAND flash memory occupied 40% of the total flash memory market with an annual growth rate of 70% in 2004, while NOR flash achieved only more modest growth rate of 30%. It is expected that NAND flash will surpass the market share of NOR flash in the flash market for the first time in 2005. From the viewpoint of market trend, NAND flash will be more popular in future because of more diversified applications such as NHDD (NAND-HDD) and sub-notebook PC storage. In this paper, we review the critical barriers in further scaling down NAND flash to 40nm technology node and beyond. Then, breakthrough technologies are addressed to overcome the barriers. In addition, issues in performance and reliability of the high density NAND flash are discussed
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paper_title: Cramming More Components Onto Integrated Circuits

paper_content:

The future of integrated electronics is the future of electronics itself. The advantages of integration will bring about a proliferation of electronics, pushing this science into many new areas. Integrated circuits will lead to such wonders as home computers—or at least terminals connected to a central computer—automatic controls for automobiles, and personal portable communications equipment. The electronic wristwatch needs only a display to be feasible today. But the biggest potential lies in the production of large systems. In telephone communications, integrated circuits in digital filters will separate channels on multiplex equipment. Integrated circuits will also switch telephone circuits and perform data processing. Computers will be more powerful, and will be organized in completely different ways. For example, memories built of integrated electronics may be distributed throughout the machine instead of being concentrated in a central unit. In addition, the improved reliability made possible by integrated circuits will allow the construction of larger processing units. Machines similar to those in existence today will be built at lower costs and with faster turnaround.
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paper_title: Storage-class memory: The next storage system technology

paper_content:

The dream of replacing rotating mechanical storage, the disk drive, with solid-state, nonvolatile RAM may become a reality in the near future. Approximately ten new technologies--collectively called storage-class memory (SCM)--are currently under development and promise to be fast, inexpensive, and power efficient. Using SCM as a disk drive replacement, storage system products will have random and sequential I/O performance that is orders of magnitude better than that of comparable disk-based systems and require much less space and power in the data center. In this paper, we extrapolate disk and SCM technology trends to 2020 and analyze the impact on storage systems. The result is a 100- to 1,O00-fold advantage for SCM in terms of the data center space and power required.
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paper_title: Design of ion-implanted MOSFET's with very small physical dimensions

paper_content:

This paper considers the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits using dimensions of the order of 1μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation to proVide shallow source and drain regions and a nonuniform substrate doping profile. Onedimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFETs with channel lengths as short as 0.5μ were fabricated, and the device characteristics measured and compared with predicted values. Ibe performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected. Reprintedfrom the IEEE Journal of Solid-State Circuits, Vol. SC-9, October 1974, pp. 256-268.]
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paper_title: Technological impact of magnetic hard disk drives on storage systems

paper_content:

Magnetic hard disk drives have undergone vast technological improvements since their introduction as storage devices over 45 years ago, and these improvements have had a marked influence on how disk drives are applied and what they can do. Areal density increases have exceeded the traditional semiconductor development trajectory and have yielded higher-capacity, higher-performance, and smaller-form-factor disk drives, enabling desktop and mobile computers to store multi-gigabytes of data easily. Server systems containing large numbers of drives have achieved unparalleled reliability, performance, and storage capacity. All of these characteristics have been achieved at rapidly declining disk costs. This paper relates advances in disk drives to corresponding trends in storage systems and projects where these trends may lead in the future.
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paper_title: 512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

paper_content:

A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-/spl mu/m CMOS substrate. One-time programming is performed by applying a high voltage across the cell terminals, which ruptures the antifuse and permanently encodes a logic 0. Unruptured antifuses encode a logic 1. Cells are arranged in 8-Mb tiles, 1 K rows by 1 K columns by 8 bits high. The die contains 72 such tiles: 64 tiles for data and eight tiles for error-correcting code bits. Wordline and bitline decoders, bias circuits, and sense amplifiers are built in the CMOS substrate directly beneath the memory tiles, improving die efficiency. The device supports a generic standard NAND flash interface and operates from a single 3.3-V supply.
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paper_title: The micro to nano addressing block (MNAB)

paper_content:

Over the past few years, a number of techniques, including self-assembly, nanoimprint lithography and spacer-based frequency doubling, have been explored to pattern line and space structures that are considerably denser than possible with conventional photolithography, with excellent critical dimension control. In order to build useful circuits with them, an efficient way of interfacing these nanoscale lines with the photolithographically defined peripheral circuits is needed. While many solutions to this problem have been proposed, for the first time, we report a solution (MNAB) that is (a) fully silicon-process compatible, (b) non-stochastic (i.e. is completely deterministic,) and (c) does not require any critical alignment. The MNAB uses discrete analog potentials to deplete and switch off certain nanoscale lines enabling selection of the remaining nanoscale line. Simulation results show that individual nanoscale silicon lines can be addressed with selectivities (ratio of current in conducting line to that in depleted lines) exceeding 100times at features as small as 10 nm using this concept. Experimental results on various silicon prototypes show that selectivities exceeding 100times can be easily obtained even on sub-20 nm features
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paper_title: Multilevel flash cells and their trade-offs

paper_content:

In this paper we compare six different multilevel flash cells, viz., common ground, DINOR, AND, AMG, split gate and NAND. The key conclusions are that the hot electron effect lends itself better than tunneling as the multilevel programming mechanism. The common ground cell is the most suitable for multilevel flash cells. The NAND architecture is the least favorable.
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paper_title: Effects of floating-gate interference on NAND flash memory cell operation

paper_content:

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V/sub T/ shift of a cell proportional to the V/sub T/ change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-/spl mu/m design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors.
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paper_title: Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

paper_content:

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.
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paper_title: A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory

paper_content:

The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.
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paper_title: Future Outlook of NAND Flash Technology for 40nm Node and Beyond

paper_content:

The NAND flash memory occupied 40% of the total flash memory market with an annual growth rate of 70% in 2004, while NOR flash achieved only more modest growth rate of 30%. It is expected that NAND flash will surpass the market share of NOR flash in the flash market for the first time in 2005. From the viewpoint of market trend, NAND flash will be more popular in future because of more diversified applications such as NHDD (NAND-HDD) and sub-notebook PC storage. In this paper, we review the critical barriers in further scaling down NAND flash to 40nm technology node and beyond. Then, breakthrough technologies are addressed to overcome the barriers. In addition, issues in performance and reliability of the high density NAND flash are discussed
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paper_title: Data retention behavior of a SONOS type two-bit storage flash memory cell

paper_content:

Data retention loss mechanisms in a 2-bit SONOS type flash EEPROM cell with hot electron programming and hot hole erase are investigated. In erase (low-Vt) state, a threshold voltage drift with storage time is observed after P/E cycling stress. Positive trapped charge creation in the bottom oxide is found to be responsible for the drift. In program (high-Vt) state, data retention loss is attributed mostly to nitride charge escape by Frenkel-Poole emission and oxide trap assisted tunneling. A square-root dependence of the nitride charge loss on electric field is obtained. A Vg-acceleration method for retention lifetime measurement is proposed.
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paper_title: On the go with SONOS

paper_content:

Advancements in scaling gate insulators for MOS transistors permit low-voltage, silicon-oxide-nitride-silicon (SONOS) nonvolatile semiconductor memories (NVSMs) for a wide range of applications. The continued scaling of SONOS devices offers improved performance with a small cell size, single-level polysilicon with low voltage, fast erase/write, improved memory retention, increased endurance, and radiation hardness. In this article, we discuss scaled SONOS devices, SONOS memory technology, and some SONOS NVSM applications.
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paper_title: Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory

paper_content:

A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si3N4/Al2O3/Si3N4 (NAN) was adopted as a trap layer in place of single Si3N4 layer in TANOS structure (Y. Shin et al., 2005). Compared to the reference structure of single Si3N4 trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10 V), which is ideal for multi-level application. In addition, highly reliable operation is obtained due to lower program/erase voltages, superior endurance, and smaller room/high temperature pre-/post-cycling charge loss (DeltaVth <0.5 V).
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paper_title: Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

paper_content:

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 /spl mu/m design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.
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paper_title: 4-Bit Double SONOS Memories (DSMs) Using Single-Level and Multi-Level Cell Schemes

paper_content:

In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The VTH shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention
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paper_title: Technology for sub-50nm DRAM and NAND flash manufacturing

paper_content:

This paper discusses whether memory technologies can continue advances beyond sub-50nm node especially for DRAM and NAND flash memories. First, the barriers to shrink technology are addressed for DRAM and NAND flash memories, depending on their inherent operation principles. Then, details of technology solutions are introduced and its manufacturability is examined. Beyond 30nm node, It is expected that 3-dimensional transistor scheme is needed for both logic and memory array in addition to the development of new materials and structural technologies
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paper_title: Multilevel flash cells and their trade-offs

paper_content:

In this paper we compare six different multilevel flash cells, viz., common ground, DINOR, AND, AMG, split gate and NAND. The key conclusions are that the hot electron effect lends itself better than tunneling as the multilevel programming mechanism. The common ground cell is the most suitable for multilevel flash cells. The NAND architecture is the least favorable.
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paper_title: Integration of lead zirconium titanate thin films for high density ferroelectric random access memory

paper_content:

Interests are being focused on types of nonvolatile memories such as ferroelectric random access memory (FRAM), phase change random access memory, or magnetoresistance random access memory due to their distinct memory properties such as excellent write performance which conventional nonvolatile memories do not possess. Among these types of nonvolatile memories, FRAM whose cell structure and operation are almost identical to dynamic random access memory (DRAM) can ideally realize cell size and speed of DRAM. Thus FRAM is the most appropriate candidate for future universal memory where all memory functions are performed with a single chip solution. Due to the poor ferroelectric properties of downscaled ultrathin lead zirconium titanate (PZT) capacitors as well as technical issues such as hydrogen and plasma related degradation arising from embedding ferroelectric metal-insulator-metal capacitors into conventional complementary metal oxide semiconductor processes, current FRAM still falls far below its ideal...
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paper_title: Integration of lead zirconium titanate thin films for high density ferroelectric random access memory

paper_content:

Interests are being focused on types of nonvolatile memories such as ferroelectric random access memory (FRAM), phase change random access memory, or magnetoresistance random access memory due to their distinct memory properties such as excellent write performance which conventional nonvolatile memories do not possess. Among these types of nonvolatile memories, FRAM whose cell structure and operation are almost identical to dynamic random access memory (DRAM) can ideally realize cell size and speed of DRAM. Thus FRAM is the most appropriate candidate for future universal memory where all memory functions are performed with a single chip solution. Due to the poor ferroelectric properties of downscaled ultrathin lead zirconium titanate (PZT) capacitors as well as technical issues such as hydrogen and plasma related degradation arising from embedding ferroelectric metal-insulator-metal capacitors into conventional complementary metal oxide semiconductor processes, current FRAM still falls far below its ideal...
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paper_title: A NOVEL ATE (ADDITIONAL TOP-ELECTRODE) SCHEME FOR A 1.6 V FRAM EMBEDDED DEVICE AT 180 NM TECHNOLOGY

paper_content:

ABSTRACT We developed a 1.6 V FRAM embedded device by successfully implementing a 100 nm MOCVD-PZT capacitor with a SrRuO3 electrode and a novel additional top electrode (ATE). ATE was used for preventing hydrogen-reduction damage or metal substance damage, arising from direct application of Al or W to top electrode. In spite of excellent reliability and wide sensing window of the memory, we found that there was a problem of lift-off of the ATE layer after full integration, leading to bit failure of the product. In order to eliminate the lift-off, we developed a new ATE scheme not only by using a compressive capping- oxide layer but by improving conformal deposition of ATE. The failed bits that appear as a tail of charge distribution were cleared even under a reliability test, a bake for 100 hours at 150°C. As a result, yield loss of the device was greatly reduced.
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paper_title: Why is nonvolatile ferroelectric memory field-effect transistor still elusive?

paper_content:

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.
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paper_title: High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics

paper_content:

The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.
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paper_title: Full-Bit Functional, High-Density 8 Mbit One Transistor–One Capacitor Ferroelectric Random Access Memory Embedded within a Low-Power 130 nm Logic Process

paper_content:

We report the electrical properties of a full-bit functional 8 Mbit one transitor–one capacitor (1T–1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm 5 lm Cu interconnect complementary metal oxide semiconductor (CMOS) logic process. To increase manufacturability and reliability margins, we have introduced a single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements leading to an increased signal margin. Further, we have fabricated a digital signal processor (DSP) using the eFRAM process flow and have shown that the operating frequency is nearly the same relative to the CMOS baseline. With the development of logic-compatible eFRAM, we have created a technology platform that enables ultra-low-power devices.
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paper_title: Ferroelectric thin films: Review of materials, properties, and applications

paper_content:

An overview of the state of art in ferroelectric thin films is presented. First, we review applications: microsystems' applications, applications in high frequency electronics, and memories based on ferroelectric materials. The second section deals with materials, structure (domains, in particular), and size effects. Properties of thin films that are important for applications are then addressed: polarization reversal and properties related to the reliability of ferroelectric memories, piezoelectric nonlinearity of ferroelectric films which is relevant to microsystems' applications, and permittivity and loss in ferroelectric films-important in all applications and essential in high frequency devices. In the context of properties we also discuss nanoscale probing of ferroelectrics. Finally, we comment on two important emerging topics: multiferroic materials and ferroelectric one-dimensional nanostructures. (c) 2006 American Institute of Physics.
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paper_title: A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor

paper_content:

The ferroelectric field effect has successfully been demonstrated on a bulk semiconductor (silicon) using a thin ferroelectric film of bismuth titanate (Bi 4 Ti 3 O 12 ) deposited onto it by RF sputtering. A new memory device, the metal-ferroelectric-semiconductor transistor (MFST); has been fabricated. This device utilizes the remanent polarization of a ferroeletric thin film to control the surface conductivity of a bulk semiconductor substrate and perform a memory function. The capacitance-voltage characteristics of the metal-ferroelectric-semiconductor structure were employed to study the memory behavior. The details of the study together with a preliminary results on the MFST are presented.
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paper_title: A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion

paper_content:

A novel SPRAM (spin-transfer torque RAM) consisting of MgO-barrier-based magnetic tunnel junctions (MTJs) with a synthetic ferrimagnetic (SyF) structure in a free layer was demonstrated for both higher immunity to read disturbance and a sufficient margin between the read and write currents. Since magnetization of the free layer becomes stable against thermal fluctuation with increasing thermal-stability factor E/kBT, the SyF free layer of the MTJs realized a magnetic information retention of over 10 years due to its high E/kBT of 67. Furthermore, it was found that the SyF free layer has an advantage of reducing dispersion of write-current density Jc, which is necessary for securing an adequate margin between the read and write currents.
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paper_title: Thermally assisted switching in exchange-biased storage layer magnetic tunnel junctions

paper_content:

A thermally assisted writing procedure is proposed in a tunnel junction based magnetic random access memory cell. The magnetic layers of the tunnel junction are both exchange-biased with antiferromagnetic layers, the reference layer having a much higher blocking temperature than the storage layer. In the operating mode, a current pulse sent through the junction generates enough heat to raise the temperature of the storage layer above its blocking temperature, without affecting the pinning of the reference layer. The concept is demonstrated here for an isolated junction using an homogeneous external magnetic field.
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paper_title: Resonant Amplification of Magnetic Domain-Wall Motion by a Train of Current Pulses

paper_content:

The current-induced motion of magnetic domain walls confined to nanostructures is of interest for applications in magnetoelectronic devices in which the domain wall serves as the logic gate or memory element. The injection of spin-polarized current below a threshold value through a domain wall confined to a pinning potential results in its precessional motion within the potential well. We show that by using a short train of current pulses, whose length and spacing are tuned to this precession frequency, the domain wall's oscillations can be resonantly amplified. This makes possible the motion of domain walls with much reduced currents, more than five times smaller than in the absence of resonant amplification.
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paper_title: Magnetically engineered spintronic sensors and memory

paper_content:

The discovery of enhanced magnetoresistance and oscillatory interlayer exchange coupling in transition metal multilayers just over a decade ago has enabled the development of new classes of magnetically engineered magnetic thin-film materials suitable for advanced magnetic sensors and magnetic random access memories. Magnetic sensors based on spin-valve giant magnetoresistive (GMR) sandwiches with artificial antiferromagnetic reference layers have resulted in enormous increases in the storage capacity of magnetic hard disk drives. The unique properties of magnetic tunnel junction (MTJ) devices has led to the development of an advanced high performance nonvolatile magnet random access memory with density approaching that of dynamic random-access memory (RAM) and read-write speeds comparable to static RAM. Both GMR and MTJ devices are examples of spintronic materials in which the flow of spin-polarized electrons is manipulated by controlling, via magnetic fields, the orientation of magnetic moments in inhomogeneous magnetic thin film systems. More complex devices, including three-terminal hot electron magnetic tunnel transistors, suggest that there are many other applications of spintronic materials.
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paper_title: Current-driven excitation of magnetic multilayers

paper_content:

Abstract A new mechanism is proposed for exciting the magnetic state of a ferromagnet. Assuming ballistic conditions and using WKB wave functions, we predict that a transfer of vectorial spin accompanies an electric current flowing perpendicular to two parallel magnetic films connected by a normal metallic spacer. This spin transfer drives motions of the two magnetization vectors within their instantaneously common plane. Consequent new mesoscopic precession and switching phenomena with potential applications are predicted.
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paper_title: Technological impact of magnetic hard disk drives on storage systems

paper_content:

Magnetic hard disk drives have undergone vast technological improvements since their introduction as storage devices over 45 years ago, and these improvements have had a marked influence on how disk drives are applied and what they can do. Areal density increases have exceeded the traditional semiconductor development trajectory and have yielded higher-capacity, higher-performance, and smaller-form-factor disk drives, enabling desktop and mobile computers to store multi-gigabytes of data easily. Server systems containing large numbers of drives have achieved unparalleled reliability, performance, and storage capacity. All of these characteristics have been achieved at rapidly declining disk costs. This paper relates advances in disk drives to corresponding trends in storage systems and projects where these trends may lead in the future.
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paper_title: MRAM Memory for Embedded and Stand Alone Systems

paper_content:

Magnetoresistive random access memory (MRAM) is based on magnetic tunnel junction devices integrated with standard CMOS resulting in high-speed read and write, unlimited endurance, and the highest reliability of any non-volatile memory. MRAM is a unique memory technology in that the module is inserted late in the manufacturing process, making MRAM highly compatible with advanced processing. The manufacturing flexibility of MRAM makes it an attractive choice for embedded and stand alone memory systems.
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paper_title: Tunneling between ferromagnetic films

paper_content:

Abstract FeGeCo junctions conductance G(V) is studied when mean magnetizations of the two ferromagnetic film are parrallel or antiparallel. Conductance measurement, in these two cases, is related to the spin polarizations of the conduction electrons.
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paper_title: Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology

paper_content:

Fully functional 512Mb PRAM with 0.047mum2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC
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paper_title: A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications

paper_content:

A 90nm technology node phase change memory (PCM) process, based on a chalcogenide material storage element with a vertical pnp bipolar junction transistor (BJT) selector device, is presented. The small cell area of 12F2, the good electrical results, and the intrinsic reliability demonstrate the viability of the PCM cell concept. Programming currents as low as 400muA, very good distributional data achieved on multi-megabit arrays for programming (set and reset), endurance, and retention, demonstrate the suitability of PCM for fabrication of a high density array at 90nm
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paper_title: Ultra-Thin Phase-Change Bridge Memory Device Using GeSb

paper_content:

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention
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paper_title: Phase-change random access memory: A scalable technology

paper_content:

Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm × 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.
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paper_title: Scaling analysis of phase-change memory technology

paper_content:

The scaling capability of chalcogenide-based phase-change memory (PCM) is discussed. Experimental and numerical results are presented, showing that the reset current scales down with the device contact area, reaching values as low as 50 /spl mu/A. The impact of thermal cross-talk between adjacent bits is investigated, showing that thermal disturbs will not limit the scaling of PCM down to the 65 nm technology node. Finally, scaling rules for the PCM technology are provided.
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paper_title: A Highly Reliable Self-Aligned Graded Oxide WOx Resistance Memory: Conduction Mechanisms and Reliability

paper_content:

WOx formed by plasmas oxidation shows promising multi-bit/cell resistance memory characteristics (ChiaHua Ho et al., 2007). The simple memory is completely self-aligned, requiring no additional masks and has a small 6F2 cell size. In this work we introduce a graded oxide device that is highly reliable (250degC baking for > 2,000 hrs). The conduction mechanism and factors affecting the memory reliability are examined extensively.
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paper_title: Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses

paper_content:

Simple binary-TMO (transition metal oxide) resistive random access memory named as OxRRAM has been fully integrated with 0.18/spl mu/m CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300/spl deg/C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2/spl mu/m/sup 2/.
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paper_title: Non-volatile resistive switching for advanced memory applications

paper_content:

A non-volatile resistive switching mechanism based on trap-related space-charge-limited-conduction (SCLC) is proposed. Excellent memory characteristics have been demonstrated using near-stoichiometric cuprous oxide (CuxO) metal-insulator-metal (MIM) structures: low-power operation, fast switching speed, superior temperature characteristics, and long retention. This MIM memory cell is fully compatible with standard CMOS process. The proposed switching mechanism is a strong contender for high density and low cost memory applications
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paper_title: Characterization of silver-saturated Ge–Te chalcogenide thin films for nonvolatile random access memory

paper_content:

Programmable metallization cell structure with a device diameter of 2μm composed of Ag–Ge–Te chalcogenide films was prepared by a cosputtering technique at room temperature. The device with a 150nm thick Ag30(Ge0.3Te0.7)70 electrolyte switches at 0.2V from an “off” state resistance Roff close to 106Ω to an “on” resistance state Ron more than four orders of magnitude lower for this programming current. The switching characteristics were closely related with a diffusion of silver anode into silver-saturated GeTe electrolyte films.
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paper_title: Reproducible unipolar resistance switching in stoichiometric ZrO2 films

paper_content:

The resistance switching characteristics of stoichiometric ZrO2 film were investigated for nonvolatile memory. The Al∕ZrO2∕Al device presents reliable and reproducible switching behaviors. The on/off ratio of two stable states is larger than 2×103. It is suggested that the current-voltage characteristics are governed by the Schottky conduction mechanism in high voltage region, while the filament conduction is suggested in low voltage region. The switching process is explained in terms of the spontaneous reversible reaction between electrode and ZrO2 films with the contribution of Joule heating effect by the external current. It provides a possible solution for low device yield of nonstoichiometric oxides.
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paper_title: Reproducible switching effect in thin oxide films for memory applications

paper_content:

Thin oxide films with perovskite or related structures and with transition metal doping show a reproducible switching in the leakage current with a memory effect. Positive or negative voltage pulses can switch the resistance of the oxide films between a low- and a high-impedance state in times shorter than 100 ns. The ratio between these two states is typically about 20 but can exceed six orders of magnitude. Once a low-impedance state has been achieved it persists without a power connection for months, demonstrating the feasibility of nonvolatile memory elements. Even multiple levels can be addressed to store two bits in such a simple capacitor-like structure.
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paper_title: Nanoscale memory elements based on solid-state electrolytes

paper_content:

We report on the fabrication and characterization of nanoscale memory elements based on solid electrolytes. When combined with silver, chalcogenide glasses such as Se-rich Ge-Se are good solid electrolytes, exhibiting high Ag ion mobility and availability. By placing an anode that has oxidizable Ag and an inert cathode (e.g., Ni) in contact with a thin layer of such a material, a device is formed that has an intrinsically high resistance, but which can be switched to a low-resistance state at small voltage via reduction of the silver ions. An opposite bias will return the device to a high-resistance state, and this reversible switching effect is the basis of programmable metallization cell technology. In this paper, electron beam lithography was used to make sub-100-nm openings in polymethylmethacrylate layers used as the dielectric between the device electrodes. The solid electrolyte film was formed in these via-holes so that their small diameter defined the active switching area between the electrodes. The Ag-Ge-Se electrolyte was created by the photodiffusion, with or without thermal assistance, of an Ag layer into the Ge-Se base glass. Combined thermal and photodiffusion leads to a nanophase separated material with a dispersed Ag ion-rich material with an average crystallite size of 7.5 nm in a glassy insulating Ge-rich continuous phase. The nanoscale devices write at an applied bias as low as 0.2 V, erase by -0.5 V, and fall from over 10/sup 7/ /spl Omega/ to a low-resistance state (e.g., 10/sup 4/ /spl Omega/ for a 10-/spl mu/A programming current) in less than 100 ns. Cycling appears excellent with projected endurance well beyond 10/sup 11/ cycles.
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paper_title: Excellent uniformity and reproducible resistance switching characteristics of doped binary metal oxides for non-volatile resistance memory applications

paper_content:

We have investigated various doped metal oxides such as copper doped molybdenum oxide, copper doped Al2O3, copper doped ZrO2, alumimum doped ZnO, and CuxO for novel resistance memory applications. Compared with non-stoichiometric oxides (Nb2O5-x, ZrOx, SrTiOx), doped metal oxides show higher device yield. Moreover, Cu: MoOx have demonstrated excellent memory characteristics such as reliability under programming cycles, potential multi-bit operation, good data retention, highly scalable property, and fast switching speed. The switching mechanism of the copper doped molybdenum oxide can be explained by the generation and rupture of multi-filaments under the electrical stress.
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paper_title: Low-Power Switching of Nonvolatile Resistive Memory Using Hafnium Oxide

paper_content:

Nonstoichiometric hafnium oxide (HfOx) resistive-switching memory devices with low-power operation have been demonstrated. Polycrystalline HfOx (O:Hf=1.5:1) films with a thickness of 20 nm are grown on a titanium nitride (TiN) bottom electrode by commercial atomic layer deposition. Platinum (Pt) as a top electrode is used in the memory device. Voltage-induced resistance switching is repeatedly observed in the Pt/HfOx/TiN/Si memory device with resistance ratio is greater than 10. During the switching cycles, the power consumptions for high- and low-resistance states are found to be 0.25 and 0.15 mW, respectively. At 85 °C, the memory device shows stable resistance switching and superior data retention with resistance ratio is greater than 100. In addition, our memory device shows little area dependence of resistance-switching behavior. The anodic electrode containing noble metal Pt serves an important role in maintaining stable resistance switching. The resistance switching in the HfOx films is thought to be due to the defects that are generated by the applied bias. The nonstoichiometric HfOx films are responsible for the low SET and RESET currents during switching. Our study shows that the HfOx resistive-switching memory is a promising candidate for next-generation nonvolatile memory device applications.
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paper_title: Resistive switching mechanism of TiO2 thin films grown by atomic-layer deposition

paper_content:

The resistive switching mechanism of 20- to 57-nm-thick TiO2 thin films grown by atomic-layer deposition was studied by current-voltage measurements and conductive atomic force microscopy. Electric pulse-induced resistance switching was repetitively (> a few hundred times) observed with a resistance ratio ⪢102. Both the low- and high-resistance states showed linear log current versus log voltage graphs with a slope of 1 in the low-voltage region where switching did not occur. The thermal stability of both conduction states was also studied. Atomic force microscopy studies under atmosphere and high-vacuum conditions showed that resistance switching is closely related to the formation and elimination of conducting spots. The conducting spots of the low-resistance state have a few tens times higher conductivity than those of the high-resistance state and their density is also a few tens times higher which results in a ∼103 times larger overall conductivity. An interesting finding was that the area where the ...
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paper_title: Resistance switching of copper doped MoOx films for nonvolatile memory applications

paper_content:

Nonvolatile and reversible resistance switching of copper doped MoOx film was studied. Hysteretic-type resistive switching was observed under dc. Reproducible resistance switching over 106cycles was observed under alternative voltage pulses. Two resistance states can be maintained for 25h at 85°C. The authors proved that resistance switching might be strongly related with the rupture and generation of multifilaments confirmed by spreading resistance images of a conducting atomic force microscope as well as filamentary conduction by double logarithmic plots. Based on the x-ray photoelectron spectroscopy analysis, local conducting filaments could be formed by thermally diffused copper into MoOx film from the bottom electrode.
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paper_title: Programmable metallization cell memory based on Ag-Ge-S and Cu-Ge-S solid electrolytes

paper_content:

Programmable metallization cell (PMC) memory is based on the electrochemical growth and removal of nanoscale metallic pathways in thin films of solid electrolyte. Our previous studies concentrated on electrolytes formed from silver-doped germanium selenide glasses but these materials are not able to withstand the temperatures used in standard back-end-of-line processing for the fabrication of CMOS integrated circuits. This paper concerns our more recent work on silver-doped germanium sulfide electrolytes and describes the electrical characteristics of PMC devices made from these materials following annealing at 300 degC and 430 degC. We also present results from devices that use copper in place of silver as this metal is currently used in integrated circuit interconnect
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paper_title: Switching properties of thin Nio films

paper_content:

Abstract This paper describes a two-terminal solid-state switch made from a thin film of nickel oxide. The switch has a typical OFF resistance of 10–20 MΩ and a typical ON resistance of 100–200 Ω. Switching times are in the 0·1–10 μsec range. The switching action is thought to be due to the formation and rupture of a nickel filament in the NiO matrix. The formation process is such that after about 100–1000 switching cycles, the devices to be described fail ‘short’; i.e. they cannot be switched out of the ON condition with normal switching signal amplitudes. Several experiments which elucidate the switching mechanism and the terminal properties of the device are described.
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paper_title: High-Speed Resistive Switching of TiO2/TiN Nano-Crystalline Thin Film

paper_content:

High-speed resistive switching was observed in a TiO2/TiN nano-crystalline thin film sandwiched between platinum electrodes. A low resistance state was achieved by applying a single negative 2.0-V amplitude 20-ns wide electric pulse, while a high resistance state was achieved by applying a single positive 2.2-V amplitude 30-ns wide electric pulse. So-called forming process, heating bit material by current flow to form conductive filament path before the resistive switching operation was not required. There was an approximately 40,000% increase in resistive change that was repeatedly obtained in the system.
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paper_title: Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter

paper_content:

In this paper, we fabricated 1T1R NiO-ReRAM test circuits based on 0.18 mum CMOS technology and observed notable suppression of Ireset by imposing current compliance Icomp using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. This enabled the systematic measurement of Icomp dependence of lreset for Icomp < 1 mA and Ireset ap Icomp was observed for 150 muA les Icomp les950 muA.
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paper_title: Mechanism for bistability in organic memory elements

paper_content:

We demonstrate that the resistive switching phenomenon observed in organic semiconductor layers containing granular metal particles conforms to a charge storage mechanism described by Simmons and Verderber [Proc. R. Soc. A 391, 77 (1967)]. The space-charge field due to the stored charge inhibits further charge injection from the electrodes. The equilibrium current–voltage curve is N shaped and the low and high resistance states are obtained by applying voltage close to the local maximum and minimum, respectively.
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paper_title: A model for filament growth and switching in amorphous oxide films

paper_content:

Abstract The forming process, by which changes are brought about in the electronic conduction of thin films of various binary amorphous oxides and halides, is first described, and experimental evidence is put forward which contradicts an earlier theory of the forming process in gold-silicon monoxide-metal structures. A theory is developed, in terms of the growth and thermal rupture of many conducting filaments through the insulating layer, to explain the observed voltage controlled negative resistance, electron emission, electroluminescence and memory phenomena. The model is presented firstly in its simplest phenomenological form, after which some atomic mechanisms which may be involved are tentatively discussed. It is further shown that there is evidence to suggest that the forming process in important in a wide range of systems. These include metal-oxide-silicon capacitors and transistors, surface-barrier junctions on silicon, oxide-coated thermionic cathodes and anodic oxide layers. Electronic conduction in each of these cases is held to take place through localized filamentary paths. The relationship between this and other filamentary conduction models is briefly discussed, and a general classification of negative-resistance devices into regenerative and non-regenerative systems is made.
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paper_title: Electronic memory effects in a sexithiophene - poly(ethylene oxide) block copolymer doped with NaCl. combined diode and resistive switching behavior

paper_content:

Electrical transport in devices consisting of an electrode of a conducting polymer (poly(ethylenedioxythiophene):poly(styrenesulfonate), PEDOT:PSS); a layer of a sexithiophene−poly(ethylene oxide) (6T-PEO) block copolymer with an Al top electrode is investigated. These devices show diode behavior with the larger current density flowing when the PEDOT:PSS electrode is biased positive with respect to the Al electrode (forward bias). Introduction of inorganic salt (NaCl) in the PEDOT layer results in resistive switching behavior under forward bias while retaining the diode character. The switching allows for storage of information and rewritable memory operation is demonstrated for the diodes although the retention time of the information is still very short (∼10 s). The reported combination of switching and diode behavior is an important requirement for passive matrix addressing of resistive switching memory cells in an array and shows that materials with combined ion and charge transport properties are int...
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paper_title: Key to design functional organic molecules for binary operation with large conductance switching

paper_content:

We have selected a new class of material which shows presence of large conductance switching. The acceptor groups present in the molecules result in low OFF-state current in the devices and hence large ON/OFF ratio of 100,000. The ON-state in the molecules has been due to conjugation restoration via electroreduction. The ON/OFF ratio decreased to 4 in devices based on molecules without any acceptor groups. The devices have undergone 'write-read-erase-read' sequence for hours, showing their applicability in random-access-memory elements.
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paper_title: New conduction and reversible memory phenomena in thin insulating films

paper_content:

It has been observed that when thin (200 to 3000 A) film insulators have been formed by the electrolytic introduction of gold ions from one of the electrodes they can draw appreciable currents. They then show temperature-independent conductivity, voltage-controlled negative resistance and reversible voltage and thermal-voltage memory effects. It is postulated that the injected ions introduce a broad band of localized impurity levels within the normally forbidden band of the insulator. The electrons are assumed to move through the insulator by tunnelling between adjacent sites within the impurity band; it is also assumed that the electrons can, under certain conditions, be trapped within the impurity band. A model based on these ideas accounts in a self-consistent manner for all the experimental observations, and calculations of current-voltage characteristics based on the model are in fact in agree­ment with them.
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paper_title: Electrical switching and memory phenomena in Cu-TCNQ thin films

paper_content:

Stable and reproducible current‐controlled bistable electrical switching has been observed in polycrystalline organic semiconducting films. The effect has been observed in a lamellar structure with a film of microcrystalline Cu‐TCNQ between Cu and Al electrodes where the Cu‐TCNQ is grown on a Cu substrate via a spontaneous electrolysis technique. The switching effect is insensitive to moisture and is observed over a large temperature range. The current‐voltage characteristics reveal an abrupt decrease in impedance from 2 MΩ to less than 200 Ω at a field strength of 4×103 V/cm. The transition from a high‐ to low‐impedance state occurs with delay and switching times of approximately 15 and 10 nsec, respectively. Switching with high‐power dissipation yields a low‐impedance memory state which can be erased by application of a short current pulse. An interpretation of this behavior is based on the bulk properties of the mixed valence semiconductor Cu‐TCNQ.
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paper_title: Organic Materials and Thin-Film Structures for Cross-Point Memory Cells Based on Trapping in Metallic Nanoparticles

paper_content:

Non-volatile solid-state memory cells based on composites of metal nanoparticles and polymers are embedded in organic semiconducting host materials. This paper presents data from a wide range of materials and device structures and shows that the switching phenomenon is commonly observed.
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paper_title: Electrical bistability and memory phenomenon in carbon nanotube-conjugated polymer matrixes.

paper_content:

We have observed electrical bistability and large conductance switching in functionalized carbon nanotube (CNT)-conjugated polymer composites at room temperature. The concentration of the CNTs in the polymer matrix controlled the degree of bistability. Conduction mechanism applicable in each of the conducting states has been identified. The switching had an associated memory phenomenon and was reversible in nature. In the bistable devices, the active layer retained its high-conducting state until a reverse voltage erased it. We could "write" or "erase" a state and "read" it for many cycles for random-access memory applications.
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paper_title: Nonvolatile Memory Elements Based on Organic Materials

paper_content:

Many organic electronic devices exhibit switching behavior, and have therefore been proposed as the basis for a nonvolatile memory (NVM) technology. This Review summarizes the materials that have been used in switching devices, and describes the variety of device behavior observed in their charge-voltage (capacitive) or current-voltage (resistive) response. A critical summary of the proposed charge-transport mechanisms for resistive switching is given, focusing particularly on the role of filamentary conduction and of deliberately introduced or accidental nanoparticles. The reported device parameters (on-off ratio, on-state current, switching time, retention time, cycling endurance, and rectification) are compared with those that would be necessary for a viable memory technology.
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paper_title: SECONDARY COULOMB BLOCKADE GAP IN A FOUR-ISLAND TUNNEL-JUNCTION ARRAY

paper_content:

In the ring-shaped tunnel-junction array with four islands, the secondary Coulomb blockade gap in a low bias-voltage range is observed in the I-V characteristics. We attribute its appearance to the unique topology of the array which induces up to two electrons to get trapped inside. We have analyzed the formation and destruction of the gap in terms of detailed single-electron tunneling processes. The negative differential resistance behavior when the thermal and quantum fluctuations are present is also studied.
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paper_title: Electrical Switching and Bistability in Organic/Polymeric Thin Films and Memory Devices

paper_content:

Recently, films created by incorporating metallic nanoparticles into organic or polymeric materials have demonstrated electrical bistability, as well as the memory effect, when subjected to an electrical bias. Organic and polymeric digital memory devices based on this bistable electronic behavior have emerged as a viable technology in the field of organic electronics. These devices exhibit fast response speeds and can form multiple-layer stacking structures, demonstrating that organic memory devices possess a high potential to become flexible, ultrafast, and ultrahigh-density memory devices. This behavior is believed to be related to charge storage in the organic or polymer film, where devices are able to exhibit two different states of conductivity often separated by several orders of magnitude. By defining the two states as “1” and “0”, it is now possible to create digital memory devices with this technology. This article reviews electrically bistable devices developed in our laboratory. Our research has stimulated strong interest in this area worldwide. The research by other laboratories is reviewed as well.
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paper_title: Polymer dielectric films

paper_content:

Polymer dielectric films, ranging in thickness from less than 100 A to several microns, have become increasingly useful for basic investigations of surface phenomena and thin film electrical conductivity and for thin film electronic device and circuit development. The preparation and characterizing properties of thin polymer films are discussed with particular emphasis on recent developments in such areasa s ultraviolet surface photolysis, electron bombardment, gaseous electrical discharge, and special chemical processes. Previously unpublished data on certain aspects of polymer dielectric films are presented, and present and potential applications are briefly reviewed.
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paper_title: Memory effect in the current–voltage characteristic of a low-band gap conjugated polymer

paper_content:

Diodes formed by electrodeposition of the low-band gap polymer poly(4-dicyano methylene-4H-cyclopenta[2,1-b:3,4-b′]dithiophene), onto glass slides coated with indium tin oxide (ITO) and furnished with evaporated aluminum counterelectrodes exhibit a reversible bistability in their current–voltage (I–V) characteristics. Applying +5 V to the ITO electrode induces a “high” conductance state while applying −5 V induces a “low” conductance state. The effect is identical in most respects to recent observations in diodes formed from thin films of chromium-doped SrZrO3 sandwiched between SrRuO3 and gold electrodes. A number of mechanisms are discussed but the evidence points to the controlling influence of an interfacial depletion layer at the ITO–polymer interface. It is also shown that the high capacitances associated with such layers can lead to higher than expected displacement currents being generated during the automated collection of I–V data. The presence of such currents distorts the I–V characteristics i...
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paper_title: Why is nonvolatile ferroelectric memory field-effect transistor still elusive?

paper_content:

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.
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paper_title: Ultra-Thin Phase-Change Bridge Memory Device Using GeSb

paper_content:

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention
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paper_title: Current-driven excitation of magnetic multilayers

paper_content:

Abstract A new mechanism is proposed for exciting the magnetic state of a ferromagnet. Assuming ballistic conditions and using WKB wave functions, we predict that a transfer of vectorial spin accompanies an electric current flowing perpendicular to two parallel magnetic films connected by a normal metallic spacer. This spin transfer drives motions of the two magnetization vectors within their instantaneously common plane. Consequent new mesoscopic precession and switching phenomena with potential applications are predicted.
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paper_title: A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor

paper_content:

The ferroelectric field effect has successfully been demonstrated on a bulk semiconductor (silicon) using a thin ferroelectric film of bismuth titanate (Bi 4 Ti 3 O 12 ) deposited onto it by RF sputtering. A new memory device, the metal-ferroelectric-semiconductor transistor (MFST); has been fabricated. This device utilizes the remanent polarization of a ferroeletric thin film to control the surface conductivity of a bulk semiconductor substrate and perform a memory function. The capacitance-voltage characteristics of the metal-ferroelectric-semiconductor structure were employed to study the memory behavior. The details of the study together with a preliminary results on the MFST are presented.
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Title: Overview of Candidate Device Technologies for Storage-Class Memory

Section 1: Introduction
Description 1: Provide an introduction to Moore's Law and the economic cycle it triggered. Discuss the current limitations of flash memory and the opportunity for alternative nonvolatile memory (NVM) technologies to emerge.

Section 2: SCM
Description 2: Discuss the concept of Storage-Class Memory (SCM) and the significance of integrating high-performance, high-density, and low-cost NVM technologies into the memory-storage hierarchy.

Section 3: Flash and other charge-trapping memory
Description 3: Outline the structure and function of conventional flash memory, including NOR and NAND flash types. Discuss the scaling challenges and potential of charge-trapping memory technologies like SONOS and nanocrystal flash.

Section 4: Ferroelectric RAM
Description 4: Explain the principles behind ferroelectric RAM (FeRAM), its advantages, scaling challenges, and various device structures for improving memory performance.

Section 5: Magnetic RAM
Description 5: Describe the technology behind Magnetic RAM (MRAM), key breakthroughs like the magnetic tunnel junction (MTJ), and issues such as high write currents and scaling limitations.

Section 6: Phase-change RAM
Description 6: Explore Phase-change RAM (PCRAM), its operation based on resistance contrast between amorphous and crystalline states, and its scaling potential and integration challenges.

Section 7: Resistive RAM and solid-electrolyte memory
Description 7: Discuss the mechanism and materials used in Resistive RAM (RRAM) and solid-electrolyte (SE) memory, including their advantages, switching phenomena, and current limitations.

Section 8: Organic and polymeric memory
Description 8: Review the diverse mechanisms and materials involved in organic and polymeric memory technologies, along with their advantages and integration challenges.

Section 9: Summary and outlook
Description 9: Summarize the prospects of each candidate NVM technology, their ability to meet scalability, performance, and endurance requirements, and the potential for achieving a universal memory solution.