Software Defined Radio Architecture Survey for Cognitive Testbeds
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paper_title: Software radios-survey, critical evaluation and future directions

paper_content:

Relates the performance of enabling hardware technologies to software radio requirements, portending a decade of shift from hardware radios toward software intensive approaches. Such approaches require efficient use of computational resources through topological consistency of radio functions and host architectures. This leads to a layered topology oriented design approach encapsulated in a canonical open architecture software radio model. This model underscores challenges in simulation and computer-aided design (CAD) tools for radio engineering. It aso provides a unified mathematical framework for quantitative analysis of algorithm structures, host architectures, and system performance for radio engineering CAD environments of the 1990s.<<ETX>>
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paper_title: Future Software-Defined Radio Platforms and Mapping Flows

paper_content:

A software-defined radio (SDR) system is a radio communication system in which physical layer components are implemented on a programmable or reconfigurable platform. The modulation and demodulation is performed in software and thus the radio is able to support a broad ran: of frequencies and functions concurrently. In the ideal SDR transceiver scheme, an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) are attached to the antenna. This would imply that a digital signal processor (DSP) is connected to the ADC and the DAC, directly performing signal processing for the streams of data from/to antenna. Today, the ideal SDR transceiver scheme is still not feasible and thus some processing has to happen in the reconfigurable analog front end.
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paper_title: Software Defined Radio: Challenges and Opportunities

paper_content:

Software Defined Radio (SDR) may provide flexible, upgradeable and longer lifetime radio equipment for the military and for civilian wireless communications infrastructure. SDR may also provide more flexible and possibly cheaper multi-standard-terminals for end users. It is also important as a convenient base technology for the future context-sensitive, adaptive and learning radio units referred to as cognitive radios. SDR also poses many challenges, however, some of them causing SDR to evolve slower than otherwise anticipated. Transceiver development challenges include size, weight and power issues such as the required computing capacity, but also SW architectural challenges such as waveform application portability. SDR has demanding implications for regulators, security organizations and business developers.
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paper_title: Sora: high-performance software radio using general-purpose multi-core processors

paper_content:

This paper presents Sora, a fully programmable software radio platform on commodity PC architectures. Sora combines the performance and fidelity of hardware software-defined radio (SDR) platforms with the programmability and flexibility of general-purpose processor (GPP) SDR platforms. Sora uses both hardware and software techniques to address the challenges of using PC architectures for high-speed SDR. The Sora hardware components consist of a radio front-end for reception and transmission, and a radio control board for high-throughput, low-latency data transfer between radio and host memories. Sora makes extensive use of features of contemporary processor architectures to accelerate wireless protocol processing and satisfy protocol timing requirements, including using dedicated CPU cores, large low-latency caches to store lookup tables, and SIMD processor extensions for highly efficient physical layer processing on GPPs. Using the Sora platform, we have developed a few demonstration wireless systems, including SoftWiFi, an 802.11a/b/g implementation that seamlessly interoperates with commercial 802.11 NICs at all modulation rates, and SoftLTE, a 3GPP LTE uplink PHY implementation that supports up to 43.8Mbps data rate.
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paper_title: Software Defined Radio: Challenges and Opportunities

paper_content:

Software Defined Radio (SDR) may provide flexible, upgradeable and longer lifetime radio equipment for the military and for civilian wireless communications infrastructure. SDR may also provide more flexible and possibly cheaper multi-standard-terminals for end users. It is also important as a convenient base technology for the future context-sensitive, adaptive and learning radio units referred to as cognitive radios. SDR also poses many challenges, however, some of them causing SDR to evolve slower than otherwise anticipated. Transceiver development challenges include size, weight and power issues such as the required computing capacity, but also SW architectural challenges such as waveform application portability. SDR has demanding implications for regulators, security organizations and business developers.
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paper_title: A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals

paper_content:

The increasing number of radio protocols along with the need for multimedia support in mobile communication devices call for heterogeneous, programmable multi-core processors. In this paper, we present a fully programmable, heterogeneous single chip SDR platform with multimedia support, fabricated in a 0.13 mum CMOS process. Running at 175 MHz, a peak performance of 40 GOPS is delivered while dissipating 1.5 W. The typical MPSoC programmability problem is solved with a dedicated hardware unit which performs dynamic spatial and temporal mapping of tasks onto processing elements.
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paper_title: From SODA to scotch: The evolution of a wireless baseband processor

paper_content:

With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly changing wireless communication landscape. Software defined radio (SDR) promises to deliver a cost effective and flexible solution by implementing a wide variety of wireless protocols in software. In previous work, a fully programmable multicore architecture, SODA, was proposed that was able to meet the real-time requirements of 3G wireless protocols. SODA consists of one ARM control processor and four wide single instruction multiple data (SIMD) processing elements. Each processing element consists of a scalar and a wide 512-bit 32-lane SIMD datapath. A commercial prototype based on the SODA architecture, Ardbeg (named after a brand of Scotch whisky), has been developed. In this paper, we present the architectural evolution of going from a research design to a commercial prototype, including the goals, tradeoffs, and final design choices. Ardbegpsilas redesign process can be grouped into the following three major areas: optimizing the wide SIMD datapath, providing long instruction word (LIW) support for SIMD operations, and adding application-specific hardware accelerators. Because SODA was originally designed with 180 nm technology, the wide SIMD datapath is re-optimized in Ardbeg for 90 nm technology. This includes re-evaluating the most efficient SIMD width, designing a wider SIMD shuffle network, and implementing faster SIMD arithmetic units. Ardbeg also provides modest LIW support by allowing two SIMD operations to issue in the same cycle. This LIW execution supports SDR algorithmspsila most common parallel SIMD execution patterns with minimal hardware overhead. A viable commercial SDR solution must be competitive with existing ASIC solutions. Therefore, algorithm-specific hardware is added for performance bottleneck algorithms while still maintaining enough flexibility to support multiple wireless protocols. The combination of these architectural improvements allows Ardbeg to achieve 1.5-7x speedup over SODA across multiple wireless algorithms while consuming less power.
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paper_title: DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

paper_content:

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare dataflow for scheduling. Architecture abstraction generates an internal graph representation from a concrete architecture description. A modulo scheduling algorithm is key to exploit parallelism and achieve high performance. The experimental results show up to 28.7 instructions per cycle (IPC) over tested kernels.
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paper_title: SODA: A Low-power Architecture For Software Radio

paper_content:

The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or software defined radio, has a number of advantages. These include support for multiple protocols, faster time-to-market, higher chip volumes, and support for late implementation changes. The challenge is to achieve this without sacrificing power. In this paper, we present a design study for a fully programmable architecture, SODA, that supports software defined radio a high-end signal processing application. Our design achieves high performance, energy efficiency, and programmability through a combination of features that include single-instruction multiple- data (SIMD) parallelism, and hardware optimized for 16bit computations. The basic processing element is an asymmetric processor consisting of a scalar and SIMD pipeline, and a set of distributed scratchpad memories that are fully managed in software. Results show that a four processor design is capable of meeting the throughput requirements of theW-CDMA and 802.11a protocols, while operating within the strict power constraints of a mobile terminal.
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paper_title: The sandbridge SB3011 platform

paper_content:

This paper describes the Sandbridge Sandblaster real-time software-defined radio platform. Specifically, we describe the SB3011 system-on-a-chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. Each processor core achieves 600MHz at 0.9V operation while typically dissipating 75mW in 90nm technology. The entire chip typically dissipates less than 500mW at 0.9V.
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paper_title: A Low-Power Multithreaded Processor for Baseband Communication Systems

paper_content:

Embedded digital signal processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, these processors should be compiler-friendly, so that code for them can quickly be developed in a high-level language. This paper presents the design of a high-performance, low-power digital signal processor for baseband communication systems. The processor uses token triggered threading, SIMD vector processing, and powerful compound instructions to provide real-time baseband processing capabilities with very low power consumption. Using a super-computer class vectorizing compiler, the processor achieves real-time performance on a 2Mbps WCDMA transmission system.
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paper_title: Software-Defined Radio Prospects for Multistandard Mobile Phones

paper_content:

A multitude of existing and evolving cell phone standards, coupled with the need to react quickly to market requirements, is radically changing the system architect's task.Two alternative approaches to classic ASIC-centered and DSP-assisted designs have emerged: reconfigurable architectures and DSP-centered and accelerator-assisted architectures.
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paper_title: Architecture and implementation of a Software-Defined Radio baseband processor

paper_content:

The architecture and implementation of a Software Defined Radio (SDR) multi-standard baseband processor are presented. As the first representative of a new SDR baseband family, the X-GOLDTM SDR20 has been successfully designed and fabricated in a 65nm CMOS process. The physical layer signal processing for GSM, EDGE, GPRS, UMTS, HSPA, GMR1-3G, and LTE can be implemented in software on this single-chip device. Respective GSM, UMTS and LTE lab demonstrations have proven the competitiveness of this SDR approach.
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paper_title: Vector Processing as an Enabler for Software-Defined Radio in Handheld Devices

paper_content:

A major challenge of software-defined radio (SDR) is to realize many giga operations per second of flexible baseband processing within a power budget of only a few hundred mW. A heterogeneous hardware architecture with the programmable vector processor EVP as key component can support WLAN, UMTS, and other standards. A detailed rationale for the EVP architecture, based on the analysis of a number of key algorithms, as well as implementation and benchmarking results are described.
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paper_title: KUAR: A Flexible Software-Defined Radio Development Platform

paper_content:

In this paper, we present the details of a portable, powerful, and flexible software-defined radio development platform called the Kansas University Agile Radio (KUAR). The primary purpose of the KUAR is to enable advanced research in the areas of wireless radio networks, dynamic spectrum access, and cognitive radios. The KUAR hardware implementation and software architecture are discussed in detail. Radio configurations and applications are presented. Future research made possible by this flexible platform is also discussed.
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paper_title: Single-Chip Baseband Signal Processor for Software-Defined Radio

paper_content:

Reconfigurable processor technology offers a way to couple significant hardware performance improvements with realtime software signal processing. This technology enables software-defined radio (SDR) to be realized on a system-on-a-chip (SoC) platform. In this paper, we describe an SDR SoC LSI that is suitable for use in programmable wireless communication systems. The LSI has two advanced features. First, the hybrid architecture consists of reconfigurable signal processors and accelerator circuits. These accelerators are parametric circuits essential for baseband processing. Second, the reconfigurable processing elements have a cluster structure that improves the mapping efficiency and minimizes the processing time. We also describe a prototype SDR system that uses this LSI to perform software-defined IEEE802.11a and 11 b communications.
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paper_title: A 200Mbps+ 2.14nJ/b digital baseband multi processor system-on-chip for SDRs

paper_content:

This paper describes the implementation of an energy-efficient digital SDR baseband platform. The multi processor system-on-chip (MPSOC) is implemented in 90nm CMOS technology and occupies 32mm2. It incorporates all digital signal processing required by the physical layer of the WiFi(802.11n), WiMax(802.16e), mobile TV and 3GPP-LTE standards. The heterogeneous architecture with hierarchical wake-up achieves 5mW idle time power, is capable of delivering a net data rate in excess of 200Mbps and consumes 231mW during 108Mbps WLAN 2×2 MIMO Rx, achieving 2.14nJ/b energy efficiency.
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paper_title: Future Software-Defined Radio Platforms and Mapping Flows

paper_content:

A software-defined radio (SDR) system is a radio communication system in which physical layer components are implemented on a programmable or reconfigurable platform. The modulation and demodulation is performed in software and thus the radio is able to support a broad ran: of frequencies and functions concurrently. In the ideal SDR transceiver scheme, an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) are attached to the antenna. This would imply that a digital signal processor (DSP) is connected to the ADC and the DAC, directly performing signal processing for the streams of data from/to antenna. Today, the ideal SDR transceiver scheme is still not feasible and thus some processing has to happen in the reconfigurable analog front end.
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paper_title: Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques

paper_content:

This paper presents the ANR project IDROMel, which aims at developing reconfigurable SDR (Software Defined Radio) and Cognitive Radio (CR) equipments. IDROMel is a 3 years project that started in 2005 and finishes in 2009. The main objective of IDROMel is to define, develop and validate a powerful SDR and CR platform combining very last technology progresses. The platform includes software parts (reconfigurable protocol stacks) and hardware parts (a base band board and a Radio Frequency Front end, RF). Both parts are presented in this paper.)
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paper_title: Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem

paper_content:

Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power consumption and low cost. With the rapid evolution of telecom standards and the increasing demand for multi-standard products, the need for flexible baseband solutions is growing. The concept of Multi-Processor System-on-Chip (MPSoC) is well adapted to enable hardware reuse between products and between multiple wireless standards in the same device. Heterogeneous architectures are well known solutions but they have limited flexibility. Based on the experience of two heterogeneous Software Defined Radio (SDR) telecom chipsets, this paper presents the homoGENEous Processor arraY (GENEPY) platform for 4G applications. This platform is built with Smart ModEm Processors (SMEP) interconnected with a Network-on-Chip. The SMEP, implemented in 65nm low-power CMOS, can perform 3.2 GMAC/s with 77 GBits/s internal bandwidth at 400MHz. Two implementations of homogeneous GENEPY are compared to a heterogeneous platform in terms of silicon area, performance and power consumption. Results show that a homogeneous approach can be more efficient and flexible than a heterogeneous approach in the context of 4G Mobile Terminals.
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paper_title: An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application

paper_content:

Advanced telecommunication applications require more and more flexibility. Static and run-time configuration mechanisms, as well as plug-in computing units are two solutions to solve this issue. In this paper, we propose an open architec- ture, dedicated to complex data-flow applications, fulfilling these requirements thanks to a distributed configuration scheme and a standard interface for data flow computing units. Based on this architecture, an open platform demonstrator has been designed. Simulation results on a 3GPP/LTE application are presented, showing a reconfiguration time overhead of only 2.6%.
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paper_title: XiSystem: a XiRisc-based SoC with reconfigurable IO module

paper_content:

In the nanometer era, the increase in nonrecurring engineering costs is a challenge for SoCs that can be faced through a standardization process. Hardware specialization of a standard platform to a given application can be achieved by exploiting reconfigurable technology. This paper presents a XiSystem SoC, which integrates two different field-programmable devices to provide application-specific computing blocks and IOs. A XiRisc reconfigurable processor is exploited to achieve more than one order of magnitude speed-up and energy consumption reduction vis-a/spl grave/-vis a DSP-like processor, while an eFPGA is integrated in the system in order to make it flexible enough to support various IO ports and protocols. The reconfigurable IO device is also utilized for pre/post data processing and implementation of some standard computational blocks.
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paper_title: Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem

paper_content:

Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power consumption and low cost. With the rapid evolution of telecom standards and the increasing demand for multi-standard products, the need for flexible baseband solutions is growing. The concept of Multi-Processor System-on-Chip (MPSoC) is well adapted to enable hardware reuse between products and between multiple wireless standards in the same device. Heterogeneous architectures are well known solutions but they have limited flexibility. Based on the experience of two heterogeneous Software Defined Radio (SDR) telecom chipsets, this paper presents the homoGENEous Processor arraY (GENEPY) platform for 4G applications. This platform is built with Smart ModEm Processors (SMEP) interconnected with a Network-on-Chip. The SMEP, implemented in 65nm low-power CMOS, can perform 3.2 GMAC/s with 77 GBits/s internal bandwidth at 400MHz. Two implementations of homogeneous GENEPY are compared to a heterogeneous platform in terms of silicon area, performance and power consumption. Results show that a homogeneous approach can be more efficient and flexible than a heterogeneous approach in the context of 4G Mobile Terminals.
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paper_title: A 167-Processor Computational Platform in 65 nm CMOS

paper_content:

A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock frequency scaling, three algorithm-specific processors, and three 16 KB shared memories; and is implemented in 65 nm CMOS. All processors and shared memories are clocked by local fully independent, dynamically haltable, digitally-programmable oscillators and are interconnected by a configurable circuit-switched network which supports long-distance communication. Programmable processors occupy 0.17 mm 2 and operate at a maximum clock frequency of 1.2 GHz at 1.3 V. At 1.2 V, they operate at 1.07 GHz and consume 47.5 mW when 100% active, resulting in an energy dissipation of 44 pJ per operation. At 0.675 V, they operate at 66 MHz and consume 608 μW when 100% active, resulting in a total energy dissipation of 9.2 pJ per ALU or MAC operation.
---
paper_title: An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application

paper_content:

Advanced telecommunication applications require more and more flexibility. Static and run-time configuration mechanisms, as well as plug-in computing units are two solutions to solve this issue. In this paper, we propose an open architec- ture, dedicated to complex data-flow applications, fulfilling these requirements thanks to a distributed configuration scheme and a standard interface for data flow computing units. Based on this architecture, an open platform demonstrator has been designed. Simulation results on a 3GPP/LTE application are presented, showing a reconfiguration time overhead of only 2.6%.
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paper_title: Software defined baseband processing for 3G base stations

paper_content:

There is much discussion on devices for signal processing based on novel architectures for 3G base stations. The paper discusses how parallel architectures can be applied to demanding signal processing systems, based around the case-study of a real design of a 64 channel 3G (WCDMA) base station. It also considers the "total cost" of such a development.
---
paper_title: Future Software-Defined Radio Platforms and Mapping Flows

paper_content:

A software-defined radio (SDR) system is a radio communication system in which physical layer components are implemented on a programmable or reconfigurable platform. The modulation and demodulation is performed in software and thus the radio is able to support a broad ran: of frequencies and functions concurrently. In the ideal SDR transceiver scheme, an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) are attached to the antenna. This would imply that a digital signal processor (DSP) is connected to the ADC and the DAC, directly performing signal processing for the streams of data from/to antenna. Today, the ideal SDR transceiver scheme is still not feasible and thus some processing has to happen in the reconfigurable analog front end.
---
paper_title: An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application

paper_content:

Advanced telecommunication applications require more and more flexibility. Static and run-time configuration mechanisms, as well as plug-in computing units are two solutions to solve this issue. In this paper, we propose an open architec- ture, dedicated to complex data-flow applications, fulfilling these requirements thanks to a distributed configuration scheme and a standard interface for data flow computing units. Based on this architecture, an open platform demonstrator has been designed. Simulation results on a 3GPP/LTE application are presented, showing a reconfiguration time overhead of only 2.6%.
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paper_title: Open-source SCA-based core framework and rapid development tools enable software-defined radio education and research

paper_content:

This article describes the Open Source SCA Implementation::Embedded project, an open source software development kit designed for rapid prototyping of software defined radios consistent with the software communications architecture. The SCA is a product of the American military's SDR acquisition program and has played a large role in SDR development in the military and in the wireless industry. OSSIE was designed for use in wireless communications curricula and research efforts, so it is easy to learn and illustrative of software engineering, programming, and communications engineering concepts important in industrial practice today. OSSIE includes a core framework (i.e., common services enumerated in the SCA). It also includes graphical user interface-oriented tools that are easily learned and free to download and use. The tools auto-generate SCA-specific component source code and supporting files, leaving the developer to provide signal processing functionality. In addition, visualization tools for debugging and a growing library of SDR software components are available. Discussed herein are examples of SDRs designed using OSSIE, including embedded applications. OSSIE enables easy transition from concepts to practice in SDR design for communications engineers who may not have a strong software background.
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Title: Software Defined Radio Architecture Survey for Cognitive Testbeds

Section 1: INTRODUCTION
Description 1: This section introduces the concept of software radio technology and the motivation for studying SDR architectures, particularly for cognitive radio testbeds.

Section 2: SDR TECHNOLOGY
Description 2: This section explains the tiers of SDR defined by the SDR Forum, the components involved in building an SDR terminal, and their relevance to cognitive radio.

Section 3: SURVEY OF HARDWARE PLATFORMS FOR SDR
Description 3: This section categorizes existing SDR hardware platforms and describes each category in detail, including examples and their respective characteristics.

Section 4: ANALYSIS
Description 4: This section provides a comparative analysis of the surveyed SDR hardware platforms, summarizing their main characteristics and suitability for different applications.

Section 5: Cortexlab
Description 5: This section discusses the development of the CortexLab cognitive radio testbed in Lyon, explaining its objectives, design choices, and how it differs from other testbeds.

Section 6: CONCLUSION
Description 6: This section summarizes the findings from the survey, concluding with insights into platform trends and the selected approaches for developing an efficient cognitive radio testbed.