NanoMagnet Logic: an Architectural Level Overview
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paper_title: Theoretical study of molecular quantum dot cellular automata

paper_content:

Molecular quantum-dot cellular automata (QCA) is an alternative paradigm for molecular electronics. Each single molecule acts as a QCA cell and binary information is encoded in the configuration of charge among redox-active molecular sites. Coulomb interaction between neighboring molecules provides information transport from one molecule to another, so the heat dissipation is low because no current through molecular circuits is needed. In this paper, we present a quantum-chemistry ab initio analysis of these two QCA candidates. For Trans-Ru(dppm)/sub 2/(C=CFc)(NCCH/sub 2/CH/sub 2/NH/sub 2/) dication, our calculation confirms a bistable charge configuration in which the binary information can be encoded. The ferrocence and Ru(dppm)/sub 2/ groups are two natural quantum dots in the molecule. The carbon-carbon triple bond connecting these two dots provides the tunneling junction for a mobile electron. Driven by an external electric field, the mobile electron can move from one dot to the other, resulting in an abrupt change of dipole moment. The critical driven field is determined by the energy difference of the bistable states and the effect of counterions as well. Our calculations qualitatively explain the experimental observations.
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paper_title: Towards a molecular QCA wire: simulation of write-in and read-out systems

paper_content:

Abstract Among emerging beyond CMOS technologies Molecular Quantum Dot Cellular Automata (MQCA) are estimated as extremely promising for computational purposes. The elementary nanoelectronic devices are molecular systems in which the binary encoding is provided by the charge localization within a molecule. As a consequence, there is no current flowing among the cells and power dissipation is dramatically reduced. We study a new real molecule that was synthesized ad hoc for this technology. Differently with respect to previous contributions, this study has the aim of assessing the realistic properties of this molecule in a perspective experimental system based on a molecular wire principle. We use a combination of ab initio calculations and molecular dynamics simulations and analyze the molecule behavior when specific electric fields are applied to move the electrons inside the molecule in order to force a logic state. Our results allowed us (i) to asses the molecule behavior and to explore the working points of our experimental system for the write-in, (ii) to introduce in this scenario new metrics for studying and using these new devices from an electronic point of view, (iii) to give a perspective and to define design constraints for possible experimental solutions eligible for issue of molecule state read-out.
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paper_title: UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2

paper_content:

The increased leakage, yield inefficiency, process, power supply, and temperature variations have significant aftereffects on the performance of complex VLSI architectures especially if mapped on ultra deep sub micrometer (UDSM) technologies. In this paper we assess the technology trend based on three industrial technologies (90, 65, and 45 nm) using a state of the art processor as benchmark: The UltraSparc Niagara 2 from SUN Microsystem. We analyze frequency, dynamic, and static power and area after synthesis varying power supply voltage and temperature. We then compare these exhaustive analyses of system level performance as a function of technology to ITRS device level estimations. The results suggest that this prediction can be of help when addressing both the technological scaling and the variability scenario of the selected technology. We believe that correctly predicting specific values on performance variations when realistic conditions and technologies are changed could provide a valuable information for the architect. Our analysis advises the designer on the effective applicability of the ITRS trends to system performance, but also pinpoints that a reliable system level prediction should better take into account the design complexity.
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paper_title: Magnetic Logic Devices Based on Field-Coupled Nanomagnets

paper_content:

Nanomagnets that exhibit two distinct stable states of magnetization can be used to store digital bits. This phenomenon is already applied in today’s magnetic random access memories (MRAM). In addition, interacting networks of such nanomagnets, with physical spacing on the order of 10 nm between them, have been proposed to propagate and process binary information by means of magnetic coupling. The application of field-coupled nanomagnets for digital logic circuits was described in a concept called magnetic quantumdot cellular automata (MQCA) [1][2]. MQCA offer very low power dissipation and high integration density of functional devices. In addition, it can operate over a wide temperature range from near absolute zero to the Curie temperature of the employed ferromagnetic material. We introduce a logic gate similar to that proposed by Parish and Forshaw [3], which performs majority-logic operation. The nanomagnets are arranged in a cross-geometry as shown in Fig. 1, where the dipole coupling between the nanomagnets produces ferromagnetic and antiferromagnetic ordering of the magnetic states. Consider that the magnetic state of nanomagnets A, B, and C can be set by some inputs, and that a horizontal external magnetic field, called the clock-field, can allow the system to relax to its ground state. Then, majority logic operation can be performed by the central nanomagnet M, and the result can be transferred to another nanomagnet labeled as “out”. The cross-geometry can be extended, and inputs can be provided by adding nanomagnets that are oriented along the clock-field. Varying the position of these horizontally elongated nanomagnets, all eight input combinations in the majority-logic truth table can be tested. Figure 1. (a) An elongated polycrystalline NiFe alloy nanomagnet exhibits two stable magnetic states in the direction of its longest axis. (b) Majority gate geometry built up from nanomagnets. We demonstrate room temperature operation of majority gates made of NiFe alloy and fabricated by electron-beam lithography on silicon. Dipolar ordering in the nanomagnetnetworks is imaged by magnetic force microscopy (MFM), and the operation is explained by means of micromagnetic simulations. Figure 2 introduces a particular majority gate, in which the magnetic state of A is set to be the opposite to that of B and C. In this gate, A, B, and C all exert torque on the central dot’s magnetic moment in the same direction. Simulations show that, as the clock-field is reduced, the switching of the nanomagnets inside the gate begins at the input dots. The central dot switches after A, B, and C, and the switching propagates along the antiferromagnetically-coupled chain to the right. The figure demonstrates the final states after two independent experiments, in which the clock-field was applied in opposite directions. The MFM data shows the correct alignment of the magnetic moments in both cases.
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paper_title: Clocked molecular quantum-dot cellular automata

paper_content:

Quantum-dot cellular automata (QCA) is an approach to computing that eliminates the need for current switches by representing binary information as the configuration of charge among quantum dots. For molecular QCA, redox sites of molecules serve as the quantum dots. The Coulomb interaction between neighboring molecules provides device-device coupling. By introducing clocked control of the QCA cell, power gain, reduced power dissipation, and computational pipelining can be achieved. We present an ab initio analysis of a simple molecular system, which acts as a clocked molecular QCA cell. The intrinsic bistability of the molecular charge configuration results in dipole or quadrupole fields that couple strongly to the state of neighboring molecules. We show how clocked control of the molecular QCA can be accomplished with a local electric field.
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paper_title: A technology aware magnetic QCA NCL-HDL architecture

paper_content:

Magnetic Quantum Dot Cellular Automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose a practicable clock structure for MQCA baptised “snake-clock”, we stick to this while developing a system level Hardware Description Language (HDL) based description of an architectural block, and we suggest a delay insensitive Null Convention LogicTM (NCL, [1]) implementation for the magnetic case so that the “layout=timing” problem can be solved. Furthermore we include in our model aspects critically related to technology and real production, that is timing, power and layout, and we present the preliminary steps of our experiments, the results of which will be included in the architecture description.
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paper_title: An NCL-HDL Snake-Clock-Based Magnetic QCA Architecture

paper_content:

The International Technology Roadmap of semiconductors suggests that quantum-dot cellular automata (QCA) technology might be a possible CMOS substitute. In particular, magnetic quantum-dot cellular automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented, and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level, we propose the use of delay insensitive null convention logic (NCL) . It is implemented for MQCA in order to solve the “layout=timing” problem in the specific case of MQCA. We, thus, describe an architectural block at system level using a hardware description language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called “snake clock,” proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore, we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase “snake-clock” NCL structure works correctly.
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paper_title: Clocking structures and power analysis for nanomagnet-based logic devices

paper_content:

Logical devices made from nano-scale magnets have many potential advantages - systems should be non-volatile, dense, low power, radiation hard, and could have a natural interface to MRAM. Initial work includes experimental demonstrations of logic gates and wires and theoretical studies that consider their power dissipation. This paper looks at power dissipation too, but also considers the circuitry needed to drive a computation. Initial results are very encouraging and indicate that clocked magnetic logic could - in the worst case - match equivalent low power CMOS circuits and - in the best-case - potentially provide more than 2 orders of magnitude improvement when one considers energy per operation.
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paper_title: Signal Processing with Near-Neighbor-Coupled Time-Varying Quantum-Dot Arrays

paper_content:

The Nano-Devices Group at the University of Notre Dame proposed a new device that encodes information in the geometrical charge distribution of artificial (or natural) molecules. Functional units are composed by electrostatic coupling. In these units, processing takes place by reshaping the electron density of the molecules, and not by switching currents. Signal processing potential of next-neighbor-coupled cellular nonlinear networks (CNNs) has been recently explored with the conclusion that local-activity of the cells is necessary to exhibit complexity. It will be shown that Coulomb-coupled time-invariant artificial molecules behave like nonlinear locally passive devices, thus signal-power-gain or multiple equilibria cannot be achieved by integrating them. However, the signal input-output relation of strongly nonlinear molecules can be varied in time by adiabatic pumping, called clock control. It will be shown that strongly nonlinear time-varying molecules can transform the necessary amount of clock energy into the signal flow, thereby enabling the network of molecules to perform signal processing.
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paper_title: Quantum cellular automata

paper_content:

The authors formulate a new paradigm for computing with cellular automata (CAS) composed of arrays of quantum devices-quantum cellular automata. Computing in such a paradigm is edge driven. Input, output, and power are delivered at the edge of the CA array only; no direct flow of information or energy to internal cells is required. Computing in this paradigm is also computing with the ground state. The architecture is so designed that the ground-state configuration of the array, subject to boundary conditions determined by the input, yields the computational result. The authors propose a specific realization of these ideas using two-electron cells composed of quantum dots. The charge density in the cell is very highly polarized (aligned) along one of the two cell axes, suggestive of a two-state CA. The polarization of one cell induces a polarization in a neighboring cell through the Coulomb interaction in a very non-linear fashion. Quantum cellular automata can perform useful computing. The authors show that AND gates, OR gates, and inverters can be constructed and interconnected.
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paper_title: Behavior of Nanomagnet Logic in the presence of thermal noise

paper_content:

We use numerical simulations to analyze the behavior of Nanomagnet Logic (NML) in the presence of room-temperature thermal fluctuations and discuss simple models to estimate temperature-induced error rates in these devices. Our calculations show that small NML gates — composed of sub-100 nm size dots — are sufficiently stable against temperature fluctuations, but thermal noise imposes design constraints for structures with long signal paths.
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paper_title: Nanomagnet logic: progress toward system-level integration.

paper_content:

Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, 'Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.' This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain--using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.
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paper_title: On-Chip Clocking for Nanomagnet Logic Devices

paper_content:

We report local control of nanomagnets that can be arranged to perform computation in a cellular automata-like architecture. This letter represents the first demonstration of deterministically placed quantum-dot cellular automata (QCA) devices (of any implementation), where devices are controlled by on-chip local fields.
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paper_title: Systolic Pattern Matching Hardware With Out-of-Plane Nanomagnet Logic Devices

paper_content:

We present the design and simulation of systolic information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic or oNML). The designed circuit can identify instances of a preprogrammed bit sequence in streaming data. The systolic architecture 1) exploits unique benefits of the oNML device architecture such as nonvolatility and inherently pipelined logic with no memory overhead for holding the bits in the pipeline and 2) mitigates less desirable features of oNML such as nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor. The designed layout is verified and analyzed by micromagnetic simulations. We quantify how the performance and energy of oNML information processing hardware compares to CMOS equivalents and conclude that the initial oNML design (including the overhead of magnetic field generation) is about an order of magnitude more power efficient at essentially iso-performance.
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paper_title: Magnetization dynamics, throughput and energy dissipation in a universal multiferroic nanomagnetic logic gate with fan-in and fan-out

paper_content:

The switching dynamics of a multiferroic nanomagnetic NAND gate with fan-in/fan-out is simulated by solving the Landau-Lifshitz-Gilbert (LLG) equation while neglecting thermal fluctuation effects. The gate and logic wires are implemented with dipole-coupled two-phase (magnetostrictive/piezoelectric) multiferroic elements that are clocked with electrostatic potentials of ~50 mV applied to the piezoelectric layer generating 10.1 MPa stress in the magnetostrictive layers for switching. We show that a pipeline bit throughput rate of ~0.5 GHz is achievable with proper magnet layout and sinusoidal four-phase clocking. The gate operation is completed in 2 ns with a latency of 4 ns. The total (internal + external) energy dissipated for a single gate operation at this throughput rate is found to be only ~500 kT in the gate and ~1250 kT in the 12-magnet array comprising two input and two output wires for fan-in and fan-out. This makes it respectively three and five orders of magnitude more energy-efficient than complementary-metal-oxide-semiconductor-transistor (CMOS)-based and spin-transfer-torque-driven nanomagnet-based NAND gates. Finally, we show that the dissipation in the external clocking circuit can always be reduced asymptotically to zero using increasingly slow adiabatic clocking, such as by designing the RC time constant to be three orders of magnitude smaller than the clocking period. However, the internal dissipation in the device must remain and cannot be eliminated if we want to perform fault-tolerant classical computing.
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paper_title: Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures

paper_content:

In this paper, we report magnetic quantum cellular automata (MQCA) realization using multi-layer cells with tilted polarizer reference layer with a particular focus on the critical need to shift toward the multi-layer cells as elemental entities from the conventional single-domain nanomagnets. We have reported a novel spin-transfer torque current-induced clocking scheme, theoretically derived the clocking current, and shown the reduction in power consumption achieved against the traditional mechanism of clocking using magnetic fields typically generated from overhead or underneath wires. We have modeled the multi-layer cell behavior in Verilog-A along with the underlying algorithm used in implementing the neighbor interaction between the cells. This paper reports the switching and clocking current magnitudes, their direction and the power consumption associated with switching and clocking operation. Finally, we present the simulation results from Verilog-A model of switching, clocking and neighbor interaction. Low power consumption due to spin transfer torque current induced switching and clocking along with the reasonable magneto-resistance (MR) distinguishing the two energy minimum states of the device, make these devices a promising candidate in MQCA realization.
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paper_title: A technology aware magnetic QCA NCL-HDL architecture

paper_content:

Magnetic Quantum Dot Cellular Automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose a practicable clock structure for MQCA baptised “snake-clock”, we stick to this while developing a system level Hardware Description Language (HDL) based description of an architectural block, and we suggest a delay insensitive Null Convention LogicTM (NCL, [1]) implementation for the magnetic case so that the “layout=timing” problem can be solved. Furthermore we include in our model aspects critically related to technology and real production, that is timing, power and layout, and we present the preliminary steps of our experiments, the results of which will be included in the architecture description.
---
paper_title: An NCL-HDL Snake-Clock-Based Magnetic QCA Architecture

paper_content:

The International Technology Roadmap of semiconductors suggests that quantum-dot cellular automata (QCA) technology might be a possible CMOS substitute. In particular, magnetic quantum-dot cellular automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented, and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level, we propose the use of delay insensitive null convention logic (NCL) . It is implemented for MQCA in order to solve the “layout=timing” problem in the specific case of MQCA. We, thus, describe an architectural block at system level using a hardware description language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called “snake clock,” proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore, we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase “snake-clock” NCL structure works correctly.
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paper_title: Study of single layer and multilayer nano-magnetic logic architectures

paper_content:

Nano-magnetic logic (NML) has been a promising technology for logic computation. Contribution of this paper is two-fold. First, we have fabricated and captured MFM images of a NML architecture that has computed the majority of seven variables. This logic block can potentially implement eight different logic functions that could be configured in real-time. Next, we have performed a set of experiments with a multilayer stack of Cot = 0.4 nm/Cut = 4 nm/Ni20Fe80t = 5 nm with a perpendicular magnetic anisotropy bottom layer to realize neighbor interaction between adjacent free layers of devices. Based on the MFM images, we conclude that dipolar coupling between the free layers of the neighboring spin-valve based NML (SVBN) devices can be exploited to construct local elements such as majority gates, inverters and interconnects. Since magnetic multilayer stacks have already been implemented in memory devices to read/write data, SVBN devices would not only solve the input/output problems in NML but also would hav...
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paper_title: Majority Voter Full Characterization for Nanomagnet Logic Circuits

paper_content:

The recently proposed Nanomagnet-based logic (NML) represents an innovative way to assemble electronic logic circuits. The low power consumption, combined with the possibility of maintaining the information stored without power supply, allows us to design low power digital circuits far beyond the limitations of CMOS technology. This paper is focused on the key logic block of NML, the majority voter (MV). It is thoroughly analyzed through detailed micromagnetic simulations, changing the geometrical parameters, and detecting logic behavior, timing performance, and energy dissipation. Our analysis enables us to derive important results, substantially enhancing the practical knowledge of NML. First, we demonstrate that NML circuits can be effectively fabricated not only using electron beam lithography, but also using high-end optical lithography without loosing performance. This is a promising opportunity for the future of this technology. Second, we demonstrate the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation. Third, we show how, and how much, the alteration of magnets sizes and distances affect timing and energy consumption. Finally, fourth, we outline the problematic fabrication of the gate with real clock wires, and propose a modification that enables the fabrication of working gates, remarkably enhancing the possibilities of this technology.
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paper_title: Heat dissipation bounds for nanocomputing: Theory and application to QCA

paper_content:

Computing circuits that implement logically irreversible operations unavoidably dissipate heat. The resulting dissipative costs, while insignificant in CMOS technology, may be dominant or even prohibitive in some dense, high speed post-CMOS nanocomputing approaches. This motivates determination of lower bounds on the dissipative cost of computation that can be applied to concrete nanocomputing technology proposals. In this work, we outline a general approach for the determination of such bounds and illustrate its application to a half adder circuit implemented in quantum cellular automata (QCA) controlled using both Landauer and Bennett clocking schemes that support pipelining. The resulting bounds on energy dissipation are used to compare lower bounds on power dissipation for the two clocking schemes at a fixed computational throughput. Potential application of our approach to assessment of post-CMOS nanocomputing technologies, both transistor-based and non-transistor based, is briefly discussed.
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paper_title: Shape Engineering for Controlled Switching With Nanomagnet Logic

paper_content:

We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets.
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paper_title: Nanomagnetic Logic Microprocessor: Hierarchical Power Model

paper_content:

The interest in emerging nanotechnologies has been recently focused on nanomagnetic logic (NML), which has unique appealing features. NML circuits have very low power consumption and, because of their magnetic nature, maintain the information safely stored even without power supply. The nature of these circuits is much different from that of CMOS circuits. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics; and 3) modeling performance aspects such as speed and power, together with logic behavior. In this paper, we present a very-high-speed integrated circuits HDL (VHDL) behavioral model for NML circuits, which allows the evaluation of not only the logic behavior but also its power dissipation. It is based on a technological solution called “snake-clock.” We demonstrate this model using a case study which offers the right variety of internal substructures to test the method: a 4-bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area, and power dissipation, which we evaluate using a benchmark division algorithm. The results highlight the flexibility and the efficiency of this model, as well as the remarkable improvements that it brings to the analysis of NML circuits.
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paper_title: Behavior of Nanomagnet Logic in the presence of thermal noise

paper_content:

We use numerical simulations to analyze the behavior of Nanomagnet Logic (NML) in the presence of room-temperature thermal fluctuations and discuss simple models to estimate temperature-induced error rates in these devices. Our calculations show that small NML gates — composed of sub-100 nm size dots — are sufficiently stable against temperature fluctuations, but thermal noise imposes design constraints for structures with long signal paths.
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paper_title: Clocking Schemes for Field Coupled Devices from Magnetic Multilayers

paper_content:

This paper introduces a clocking scheme that can be applied in magnetic field-coupled computing devices made from Co/Pt multilayers. The clocking wires are buried under the magnetic computing layer. Oscillating currents running through these wires generate an easy-axis field in the plane of the magnets. We show that this field can propagate signals between the magnetic dots and prevents frustration and splitting of the dots into multiple domains. We demonstrate our concept on a full micromagnetic simulation of an XOR gate. We argue that largescale logic devices could be built based on this architecture.
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paper_title: Nanomagnet logic: progress toward system-level integration.

paper_content:

Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, 'Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.' This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain--using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.
---
paper_title: Problems in designing with QCAs: Layout = Timing

paper_content:

SUMMARY The quantum cellular automata (QCA) is currently being investigated as an alternative to CMOS VLSI. While some simple logical circuits and devices have been studied, little if any work has been done in considering the architecture for systems of QCA devices. This work discusses the progress of one of the rst such eorts. Namely, the design of dataow components for a simple microprocessor being designed exclusively in QCA are discussed. Problems associated with initial designs and enumerated solutions to these problems (usually stemming from oorplanning techniques) are explained. Finally, areas of future research direction for circuit design in QCA are presented. Copyright ? 2001 John Wiley & Sons, Ltd.
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paper_title: Systolic Pattern Matching Hardware With Out-of-Plane Nanomagnet Logic Devices

paper_content:

We present the design and simulation of systolic information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic or oNML). The designed circuit can identify instances of a preprogrammed bit sequence in streaming data. The systolic architecture 1) exploits unique benefits of the oNML device architecture such as nonvolatility and inherently pipelined logic with no memory overhead for holding the bits in the pipeline and 2) mitigates less desirable features of oNML such as nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor. The designed layout is verified and analyzed by micromagnetic simulations. We quantify how the performance and energy of oNML information processing hardware compares to CMOS equivalents and conclude that the initial oNML design (including the overhead of magnetic field generation) is about an order of magnitude more power efficient at essentially iso-performance.
---
paper_title: An NCL-HDL Snake-Clock-Based Magnetic QCA Architecture

paper_content:

The International Technology Roadmap of semiconductors suggests that quantum-dot cellular automata (QCA) technology might be a possible CMOS substitute. In particular, magnetic quantum-dot cellular automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented, and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level, we propose the use of delay insensitive null convention logic (NCL) . It is implemented for MQCA in order to solve the “layout=timing” problem in the specific case of MQCA. We, thus, describe an architectural block at system level using a hardware description language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called “snake clock,” proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore, we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase “snake-clock” NCL structure works correctly.
---
paper_title: Problems in designing with QCAs: Layout = Timing

paper_content:

SUMMARY The quantum cellular automata (QCA) is currently being investigated as an alternative to CMOS VLSI. While some simple logical circuits and devices have been studied, little if any work has been done in considering the architecture for systems of QCA devices. This work discusses the progress of one of the rst such eorts. Namely, the design of dataow components for a simple microprocessor being designed exclusively in QCA are discussed. Problems associated with initial designs and enumerated solutions to these problems (usually stemming from oorplanning techniques) are explained. Finally, areas of future research direction for circuit design in QCA are presented. Copyright ? 2001 John Wiley & Sons, Ltd.
---
paper_title: Majority Voter Full Characterization for Nanomagnet Logic Circuits

paper_content:

The recently proposed Nanomagnet-based logic (NML) represents an innovative way to assemble electronic logic circuits. The low power consumption, combined with the possibility of maintaining the information stored without power supply, allows us to design low power digital circuits far beyond the limitations of CMOS technology. This paper is focused on the key logic block of NML, the majority voter (MV). It is thoroughly analyzed through detailed micromagnetic simulations, changing the geometrical parameters, and detecting logic behavior, timing performance, and energy dissipation. Our analysis enables us to derive important results, substantially enhancing the practical knowledge of NML. First, we demonstrate that NML circuits can be effectively fabricated not only using electron beam lithography, but also using high-end optical lithography without loosing performance. This is a promising opportunity for the future of this technology. Second, we demonstrate the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation. Third, we show how, and how much, the alteration of magnets sizes and distances affect timing and energy consumption. Finally, fourth, we outline the problematic fabrication of the gate with real clock wires, and propose a modification that enables the fabrication of working gates, remarkably enhancing the possibilities of this technology.
---
paper_title: Shape Engineering for Controlled Switching With Nanomagnet Logic

paper_content:

We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets.
---
paper_title: Nanomagnetic Logic Microprocessor: Hierarchical Power Model

paper_content:

The interest in emerging nanotechnologies has been recently focused on nanomagnetic logic (NML), which has unique appealing features. NML circuits have very low power consumption and, because of their magnetic nature, maintain the information safely stored even without power supply. The nature of these circuits is much different from that of CMOS circuits. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics; and 3) modeling performance aspects such as speed and power, together with logic behavior. In this paper, we present a very-high-speed integrated circuits HDL (VHDL) behavioral model for NML circuits, which allows the evaluation of not only the logic behavior but also its power dissipation. It is based on a technological solution called “snake-clock.” We demonstrate this model using a case study which offers the right variety of internal substructures to test the method: a 4-bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area, and power dissipation, which we evaluate using a benchmark division algorithm. The results highlight the flexibility and the efficiency of this model, as well as the remarkable improvements that it brings to the analysis of NML circuits.
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paper_title: Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

paper_content:

This paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in the design space are investigated, namely, network topology, parallelism degree, the rate at which messages are sent by processing nodes over the network, and routing strategy. The main results of this analysis are as follows: 1) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de Bruijn and generalized Kautz topologies and 2) depending on the throughput requirements, different parallelism degrees, message injection rates, and routing algorithms can be used to minimize the network area overhead.
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paper_title: Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders

paper_content:

The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree $dc$ up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magnetic.
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paper_title: Multidimensional systolic arrays for the implementation of discrete Fourier transforms

paper_content:

This paper presents an efficient technique for using a multidimensional systolic array to perform the multidimensional discrete Fourier transform (DFT). Extensions of the multidimensional systolic array suitable for fast Fourier transform (FFT) computations such as the prime-factor computation or the 2/sup n/-point decomposed computation of the one-dimensional (1-D) discrete Fourier transform are also presented. The essence of our technique is to combine two distinct types of semisystolic arrays into one truly systolic array. The resulting systolic array accepts streams of input data (i.e., it does not require any preloading), and it produces output data streams at the boundary of the array. No networks for intermediate spectrum transposition between constituent transforms are required. The systolic array has regular processing elements that contain a complex multiplier accumulator and a few registers and multiplexers. Simple and regular connections are required between the PEs.
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paper_title: QCA Systolic Matrix Multiplier

paper_content:

Quantum-dot Cellular Automata (QCA) technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. To explore the characteristics of QCA technology, digital circuit design approaches have been investigated. Due to the inherent wire delay in this technology, QCA appears to be suitable for pipelined architectures particularly. Systolic arrays take advantage of pipelining and parallelism. Therefore, an investigation into systolic array design in QCA technology is provided in this paper. A case study of the first systolic matrix multiplier is designed and analyzed. The results show that by applying the systolic array structure to QCA designs, significant benefits can be achieved particular with large systolic array size, even more so than when applied to CMOS-based technology. QCA has significant advantages in terms of speed and area over CMOS technology, for instance, a factor of 12 smaller in terms of the area in this proposed matrix multiplier design when compared with same CMOS 32nm implementation.
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paper_title: Mapping multiple algorithms into a reconfigurable systolic array

paper_content:

Systolic array is a well known VLSI architecture to achieve extensive parallel and pipelining computing. Many systolic designs have been reported. All are algorithm based, that is one design is only for solving one specific problem. In this paper, the special purpose systolic architecture has been extended into a reconfigurable one and a systematic design approach to mapping two or more algorithms into a single reconfigurable systolic array is presented. First multiple algorithms are mapped into a reconfigurable systolic array that is able to compute one algorithm at a time with proper control settings. Second the reconfigurable systolic array is extended by using time or space redundancy so that it can compute multiple algorithms simultaneously. In addition, the optimal mapping, which minimizes the total hardware cost and computation time, is explored and the necessary condition of the transformation for computing multiple problem instances is also proposed. According to this condition, the search space of finding the optimal mapping can be significantly reduced.
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paper_title: Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs

paper_content:

Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computationally intensive and are therefore excellent candidates for FPGA-based code acceleration. However, there is no standard form of these algorithms, they are used in a wide variety of situations with various constraints. It is therefore not practical to have a standard kernel that can be mapped to an FPGA, hence the importance of being able to compile such codes from a high level language. ROCCC is a C to VHDL compiler, which optimizes and parallelizes the most frequently executed kernel loops in applications such as in multimedia, scientific and high-performance computing. In this paper we describe the transformations performed by ROCCC, which transformed the kernel of the Smith-Waterman algorithm into a hardware systolic array that is mapped onto the FPGA on the SGI Altix RASC blade. We report a throughput increase by over 3,000times over a 2.8 GHz Xeon.
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paper_title: Design and comparison of NML systolic architectures

paper_content:

Nanomagnet Logic (NML) is a device architecture that utilizes the magnetization of nano-scale magnets to perform logical operations. NML has been experimentally demonstrated and operates at room temperature. Because the nanomagnets are non-volatile, as data flows through a circuit, it is inherently pipelined. This feature makes NML an excellent fit for systolic architectures, which could enable low-power, high-throughput systems that can address a variety of application-level tasks. When considering possible NML systolic systems, the underlying systolic clocking scheme affects both architectural design and performance. In this paper we explore these issues in the context of two NML designs for convolution. One design is based on a 3-phase clocking scheme and uni-directional dataflow, and another is based on a 2-phase clocking scheme and bi-directional dataflow. We compare the two NML systolic designs in terms of area, delay, and energy. We also compare the NML and CMOS implementations of the design in terms of energy and delay. Results are supported by physical level simulation.
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paper_title: A unified systolic array for discrete cosine and sine transforms

paper_content:

A linear systolic array for the discrete cosine transform, discrete sine transform, and their inverses is developed. It generates the transform kernel values recursively. Compared to the scheme with the transform kernel values prestored in memory either inside or outside each processing element, the clock period is shortened by a memory access time. In addition, the array pays no cost for prestorage. The systolic array has the advantages of pipelinability, regularity, locality, and scalability, making it quite suitable for VLSI signal processing. >
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paper_title: Systolic Arrays for (VLSI).

paper_content:

Abstract : A systolic system is a network of processors which rhythmically compute and pass data through the system. Physiologists use the work 'systole' to refer to the rhythmically recurrent contraction of the heart and arteries which pulses blood through the body. In a systolic computing system, the function of a processor is analogous to that of the heart. Every processor regularly pumps data in and out, each time performing some short computation, so that a regular flow of data is kept up in the network. Many basic matrix computations can be pipelined elegantly and efficiently on systolic networks having an array structure. As an example, hexagonally connected processors can optimally perform matrix multiplication. Surprisingly, a similar systolic array can compute the LU-decomposition of a matrix. These systolic arrays enjoy simple and regular communication paths, and almost all processors used in the networks are identical. As a result, special purpose hardware devices based on systolic arrays can be built inexpensively using the VLSI technology. (Author)
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paper_title: Multiscale modeling of cellular actin filaments: From atomistic molecular to coarse-grained dynamics

paper_content:

In this article, we present a computational multiscale model for the characterization of subcellular proteins. The model is encoded inside a simulation tool that builds coarse-grained (CG) force fields from atomistic simulations. Equilibrium molecular dynamics simulations on an all-atom model of the actin filament are performed. Then, using the statistical distribution of the distances between pairs of selected groups of atoms at the output of the MD simulations, the force field is parameterized using the Boltzmann inversion approach. This CG force field is further used to characterize the dynamics of the protein via Brownian dynamics simulations. This combination of methods into a single computational tool flow enables the simulation of actin filaments with length up to 400 nm, extending the time and length scales compared to state-of-the-art approaches. Moreover, the proposed multiscale modeling approach allows to investigate the relationship between atomistic structure and changes on the overall dynamics and mechanics of the filament and can be easily (i) extended to the characterization of other subcellular structures and (ii) used to investigate the cellular effects of molecular alterations due to pathological conditions.
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paper_title: Acceleration of coarse grain molecular dynamics on GPU architectures

paper_content:

Coarse grain (CG) molecular models have been proposed to simulate complex systems with lower computational overheads and longer timescales with respect to atomistic level models. However, their acceleration on parallel architectures such as graphic processing units (GPUs) presents original challenges that must be carefully evaluated. The objective of this work is to characterize the impact of CG model features on parallel simulation performance. To achieve this, we implemented a GPU-accelerated version of a CG molecular dynamics simulator, to which we applied specific optimizations for CG models, such as dedicated data structures to handle different bead type interactions, obtaining a maximum speed-up of on the NVIDIA GTX480 GPU with Fermi architecture. We provide a complete characterization and evaluation of algorithmic and simulated system features of CG models impacting the achievable speed-up and accuracy of results, using three different GPU architectures as case studies. © 2012 Wiley Periodicals, Inc.
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paper_title: Study of Dipolar Neighbor Interaction on Magnetization States of Nano-Magnetic Disks

paper_content:

We investigate the effect of magnetic neighbor interaction on the state behavior of nano-magnetic disks for data storage and computation applications. We have observed and verified that a nano-magnetic disk, with certain dimension, can exist either in the single domain state or in the vortex state depending on the edge-to-edge spacing between the nano-magnetic disks. The experiments were conducted by varying the diameters and thicknesses with respect to edge-to-edge spacing. The dimensions were based on the phase diagram between the single domain state and the vortex state. We have observed nano-magnetic disks spaced far apart from its neighbor, settled in the vortex state and coupled nano-magnetic disks with less spacing settled in the single domain state. This phenomenon was observed for nano-magnetic disks with thickness between 8 nm to 20 nm and diameters between 80 nm to 140 nm. We validated the simulation by fabricating pairs of nano-magnetic disks with a thickness of 10 nm and diameter of 110 nm along edge-to-edge spacing from 20 nm to 260 nm in steps of 20 nm.
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Title: NanoMagnet Logic: an Architectural Level Overview

Section 1: Introduction
Description 1: Provide an introduction to the fundamental concepts and importance of NanoMagnet Logic (NML) as compared to other Quantum dot Cellular Automata (QCA) implementations, including Molecular QCA.

Section 2: Designing Circuits With Clock Zones Constraints
Description 2: Discuss the central role of the clock mechanism in NML technology and the implications of different clock system topologies on circuit design and layout.

Section 3: Problems and Solutions
Description 3: Detail the key architectural problems (e.g., Layout=Timing, Loops, Interconnections) and potential solutions for these issues in NML circuits.

Section 4: Layout=Timing
Description 4: Explain the "layout=timing" problem and describe two potential solutions: the use of asynchronous logic and systematic clock zone layouts for automatic signal synchronization.

Section 5: Asynchronous Logic
Description 5: Describe the application of Null Convention Logic (NCL) and other asynchronous logic types to solve the "layout=timing" problem, including a detailed example with performance evaluation.

Section 6: Clock Zones Layout for Automatic Signals Synchronization
Description 6: Explore how strategic clock zone layout can help achieve automatic signal synchronization in complex circuits.

Section 7: Loops
Description 7: Analyze the challenges caused by loops in inherently pipelined circuits, including their impact on performance and signal synchronization, and provide architectural redesign solutions.

Section 8: Throughput Maximization
Description 8: Present methods to increase circuit throughput, such as data interleaving and architecture redesign to reduce loop lengths.

Section 9: Signals Synchronization
Description 9: Discuss synchronization strategies for nested loops and adding specific delays to certain signals to ensure correct operation in pipelined NML circuits.

Section 10: Interconnections
Description 10: Address the impact of interconnections on propagation delay and circuit area, and propose the use of systolic arrays to mitigate these issues.

Section 11: Systolic Arrays
Description 11: Describe the structure and benefits of systolic arrays, along with techniques for pipeline interleaving to enhance performance in NML circuits.

Section 12: Analysis of Applications Suited for NML Technology
Description 12: Identify application areas where NML technology's unique features (e.g., parallelism, locality, logic-in-memory, low power consumption, radiation resistance) can be fully exploited.

Section 13: Conclusions
Description 13: Summarize the main findings, challenges, and future research directions in the architectural analysis and system-level integration of NML technology.