A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems
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paper_title: A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

paper_content:

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.
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paper_title: Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

paper_content:

We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.
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paper_title: High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

paper_content:

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I DSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V DD = 1 V and off-current I OFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.
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paper_title: Ultra-Wide Voltage Range designs in Fully-Depleted Silicon-On-Insulator FETs

paper_content:

Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices significantly improves the trade-off between leakage, variability and speed even at low-voltage. A full design framework is presented for UWVR operation using FDSOI Ultra Thin Body and Box technology considering power management, multi-VT enablement, standard cells design and SRAM bitcells. Technology performances are demonstrated on a ARM A9 critical path showing a speed increase from 40% to 200% without added energy cost. In opposite, when performance is not required, FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing.
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paper_title: Energy-Aware System Design: Algorithms and Architectures

paper_content:

Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moores law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints. Energy-Aware System Design: Algorithms and Architectures provides state-of-the-art ideas for low power design methods from circuit, architecture to software level andoffers design case studies in three fast growing areas of mobile storage, biomedical and security.Important topics and features:- Describes very recent advanced issues and methods for energy-aware design at each design level from circuit andarchitecture toalgorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level- Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts - Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency- Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camera systems.Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.
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paper_title: A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

paper_content:

A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.
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paper_title: Energy-Aware System Design: Algorithms and Architectures

paper_content:

Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moores law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints. Energy-Aware System Design: Algorithms and Architectures provides state-of-the-art ideas for low power design methods from circuit, architecture to software level andoffers design case studies in three fast growing areas of mobile storage, biomedical and security.Important topics and features:- Describes very recent advanced issues and methods for energy-aware design at each design level from circuit andarchitecture toalgorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level- Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts - Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency- Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camera systems.Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.
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paper_title: Analysis and future trend of short-circuit power

paper_content:

A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, P/sub S/, caused by the scaling in relation to the charging and discharging power, P/sub D/, is discussed and it is shown that basically power ratio, P/sub S//(P/sub D/+P/sub S/), will not change with scaling if V/sub TH//V/sub DD/ is kept constant. This paper also handles the short-circuit power of series-connected MOSFET structures which appear in NAND and other complex gates.
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paper_title: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits

paper_content:

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
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paper_title: Programmable nanowire circuits for nanoprocessors

paper_content:

In a significant step forward in complexity and capability for bottom-up assembly of nanoelectronic circuits, this study demonstrates scalable and programmable logic tiles based on semiconductor nanowire transistor arrays. The same logic tile, consisting 496 configurable transistor nodes in an area of about 960 μm2, could be programmed and operated as, among other functions, a full-adder, full-subtractor and multiplexer. The promise is that these logic tiles can be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.
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paper_title: Practical Strategies for Power-Efficient Computing Technologies

paper_content:

After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an ~ 8× improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.
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paper_title: Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric

paper_content:

In this paper, we demonstrate p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile. The tunnel FETs were fabricated with three different gate dielectrics, SiO2, Al2O3, and HfO2, and show a performance enhancement when using high-k dielectric materials. The best performance is achieved for the devices using HfO2 as the gate dielectric, which reach an Ion of 0.1 μA/μm (VDS = -0.5 V, VGS = -2 V), combined with an average inverse subthreshold slope (SS) of ~ 120 mV/dec and an Ion/Ioff ratio of around 106. For the tunnel FETs with Al2O3 as the gate dielectric, different annealing steps were evaluated, and an activation anneal at only 700°C was found to yield the best results. Furthermore, we also investigated the temperature behavior of the tunnel FETs. Ideal tunnel FET behavior was observed for devices having ohmic Ni/Au contacts, and we demonstrate the invariance of both the SS and on-current with temperature, as expected for true tunnel FETs.
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paper_title: Reconfigurable Silicon Nanowire Transistors

paper_content:

Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce static power consumption. However, CMOS transistors are limited to static electrical functions, i.e., electrical characteristics that cannot be changed. Here we present the concept and a demonstrator of a universal transistor that can be reversely configured as p-FET or n-FET simply by the application of an electric signal. This concept is enabled by employing an axial nanowire heterostructure (metal/intrinsic-silicon/metal) with independent gating of the Schottky junctions. In contrast to conventional FETs, charge carrier polarity and concentration are determined by selective and sensitive control of charge carrier injections at each Schottky junction, explicitly avoiding the use of dopants as shown by measurements and calculations. Besides the additional functionality, the fabricated nanoscale devices exhibit e...
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paper_title: A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

paper_content:

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
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paper_title: A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

paper_content:

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.
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paper_title: Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

paper_content:

We present UTBB devices with a gate length (L G ) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V bb ) enables V t modulation of more than 125mV with a V bb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V t and power management applications. We explore the impact of GP, BOX thickness and V bb on local V t variability for the first time. Excellent A Vt of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I g ) and lower external resistance (R ext ), thanks to a thicker inversion gate dielectric (T inv ) and body (T si ) thickness.
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paper_title: Extremely thin SOI for system-on-chip applications

paper_content:

We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of V T tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.
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paper_title: Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

paper_content:

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate
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paper_title: Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

paper_content:

We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.
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paper_title: Assembly and integration of semiconductor nanowires for functional nanosystems

paper_content:

Central to the bottom-up paradigm of nanoscience, which could lead to entirely new and highly integrated functional nanosystems, is the development of effective assembly methods that enable hierarchical organization of nanoscale building blocks over large areas. Semiconductor nanowires (NWs) represent one of the most powerful and versatile classes of synthetically tunable nanoscale building blocks for studies of the fundamental physical properties of nanostructures and the assembly of a wide range of functional nanoscale systems. In this article, we review several key advances in the recent development of general assembly approaches for organizing semiconductor NW building blocks into designed architectures, and the further integration of ordered structures to construct functional NW device arrays. We first introduce a series of rational assembly strategies to organize NWs into hierarchically ordered structures, with a focus on the blown bubble film (BBF) technique and chemically driven assembly. Next, we discuss significant advances in building integrated nanoelectronic systems based on the reproducible assembly of scalable NW crossbar arrays, such as high-density memory arrays and logic structures. Lastly, we describe unique applications of assembled NW device arrays for studying functional nanoelectronic-biological interfaces by building well-defined NW-cell/tissue hybrid junctions, including the highly integrated NW-neuron interface and the multiplexed, flexible NW-heart tissue interface.
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paper_title: Controlling the Polarity of Silicon Nanowire Transistors

paper_content:

Each generation of integrated circuit (IC) technology has led to new applications. The most recent advances have enabled noninvasive surgery, three-dimensional (3D) games and movies, and intelligent cars, to name a few. A single chip can contain more than 1 billon elementary devices, and this gain in complexity has been achieved by fabricating nanometer-scale transistors used as switches or memories. Recent experimental work by De Marchi et al. ( 1 ) describes changes to the structure of one of the most basic bricks of ICs by controlling the type of conduction occurring in vertically stacked silicon (Si) nanowire transistors (see the figure, panels A and B), thus making a programmable transistor.
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paper_title: Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs

paper_content:

A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated
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paper_title: Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies

paper_content:

This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (?V th) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ?V th and is therefore proportional to the trend of ?V th. The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.
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paper_title: High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

paper_content:

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I DSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V DD = 1 V and off-current I OFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.
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paper_title: FDSOI: From substrate to devices and circuit applications

paper_content:

Nanotechnology starts at the substrate level. The SOI substrates enable performance improvement, area saving and power reduction for ICs through a convolution of substrate design and device architecture to maximize the benefits at the IC level. SOI substrates have made possible an efficient PDSOI MOSFET optimization increasing current drive while minimizing leakage and reducing parasitic elements. Further development of the SOI substrate technology has made possible to position ultra thin silicon SOI (UTSOI) as an industrial option for the manufacturing of FDSOI device architectures where the SOI film thickness uniformities is controlled below +5A across the wafer and wafer to wafer. FDSOI enables the design for low power and high performance IC products. FDSOI circuit design does not have to take into consideration the history effect of PDSOI nor the high threshold voltage variation due to random dopant fluctuation given that the transistor channels are undoped. This makes the porting of designs from bulk to FDSOI much simpler. An overview of the advances in Smart Cut UTSOI and FDSOI devices and circuit applications will be given.
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paper_title: A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

paper_content:

This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers. The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions. Dramatic performance enhancement relative to unstrained devices are reported. These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 1.2nm physical gate oxide and Ni salicide. World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 1.2V are demonstrated. NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region. High NMOS drive currents of 1.26mA//spl mu/m (high VT) and 1.45mA//spl mu/m (low VT) at 1.2V are reported. The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families.
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paper_title: A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

paper_content:

A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.
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paper_title: 15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

paper_content:

For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.
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paper_title: High-performance carbon nanotube field-effect transistor with tunable polarities

paper_content:

State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky barrier (SB)-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However, decreasing the oxide thickness also results in pronounced ambipolar transistor characteristics and increased drain leakage currents. Using a novel device concept, we have fabricated high-performance, enhancement-mode CNFETs exhibiting n or p-type unipolar behavior, tunable by electrostatic and/or chemical doping, with excellent OFF-state performance and a steep subthreshold swing (S =63 mV/dec). The device design allows for aggressive oxide thickness and gate length scaling while maintaining the desired device characteristics.
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paper_title: Reconfigurable Silicon Nanowire Transistors

paper_content:

Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce static power consumption. However, CMOS transistors are limited to static electrical functions, i.e., electrical characteristics that cannot be changed. Here we present the concept and a demonstrator of a universal transistor that can be reversely configured as p-FET or n-FET simply by the application of an electric signal. This concept is enabled by employing an axial nanowire heterostructure (metal/intrinsic-silicon/metal) with independent gating of the Schottky junctions. In contrast to conventional FETs, charge carrier polarity and concentration are determined by selective and sensitive control of charge carrier injections at each Schottky junction, explicitly avoiding the use of dopants as shown by measurements and calculations. Besides the additional functionality, the fabricated nanoscale devices exhibit e...
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paper_title: Device and Architecture Outlook for Beyond CMOS Switches

paper_content:

Sooner or later, fundamental limitations destine complementary metal-oxide-semiconductor (CMOS) scaling to a conclusion. A number of unique switches have been proposed as replacements, many of which do not even use electron charge as the state variable. Instead, these nanoscale structures pass tokens in the spin, excitonic, photonic, magnetic, quantum, or even heat domains. Emergent physical behaviors and idiosyncrasies of these novel switches can complement the execution of specific algorithms or workloads by enabling quite unique architectures. Ultimately, exploiting these unusual responses will extend throughput in high-performance computing. Alternative tokens also require new transport mechanisms to replace the conventional chip wire interconnect schemes of charge-based computing. New intrinsic limits to scaling in post-CMOS technologies are likely to be bounded ultimately by thermodynamic entropy and Shannon noise.
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paper_title: Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

paper_content:

We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.
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paper_title: A polarity-controllable graphene inverter

paper_content:

We propose and experimentally demonstrate a functional electron device, which is a polarity-controllable inverter constructed using a four-terminal ambipolar graphenefield effect transistor(FET). The FET has two input terminals, both a top gate and a back gate, and the polarity of the FET can be switched by switching the input to the back gate. The slope of the inverter transfer curves can be changed by changing the back-gate voltage. By adding binary digital data and sinusoidal carrier waves into the back gate and the top gate of the inverter, respectively, the one-transistor binary digital phase modulator can be constructed and operated.
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paper_title: FinFET SONOS flash memory for embedded applications

paper_content:

FD-SOI (fully depleted silicon-on-insulator) FinFET SONOS flash memory devices are investigated for the first time, and they are found to be scalable to a gate length of 40 nm. Although the FinFET SONOS device does not have a body contact, excellent program/erase characteristics are achieved, together with high endurance, long retention time and low reading disturbance. Devices fabricated on [100] and [110] silicon surfaces are compared.
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paper_title: 6T SRAM design for wide voltage range in 28nm FDSOI

paper_content:

Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.
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paper_title: Ultra-Wide Voltage Range designs in Fully-Depleted Silicon-On-Insulator FETs

paper_content:

Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices significantly improves the trade-off between leakage, variability and speed even at low-voltage. A full design framework is presented for UWVR operation using FDSOI Ultra Thin Body and Box technology considering power management, multi-VT enablement, standard cells design and SRAM bitcells. Technology performances are demonstrated on a ARM A9 critical path showing a speed increase from 40% to 200% without added energy cost. In opposite, when performance is not required, FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing.
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paper_title: Universal logic modules based on double-gate carbon nanotube transistors

paper_content:

Double-gate carbon nanotube field-effect transistors (DG-CNT-FETs) can be controlled in the field to be either n-type or p-type through an extra polarity gate. This results in an embedded XOR behavior, which has inspired several novel circuit designs and architectures. This work makes the following contributions. First, we propose an accurate and efficient semi-classical modeling approach to realize the first SPICE-compatible model for circuit design and optimization of DG-CNTFETs. Second, we design and optimize universal logic modules (ULMs) in two circuit styles based on DG-CNTFETs. The proposed ULMs can leverage the full potential of the embedded XOR through the FPGA-centric lookup table optimization flow. Further, we demonstrate that DG-CNTFET ULMs in the double pass-transistor logic style, which inherently produces dual-rail outputs with balanced delay, are faster than DG-CNTFET circuits in the conventional single-rail static logic style that relies on explicit input inversion. On average across 12 benchmarks, the proposed dual-rail ULMs outperform the best DG-CNTFET fabrics based on tiling patterns by 37%, 12%, and 33% in area, delay, and total power, respectively.
---
paper_title: Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis

paper_content:

This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNT-FETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized NOR-NAND-AOI-OAI primitives, the proposed library of static ambipolar CNTFET gates efficiently implements XOR functions, provides full-swing outputs, and is extensible to alternate forms with area-performance tradeoffs. Since the design of the gates can be regularized, the ability to functionalize them in-field opens opportunities for novel regular fabrics based on ambipolar CNTFETs. Technology mapping of several multi-level logic benchmarks --- including multipliers, adders, and linear circuits --- indicates that on average, it is possible to reduce both the number of gates and area by ~ 38% while also improving performance by 6.9x.
---
paper_title: Digital Integrated Circuits

paper_content:

Progressive in content and form, this practical book successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design. Digital Integrated Circuits maintains a consistent, logical flow of subject matter throughout. Addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective. For readers interested in digital circuit design.
---
paper_title: Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

paper_content:

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self-checking ripple-carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.
---
paper_title: Digital Integrated Circuits

paper_content:

Progressive in content and form, this practical book successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design. Digital Integrated Circuits maintains a consistent, logical flow of subject matter throughout. Addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective. For readers interested in digital circuit design.
---
paper_title: New single-clock CMOS latches and flipflops with improved speed and power savings

paper_content:

New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.
---
paper_title: Digital Integrated Circuits

paper_content:

Progressive in content and form, this practical book successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design. Digital Integrated Circuits maintains a consistent, logical flow of subject matter throughout. Addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective. For readers interested in digital circuit design.
---
paper_title: TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs

paper_content:

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. As a promising approach to keep the pace of Moore's Law, functionality-enhanced devices with multiple independent gates have drown many recent interests. In particular, Three-Independent-Gate Silicon Nanowire FETs (TIG SiNWFETs) can realize the functionality of two serial transistors in a single device. Therefore, they open new opportunities to compact designs in both arithmetic and control circuits. In this paper, we propose TSPC flip-flop implementation with asynchronous set and reset using the compactness of TIG SiNWFET. Electrical simulations show that TIG SiNWFET-based TSPC flip-flop improves nearly 20%, 30% and 7% in area, delay and leakage power respectively as compared to its LSTP FinFET counterpart at 22nm.
---
paper_title: Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application

paper_content:

Abstract Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low- V t CMOS FinFETs representing on-current enhancement and high- V t CMOS FinFETs reducing stand-by power dramatically, namely multi- V t CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with a low- V t configuration is demonstrated with excellent noise margins at a reduced supply voltage.
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paper_title: CMOS scaling for the 22nm node and beyond: Device physics and technology

paper_content:

This paper reviews options for CMOS scaling for the 22nm node and beyond. Advanced transistor architectures such as ultra-thin body (UTB), FinFET, gate-all-around (GAA) and vertical options are discussed. Technology challenges faced by all architectures (such as variation, resistance, and capacitance) are analyzed in relation to recent research results. The impact on the CMOS scaling roadmap of system-on-chip (SOC) technologies is reviewed.
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paper_title: A DC-DC converter for short-channel CMOS technologies

paper_content:

An integrated DC-DC converter with two passive external components was designed and fabricated in an advanced, short-channel (L/sub eff/ 10 MHz) were used to minimize the size of external components, and novel circuits were used to reduce the stress on the short channel devices. Measured efficiencies for a 3.3 V to 1.65 V converter were approximately 75% for output currents from 15 to 40 mA.
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paper_title: Thermal coupling in integrated circuits: application to thermal testing

paper_content:

The power dissipated by the devices of a circuit can be construed as a signature of the circuit's performance and state. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements of the silicon die surface via built-in differential temperature sensors. In this paper, dynamic and spatial thermal behavioral characterization of VLSI MOS devices is presented using laser thermoreflectance measurements and on-chip differential temperature sensing circuits. A discussion of the application of built-in differential temperature measurements as an IC test strategy is also presented.
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paper_title: Circuit techniques for suppression and measurement of on-chip inductive supply noise

paper_content:

Increasing power consumption and clock frequency have significantly exacerbated the Ldi/dt drop, which has emerged as the dominant fraction of the overall power supply drop in high performance designs. We present the design and validation of a high-voltage, charge-pump based active decoupling circuit for the suppression of on-chip inductive power-supply noise. We also propose a low-power, high-resolution, digital on-chip oscilloscope technique, based on repetitive sampling, for measurement of high-frequency supply noise. The proposed circuits were implemented and fabricated in a 0.13mum CMOS process. Measurement results on the prototype demonstrate 48% and 53% reduction in power supply noise for rapidly switching current-loads and during resonance, respectively. On-chip supply noise is measured using the proposed on-chip oscilloscope and the noise waveforms are compared with those obtained from a traditional supply noise monitor and direct on-chip probing using probe pads.
---
paper_title: Power reduction techniques for microprocessor systems

paper_content:

Power consumption is a major factor that limits the performance of computers. We survey the “state of the art” in techniques that reduce the total power consumed by a microprocessor system over time. These techniques are applied at various levels ranging from circuits to architectures, architectures to system software, and system software to applications. They also include holistic approaches that will become more important over the next decade. We conclude that power management is a multifaceted discipline that is continually expanding with new techniques being developed at every level. These techniques may eventually allow computers to break through the “power wall” and achieve unprecedented levels of performance, versatility, and reliability. Yet it remains too early to tell which techniques will ultimately solve the power problem.
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paper_title: Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

paper_content:

A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations.
---
paper_title: All-digital PLL array provides reliable distributed clock for SOCs

paper_content:

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.
---
paper_title: Low-Cost and Robust Control of a DFLL for Multi-Processor System-On-Chip

paper_content:

Abstract Fine-grain Dynamic Voltage and Frequency Scaling (DVFS) is becoming a requirement on Globally-Asynchronous Locally-Synchronous (GALS) architectures to ensure low power consumption of the whole chip. Each voltage/frequency island is driven by a voltage and a frequency “actuators”. However, due to process variability that naturally appears with technology scaling, the actuator design must be robust. Moreover, due to area constraints, the control law must be as simple as possible. Last but not least, response time constraints require these controllers to be implemented in hardware. In this paper, the design of a low-cost control law for a full Digital FLL in the context of GALS architecture, in presence of process variability and temperature variations has been proposed. The system has been first modelled, especially, the delay that naturally arises in the sensor has been taken into account. The FLL control has been done with classical control tools. The control problem is original by its hardware implementation that has been done in fixed-point arithmetic. The FLL has been implemented in a GALS chip.
---
paper_title: Dynamic frequency scaling algorithms for improving the CPU's energy efficiency

paper_content:

This paper approaches the problem of improving the service center server CPU's energy efficiency by executing dynamic frequency scaling actions and performing tradeoffs between CPU's computational performance and its power consumption. Two different algorithms are designed and implemented: an immune inspired algorithm and a fuzzy logic based algorithm. The immune inspired algorithm uses the human antigen as a model to represent the server power / performance state. Using a set of detectors the antigens are classified as self for optimal power consumption state or non-self for non-optimal power consumption state. For the non-self antigens a biologically inspired clonal selection approach is used to determine the actions that need to be executed to bring the server's CPU in an optimal power consumption state. The fuzzy logic based algorithm adaptively changes the processor performance states to the incoming workload. The algorithm also filters workload spikes because frequent p-states transition costs can outweigh the benefit of adaptation.
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paper_title: A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

paper_content:

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.
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paper_title: All-digital PLL and transmitter for mobile phones

paper_content:

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.
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paper_title: Enabling improved power management in multicore processors through clustered DVFS

paper_content:

In recent years, chip multiprocessors (CMP) have emerged as a solution for high-speed computing demands. However, power dissipation in CMPs can be high if numerous cores are simultaneously active. Dynamic voltage and frequency scaling (DVFS) is widely used to reduce the active power, but its effectiveness and cost depends on the granularity at which it is applied. Per-core DVFS allows the greatest flexibility in controlling power, but incurs the expense of an unrealistically large number of on-chip voltage regulators. Per-chip DVFS, where all cores are controlled by a single regulator overcomes this problem at the expense of greatly reduced flexibility. This work considers the problem of building an intermediate solution, clustering the cores of a multicore processor into DVFS domains and implementing DVFS on a per-cluster basis. Based on a typical workload, we propose a scheme to find similarity among the cores and cluster them based on this similarity. We also provide an algorithm to implement DVFS for the clusters, and evaluate the effectiveness of per-cluster DVFS in power reduction.
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paper_title: Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques

paper_content:

Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.
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paper_title: Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

paper_content:

A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. In the TSMC 0.25-mum CMOS technology, we implemented 1024 proposed energy recovery clocked flip-flops through an H-tree clock network driven by a resonant clock-generator to generate a sinusoidal clock. Simulation results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops. Using a sinusoidal clock signal for energy recovery prevents application of existing clock gating solutions. In this paper, we also propose clock gating solutions for energy recovery clocking. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000times in the idle mode with negligible power and delay overhead in the active mode. Finally, a test chip containing two pipelined multipliers one designed with conventional square wave clocked flip-flops and the other one with the proposed energy recovery clocked flip-flops is fabricated and measured. Based on measurement results, the energy recovery clocking scheme and flip-flops show a power reduction of 71% on the clock-tree and 39% on flip-flops, resulting in an overall power savings of 25% for the multiplier chip.
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paper_title: Variation-Aware Adaptive Voltage Scaling System

paper_content:

Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-mum technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16times16 bit multiplier
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paper_title: An Asynchronous Power Aware and Adaptive NoC Based Circuit

paper_content:

A fully power aware globally asynchronous locally synchronous network-on-chip circuit is presented in this paper. The circuit is arranged around an asynchronous network-on-chip providing a 17 Gbits/s throughput and automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each NoC units. The dynamic power consumption can be reduced up to a factor of 8 while the static power consumption is reduced by 2 decades in stand-by mode.
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paper_title: Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory

paper_content:

With forecasted hundreds of processing elements (PE), future embedded systems will be able to handle multiple applications with very diverse running constraints. In order to avoid hot-spots and control the temperature of the tiles, dynamic voltage-frequency scaling (DVFS) can be applied at PE level. At system level, it implies to dynamically manage the different voltage-frequency couples of each PE in order to obtain a global optimization. In this article we present an approach based on game theory, which adjusts at run-time the frequency of each PE. It aims at reducing the tile temperature while maintaining the synchronization between the tasks of the application graph. A fully distributed scheme is assumed in order to build a scalable mechanism. Results show that the proposed run-time algorithm find solutions in few calculation cycles achieving temperature reductions of about 23%.
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paper_title: RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

paper_content:

Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in the state-holding latch node. The RazorII flip-flop naturally detects logic and register SER. We implement a 64-bit processor in 0.13 mum technology which uses RazorII for SER tolerance and dynamic supply adaptation. RazorII based DVS allows elimination of safety margins and operation at the point of first failure of the processor. We tested and measured 32 different dies and obtained 33% energy savings over traditional DVS using RazorII for supply voltage control. We demonstrate SER tolerance on the RazorII processor through radiation experiments.
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paper_title: Multiprocessor System-on-Chip (MPSoC) Technology

paper_content:

The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.
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paper_title: System-level energy-efficient dynamic task scheduling

paper_content:

Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time. But in a DVS system consisting of a DVS processor and multiple devices, slowing down the processor increases the device energy consumption and thereby the system-level energy consumption. In this paper, we present dynamic task scheduling algorithms for periodic tasks that minimize the system-level energy (CPU energy + device standby energy). The algorithms use a combination of (i) optimal speed setting, which is the speed that minimizes the system energy for a specific task, and (ii) limited preemption which reduces the numbers of possible preemptions. For the case when the CPU power and device power are comparable, these algorithms achieve up to 43% energy savings compared to [1], but only up to 12% over the non-DVS scheduling. If the device power is large compared to the CPU power, we show that DVS should not be employed.
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paper_title: A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

paper_content:

A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links.
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paper_title: Variation-aware dynamic voltage/frequency scaling

paper_content:

Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors. Although manufacturing process variations are giving rise to significant core-to-core variations in power and performance, traditional DVFS controllers are unaware of these variations.
---
paper_title: A dynamic voltage scaled microprocessor system

paper_content:

The microprocessor system in portable electronic devices often has a time-varying computational load which is comprised of: (1) compute-intensive and low-latency processes, (2) background and high-latency processes, and (3) system idle. The key design objectives for the processor systems in these applications are providing the highest possible peak performance for the compute-intensive code (e.g., handwriting recognition, image decompression) while maximizing the battery life for the remaining low performance periods. If clock frequency and supply voltage are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required. This strategy, which achieves the highest possible energy efficiency for time-varying computational loads, is called dynamic voltage scaling (DVS).
---
paper_title: Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

paper_content:

We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.
---
paper_title: Embedding statistical tests for on-chip dynamic voltage and temperature monitoring

paper_content:

All mobile applications require high performances with very long battery life. The speed and power consumption trade-off clearly appears as a prominent challenge to optimize the overall energy efficiency. In Multiprocessor System-On-Chip architectures, the trade-off is usually achieved by dynamically adapting the supply voltage and the operating frequency of a processor cluster or of each processor at fine grain. This requires monitoring accurately, on-chip and at runtime, the supply voltage and temperature across the die. Within this context, this paper introduces a method to estimate, from on-chip measurements, using embedded statistical tests, the supply voltage and temperature of small die area using low-cost digital sensors featuring a set of ring oscillators solely. The results obtained, considering a 32nm process, demonstrate the efficiency of the proposed method. Indeed, voltage and temperature measurement errors are kept, in average, below 5mV and 7°C, respectively.
---
paper_title: Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

paper_content:

To compensate the variability effects in advanced technologies, Process, Voltage, Temperature (PVT) monitors are mandatory to use Adaptive Voltage Scaling (AVS) or Adaptive Body Biasing (ABB) techniques. This paper describes a new monitoring system, allowing failure anticipation in real-time, looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of dedicated sensor structures located near monitored flip-flop, coupled with a specific timing detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45nm low power technology, demonstrate a scalable, low power and low area system, and its compatibility with a standard CAD flow. Gains between an AVFS scheme based on those structures and a standard DVFS are given for a 32bits VLIW DSP.
---

Title: A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems

Section 1: INTRODUCTION
Description 1: Provide an overview of the significance of power consumption issues in electronic systems and the motivation for the survey.

Section 2: NECESSARY BACKGROUND
Description 2: Discuss the nature of power consumption in digital circuits and review the different types of power contributions, specifically dynamic power and static power.

Section 3: LOW-POWER HIGH-PERFORMANCES DEVICES: TOWARDS THIN DEVICES
Description 3: Review recent innovations in device-level technologies aimed at improving energy efficiency, such as fully depleted silicon-on-insulator (FDSOI) and fin-based FETs (FinFETs).

Section 4: Functionality-Enhanced Devices: An Alternative to Moore's Law
Description 4: Explore opportunities provided by emerging multiple-independent-gate (MIG) devices and their potential to enrich functionalities beyond traditional scaling.

Section 5: CIRCUIT-LEVEL OPPORTUNITIES FOR LOW-POWER SYSTEMS
Description 5: Discuss innovations in circuit-level design that leverage advanced devices to manage power more efficiently and improve performance.

Section 6: ARCHITECTURAL-LEVEL TECHNIQUES FOR LOW-POWER SYSTEMS
Description 6: Review architectural-level techniques for power management, including dynamic voltage and frequency scaling (DVFS) and adaptive voltage and frequency scaling (AVFS) in complex systems.

Section 7: Conclusions
Description 7: Summarize the key findings and implications of the survey, emphasizing the importance of a holistic approach in energy-aware design.