A closer look at AMD's dual-core architecture Let's start by
looking at a very simplified diagram of a dual-core Opteron,
which looks like so:  How two CPU cores are situated together on
a chip. Source: AMD.  As you can see, AMD didn't simply glue a
pair of K8 cores together on a single piece of silicon. They've
actually done some integration work at a very basic level, so
that the two CPU cores can act together more effectively. Each
of the K8 cores has its own, independent L2 cache onboard, but
the two cores share a common system request queue. They also
share a dual-channel DDR memory controller and a set of
HyperTransport links to the outside world. Access to these I/O
resources is adjudicated via a crossbar, or switch, so that each
CPU can talk directly to memory or I/O as efficiently as
possible. In some respects, the dual-core Opteron acts very much
like a sort of SMP system on a chip, passing data back and forth
between the two cores internally. To the rest of the system I/O
infrastructure, though, th