F-RISC/G and Beyond -- Subnanosecond Fast RISC for TeraOPS
Parallel Processing Applications  ARPA Contract Numbers
DAAL03-90G-0187,   [AASERT Award DAAL03-92G-0307 for Cache
Memory]  Semi-Annual Technical Report  April 1994 - October 1994
Prof. John F. McDonald  Center for Integrated Electronics
Rensselaer Polytechnic Institute  Troy, New York 12180   FAX
(518)-276-8761  MACinFAX (518)-276-4882  e-mail:
mcdonald@unix.cie.rpi.edu   Previous work on F-RISC/G project
had completed the design of at least one version of each of the
key architecture chips for the 1 ns F-RISC/G computer. However,
preliminary results from the first RPI test chip suggested it
would be prudent to delay fabrication of these chips.
Fortunately the award of a companion HSCD subcontract from
Rockwell provided a mechanism whereby a series of additional
test chip fabrication probes could be tried to establish the
status of the fabrication process. These collateral fabrication
runs have made it possible for us to avoid premature expenditure