  Bradley S Henson ( Thu, 30 Sep 1999 13:22:52 -0700  New to the
list and I don't know the protocol, but I'll make a couple of
pragmatic inputs:  1. You're right that the current path is
forced to deviate, increasing the return "loop" and therefore
the inductance/impedance. However, in many, if not most, of our
multilayer boards, the path deviation to the nearest via or de-
cap is small compared to the rise times. This means the
deviation can be thought of or modeled as a small lumped
parameter discontinuity. In practice, even a 25ps rise time TDR
head travels about 150 mils during its transition. Most of our
"fast" edges are 10 times that.The first order amount of
degradation to be expected is just a matter of electrical
distance of the discontinuity WRT rise  2. Field solvers (2D or
other) usually solve a capacitance matrix based on conductor-
plane potentials, then calculate inductance and various
impedances (even/odd modal). Since the fringe field falls off
away from the conductor, I don't think the locatio