[[PageOutline]] This is the design document for SIMD support in
GHC that resulted from the October 11, 2011 meeting at GHC HQ.
Please see the [wiki:SIMD top-level GHC SIMD] page for further
details. == Introduction == We are interested in the SIMD vector
instructions on current and future generations of CPUs. This
includes SSE and AVX on x86/x86-64 and NEON on ARM chips
(targets like GPUs or FPGAs are out of scope for this project).
These SIMD vector instruction sets are broadly similar in the
sense of having relatively short vector registers and operations
for various sizes of integer and/or floating point operation. In
the details however they have different capabilities and
different vector register sizes. We therefore want a design for
SIMD support in GHC that will let us efficiently exploit current
vector instructions but a design that is not tied too tightly to
one CPU architecture or generation. In particular, it should be
possible to write portable Haskell programs that use SIMD
vectors. On the other