Take the 2-minute tour ×  Can anyone highlight ways by which
inter-core communication can be reduced in a NUMA multicore
architecture. Case study Intel NEHALEM micro architecture.
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accepted  The Nehalem processor uses QuickPath Interconnect
(QPI) for inter-processor/node/package communication. In a NUMA
system each node has its own local memory, which is shared with
other nodes in the system. When the working set of a program
fits in the L1 cache and is read-only then it doesn't matter
much which NUMA node owns the memory. Communication between NUMA
nodes is necessary when a core gets a cache miss and the memory
is owned by another node. However, this doesn't mean that it is
slower to access memory owned by another node, it depends on
whether the other node has it cached in the cache associated
with its local memory, what Intel calls the Last Level Cache
(LLC). Access by a core to a memory location that is local to
that node is faster than access to