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Difficulty level Difficulty 1.png  In the Intel Architecture,
and more precisely in protected mode, most of the memory
management and Interrupt Service Routines are controlled through
tables of descriptors. Each descriptor stores information about
a single object (e.g. a service routine, a task, a chunk of code
or data, whatever) the CPU might need at some time. If you try,
for instance, to load a new value into a segment register, the
CPU needs to perform safety and access control checks to see
whether you're actually entitled to access that specific memory
area. Once the checks are performed, useful values (such as the
lowest and highest addresses) are cached in invisible registers
of the CPU.  Intel defined 3 types of tables: the Interrupt
Descriptor Table (which supplants the IVT), the Global
Descriptor Table (GDT) and the Local Descriptor Table. Each
table is defined as a (size, linear address) to the CPU through
the LIDT, LGDT, LLDT instructions