Product Releases  Digital IC Design Platform  Fri, 12/30/2005 -
7:44am  Cadence Design Systems, Inc. introduces the SoC
Encounter™GXL and the Encounter RTL Compiler GXL, an upgraded
version of the Cadence® Encounter® RTL Compiler global synthesis
technology. SoC Encounter GXL adds yield as a standard design
target throughout the implementation flow to address both the
'defect' and 'process variation' challenges of advanced designs
at 65 nanometers and beyond. SoC Encounter GXL addresses
nanometer defect yield issues with new yield analysis and
optimization capabilities embedded across the implementation
flow. For yield analysis, a new command, reportYield, assesses
full-chip or block-level defect yield losses based on factors
such as critical area and cell yields. A unique yield
prototyping capability enables users to choose full-chip floor
planning strategies with visibility of yield considerations
before committing to a physical architecture for the chip. For
yield optimization, SoC Encounter GXL supports c