  Inter-core Interrupter (Doorbell/Mailbox)  A commonly-required
component for basic synchronisation between separate cores.
Used, for instance, where one CPU has placed a message in a
shared memory region for another to read.  Offers a target
(slave interface) for one or more cores. Generates interrupts
for the other cores (and self in symmetric situations).  One
core write a register that asserts and interrupt wire to another
core.  Mailbox variant allows small data items to be written to
a queue in the interrupter. These are read out by the (or any)
core that is (or wants to) handle the interrupt.