Understanding Bandwidth and Latency  Ars discusses issues of
bandwidth and latency inside hardware architechture.  Latencies
in real-world systems  Now let's take a look at a graph that
scales out to much longer burst lengths than the 20-beat maximum
in the previous graph.  Graph 2: Bandwidth vs. Burst Length  One
thing you should know about this graph is that even though its
curve may appear to be steeper than that of the previous graph,
this is only because the previous graph shows fewer burst
lengths (only up to 20). The graph shown above is actually much
slower to ramp up to the peak bandwidth than the previous graph,
and this is because I've used a 9-cycle memory read latency
instead of the 3-cycle latency in the former graph. The 9-cycle
latency number more accurately reflects the kind of latency seen
by a real-world system. Let's look at why this is.  In systems
where memory is connected directly to the CPU (whether main
memory or a backside L2 or L3 cache), data takes only one bus
clock cycle to trave