The above sequence will (some architectures) result in a memory protection fault at step 2, but (speculative execution) instructions 2,3,4 will get executed, loading the cache with either A0 u or A1 u.
However, via speculative execution, instructions 2,3, and 4 will get executed, loading the cache with either A0 u or A1 u. The above sequence will, on some architectures, result in a memory protection fault at step 2.
The above sequence will, on some architectures, result in a memory protection fault at step 2. However, via speculative execution, instructions 2,3, and 4 will get executed, loading the cache with either A0 u or A1 u.
The above sequence will, on some architectures, result in a memory protection fault at step 2. However, via speculative execution, instructions 2,3, and 4 will get executed, loading the cache with either A0 u or A1 u.