The use of this technique necessitates branch prediction, and incorrect branch predictions require this technique's namesake structure to be flushed, creating a (*) bubble.
Scoreboarding and the Tomasulo algorithm are two methods for improving the effectiveness of this technique by permitting out of order execution. VLIW and superscalar architectures are two other complements to this technique which improve performance without the complexity of especially deep versions of this technique. The use of this technique necessitates branch prediction, and incorrect branch predictions require this technique's namesake structure to be flushed, creating a (*) bubble. Other challenges with this technique are data hazards, such as those caused by a read after a write. Instruction fetch, decode, execute, memory access and register write are the 5 stages of the classic RISC implementation of this technique. For 10 points, name this technique from CPU architecture which increases throughput, but does not decrease latency, by processing many instructions concurrently in the namesake object.
Scoreboarding and the Tomasulo algorithm are two methods for improving the effectiveness of this technique by permitting out of order execution.
instruction pipelining