One of the innovations of this design was retrieval of data from RAM to be translated into machine code and then processed in the faster register; that process is known as the fetch-decode-execute cycle.
John Backus coined the term for one of the problems with this design and discussed its intellectual equivalent that encourages "word-at-a-time thinking," and that problem cam be counteracted with a cache in NUMA. One of the innovations of this design was retrieval of data from RAM to be translated into machine code and then processed in the faster register; that process is known as the fetch-decode-execute cycle. One alteration to this scheme is the combination of the arithmetic-logic and control units into the CPU. The primary drawback of this design scheme stems from the sequential, rather than parallel, processing, which leads to limited speed of throughput relative to the size of the memory and forces the CPU to spend too much time in the wait state. For 10 points, name this design model with an eponymous bottleneck that uses a single structure as memory for data and instructions and is often contrasted with a Harvard architecture.
John Backus coined the term for one of the problems with this design and discussed its intellectual equivalent that encourages "word-at-a-time thinking," and that problem cam be counteracted with a cache in NUMA.
{von Neumann} architecture [or {stored}-{program computer}]