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Clamper circuit problem

  1. Jul 8, 2006 #1
    # Draw the output waveform for the following clamper circuit. Assume that 5y = 5RC >> T/2 where y = time constant of the RC circuit, T = time period of the input square wave voltage.

    I solved it in the following way:

    Positive half cycle of input voltage
    During positive half of input voltage when V=V1, D1 exists in forward biased condition. Hence, V-output = V1.

    Negative half cycle of input voltage
    During negative half cycle, D1 exists in reverse biased condition. Hence V-output = Potential difference across resistance R = (-V) + (-V) where one –V is due to the input voltage and the other –V is due to the charged capacitor. Hence V-output = -2V. But the difference between my output waveform and the output waveform given in my book is that in my book they have taken 2V downwards from V1 whereas I have taken it from the origin. As per the book answer, the output voltage at a time T/2 is (2V – V1). How can that be possible when an output voltage of -2V is obtained during the negative half cycle of input voltage?
    But in a clamper circuit, the output waveform has the same voltage swing as the input waveform. So, my answer is wrong but I don’t know where I have gone wrong. Could anyone please help me with this problem?

    Attached Files:

  2. jcsd
  3. Jul 11, 2006 #2


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    Staff: Mentor

    Hi Amith, this really belongs in the homework forums (your previous similar question "Clipper circuit problem" was correctly placed there), but I'll try to address it here anyway.

    It's a little over-simplified to say that the diode is in forward conduction for the positive half cycle of the input voltage. That's not really true. The diode is in forward conduction when the anode is more positive than the cathode. For a real diode, it will settle with about 0.7V of forward voltage drop (depending on current, temperature, etc.). For the ideal diode that seems to be used in your homework problems, they seem to be assuming a 0V drop across a dead short for the diode.

    That's why the output voltage clamps at V1 (plus the 0V idealized diode forward drop) for the positive half-cycle. I think that the reason that the negative half cycle ends up at -(V-V1) is that the swing down in voltage of -2V starts at V1 because of the isolating capacitor, instead of startiong at +V if it were DC-connected. In fact, it looks more like the answer should be V1-2V for the bottom half cycle. Are you sure the text answer is correct?
  4. Jul 11, 2006 #3
    Though it is a homework problem, being an engineering topic I thought it would be better to post it here. You have rightly pointed out that the swing in the negative direction is (V1 - 2V). I am extremely sorry. Its a typo. During the positive half cycle will the capacitor be charged to a potential of (V - V1) and not V because V and V1 are acting in opposite directions?
  5. Jul 11, 2006 #4


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    Staff: Mentor

    No need to be sorry. I could see that you use the homework forums, so I didn't think you were trying anything strange with the post. But yes, the PF guidelines are pretty straightforward about posting homework problems in other forums. It's usually only allowed for graduate-level work and larger projects. Just skim over the guidelines in the homework forum to clarify.

    And I wouldn't use the words "V and V1 are acting in opposite directions". I think it's better to think about the clamping aspect of the diode when it's forward biased. Because the diode has a low impedance when in forward bias, that clamps the output voltage at the V1 supply voltage. The V1 power supply ideally has a very low output impedance, so it will sink or source whatever current is necessary to maintain the V1 voltage across its output terminals. Of course, with the diode nosing into the V1 power supply as in your figure, the V1 power supply can only sink current, not source any current to the outside circuit. Hope that helps.

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