Frequency Division Scheme

A project log for SquareTone

A hardware project that generates square waves frequencies and sums them together, Fourier style.

Adam GulyasAdam Gulyas 05/26/2015 at 09:590 Comments

Note: this log was created in 2015 and may not be valid anymore. Starting January 2016 I'm going through the design process systematically and may add or change details.

I'm calling this part of the project the division network. It's the part that takes the initial high frequency square wave and pulls out all the harmonics (which are then sent to the summing op-amp).

First, I found circuits which I could blackbox and just think of as (with regards to frequency) "divide by n".

In general, you can make a "divide by n" circuit by using the input pulse as a clock, and then pulsing the output every n pulses. The IC I found which does this is the CD4017B, a CMOS Counter/Divider (TI Datasheet). I picked the SOIC 16 package.

Here's the "divide by 2" circuit:

Now that I have blackbox dividing circuits, here's the block diagram for the divider network:

To find this configuration I tried every possible way of dividing 840 by its factors to get the desired harmonics, 840 being the LCM. I chose the way that used the least number of divisions, letting me chain multiple outputs together.

Something that kind of sucked was that originally the 8 Hz signal was coming out of the divide by 7 block, which doesn't provide a 50% duty cycle. I had to double the input frequency to 1680 Hz and add an extra divide by 2 block. This will end up halving the maximum output frequency of the project.

The dashed boxes indicate which divide by 2 blocks share an IC.

Also note that, although the outputs are labeled numerically, the input frequency will be variable. I labeled the circuit nodes that way to make sure my math was right.

This is a bit nitpicky, but I noticed something after I had designed the pcb for this project. If I want to decrease the presence of high frequency signals on the board, I should rearrange the divide by n blocks to divide by the larger numbers first. In the case of U1 - U3, instead of having 560 Hz, 112 Hz, 16Hz, I could instead get 240 Hz, 48 Hz, 16 Hz. However, I don't think it will be that big of a deal and doesn't justify changing all my documentation and design. If I had proof it would be a problem I would put in the effort, but at this point it's just a small maybe.

That concludes the theory of the divider network. Check the PCB Design project log for the implementation.