Parallel Divider

The PDU accepts two serial inputs as divisor and dividend in one word time, produces a truncated quotient by means of a parallel algorithm in one more word time, and shifts the product out in the next word time while inputs for the next operation are simultaneously shifted in. The parallel divider algorithm used is called Non-Restoring division (1). Two’s complement representation is used for negative numbers. The PDU consists of three registers, the Divisor (Z), the Dividend (D), and the Quotient (Q). The 20-bit parallel divide is accomplished in one word time of 106.6 microseconds.

(1) CHU, YOAHAN, “Digital Computer Design Fundamentals,” 1962, Mc Graw Hill, Inc., page 39

Parallel Divider F14

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