PowerPC on Apple: An Architectural History, Part I


The 604's front-end

The 604's branch unit also features a dynamic branch prediction scheme that's a vast improvement over the 603e's static branch predictor. The 604 has a large, 512-entry branch history table (BHT) with two bits per entry for tracking branches, coupled with a 64-entry branch target address cache (BTAC, which is the equivalent of the Pentium's BTB).

As always, the more transistors you spend on branch prediction, the better performance will be, so the 604's branch unit helps it quite a bit. Still, in the case of a mispredict, the 604 longer pipeline will have to pay a higher price than its shorter-pipelined predecessors in terms of performance. Of course, the bigger performance loss associated with a mispredict is also why the 604 spends those extra resources on branch prediction.

The rest of the 604's front end looks like a combination of the best features of the 601 and the 603e. Like the 601, the 604's instruction queue is eight entries deep. Instructions are fetched from the L1 cache into the queue where they're decoded before being dispatched to the execution core. The 604's dispatch logic can dispatch up to four instructions per cycle (up from two on the 603e and three on the 601) from the bottom four entries of the instruction queue to the execution core. Though Motorola's 604 whitepaper doesn't explicitly say, I assume that the instructions are dispatched in-order.

If you looked closely at the diagram of the 604, you probably noticed reservation stations attached to the tops of the execution units. Dispatched instructions go from the IQ into these reservation stations, where they wait for their operands to become available. Once all of the operands for an instruction are available, it's eligible to issue to the attached execution unit.

The 604's five reservation stations are relatively small, two-entry affairs, but they make up the heart of the 604's instruction window because they allow instructions to issue out of program order. Their small size as compared to similar structures on the P6 and P4 are due to the fact that the 604's pipeline is relatively short. Pipeline stalls aren't quite as devastating for performance on a machine with six-stage pipeline as they are on a machine with a twelve- or twenty-stage pipeline, so the 604 doesn't need as large of an instruction window as its superpipelined counterparts.

As with the P6 architecture, the reservation stations aren't the only structures that make up the 604's instruction window. The 604 has a 16-entry reorder buffer (ROB) which performs the same function as the P6 core's much larger 40-entry ROB. In my first article on the Pentium, I described the P6's ROB as follows:

The ROB is like a large log book in which the P6 can record all the essential information about each instruction that enters the execution core. The primary function of the ROB is to ensure that instructions come out one end of the out-of-order execution core in the same order in which they entered it. Iin other words, it's the reservation station's job to see that instructions are executed in the most optimal order, even if that means executing them out of program order, and it's the reorder buffer's job to ensure that the finished instructions get put back in program order and that their results are written to the architectural register file in the proper sequence. To this end, the ROB stores data about each instruction's status, operands, register needs, original place in the program, etc.

This description fits the 604's ROB and reservation stations, as well.

The ROB, which corresponds to the simpler completion queue on older PPC processors, is the reason for the two extra pipeline stages I described at the beginning of our discussion of the 604 (the dispatch and completion stages). In the first of these two stages, the dispatch stage, not only are instructions sent to execution core, but entries for the dispatched instructions are allocated an entry in the ROB and a set of rename registers. In the second of these two stages, the completion stage, the instructions are put back in program order so that their results can be written back to the register file in the subsequent write-back stage.

If you want to know more about instruction windows, ROBs, and reservation stations in general, then this page of the first Pentium article is a good place to start.

At any rate, the 604's ROB is much smaller than the P6's ROB for the same reason that the 604's reservation stations are smaller: the 604 has a much more shallow pipeline, which means that it needs a much smaller instruction window for tracking fewer in-flight instructions in order to achieve the same performance.

The tradeoff for this lack of complexity and lower pipeline depth is a lower clock speed. The six-stage 604 debuted in May of 1995 at 120MHz, while the twelve-stage Pentium Pro debuted later that year (November, 1995) at speeds ranging from 150 to 200MHz. The Pentium Pro had a clear clock speed advantage over the 604, but it wasn't what you might expect given the fact that its pipeline was twice as long.

604 conclusions

With a 32K split L1 cache, 604 had a much heftier cache than its predecessors, which it needed to help keep its longer pipeline fed. The larger cache, higher dispatch and issue rate, wider execution core, and deeper pipeline made for a solid RISC performer that was easily able to keep pace with its x86 competitors.

Still, the PPro was no slouch and its performance was scaling well with process shrinks and die improvements. Apple needed more power from AIM to keep the pace, and more power is what they got with a minor core revision that came to be called the 604e.

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