A 2-bit magnitude comparator is a combinationalcircuit which accepts two unsigned 2-bit inputs (A, B) andgenerates three outputs (EQU, GT, LT) which are 1 when input A isequal to, greater than, or less than B respectively.

Design a circuit that implements the comparator.Be sure to show truth tables, K-maps, and reduced equations.Describe your circuit using a Verilog behavioral dataflowdescription and simulate it by writing a testbench. Assume thedevice has a propagation delay of 6 time units.

Your Verilog programs must be compiled andsimulated using the Verilogger software system. Save and print thesimulator timing diagram so that you can include it in your finalreport

This final report must include

  1. 1. A brief problem description

  2. 2. Your design work (truth table, K-map, reduced equations)

  3. 3. Verilog source code listings (for both the design and thetestbench)

  4. 4. The timing diagram showing how your design performed


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