PDP-12 User's Manual



The data break facility allows an I/O device to transfer information directly with the PDP-12 core memory on a cycle- stealing basis. Up to seven devices can connect to the data break facility through the optional Data Multiplexer Type DM01. The data break is particularly well- suited for devices which transfer large amounts of information in block form.

Peripheral I/O equipment operating at high speeds can transfer information with the computer through the data break facility more efficiently than through programmed means. The combined maximum transfer rate of the data break facility is 7.5 million bits per second. Information now to effect a data break transfer with an I/O device appears in Figure 5-13.

[GIF Image of Figure 5-13]

Figure 5-13. Data Break Transfer Interface Block Diagram

In contrast to programmed operations, the data break facilities permit an external device to control information transfers. Therefore, a data- break device interfaces require more control logic circuits, causing a higher cost than programmed-transfer interfaces.

Data breaks are of two basic types: single- cycle and three- cycle. In a single- cycle data break, registers in the device (or device interface) specify the core memory address of each transfer and count the number of transfers to determine the end of data blocks. In the three- cycle data break two computer core memory locations perform these functions, simplifying the device interface by omitting two hardware registers.

In general terms, to initiate a data break transfer of information, the interface control must do the following:

  1. Specify the affected address in core memory.
  2. Provide the data word by establishing the proper logic levels at the computer interface (assuming an input data transfer), or provide readin gates and storage for the word (assuming an output data transfer).
  3. Provide a logical signal to indicate direction of data word transfer.
  4. Provide a logical signal to indicate single-cycle or three-cycle break operation.
  5. Request a data break by supplying a proper signal to the computer data break facility.
SingleCycle Data Breaks

Single- cycle breaks are used for input data transfers to the computer, output data transfers from the computer, and memory increment data breaks. Memory increment is a special data break in which the content of a memory address is read, incremented by 1, and rewritten at the same address. It is useful for counting iterations or external events without disturbing the computer program counter (PC) or Accumulator (AC) registers.

Input Data Transfers

Figure 5-14 illustrates timing of an input transfer data break. The address to be affected in core is normally provided in the device interface in the form of a 12-bit flip-flop register (data break address register) which has been preset by the interface control by programmed transfer from the computer.

External registers and control flip-flops supplying information and control signals to the data break facility and other PDP-12 interface elements are shown in Figure 5-15. The input buffer register (IB in Figure 5-15) holds the 12-bit data word to be written into the computer core memory location specified by the address contained in the address register (AR in Figure 5-14).

Appropriate output terminals of these registers are connected to the computer to supply ground potential to designate binary 1's. Since most devices that transfer data through the data break facility are designed to use either single- cycle or three- cycle breaks, but not both, the Cycle Select signal can usually be supplied from a stable source (such as a ground connection or a +3V clamped load resistor) rather than from a bistable device as shown in Figure 5-15.

Other portions of the device interface, not shown in Figure 5-15, establish the data word in the input buffer register, set the address into the address register, set the direction flip-flop to indicate an input data transfer, and control the break request flip-flop. These operations can be performed simultaneously or sequentially, but all transients should occur before the data break request is made. Note that the device interface need supply only static levels to the computer, minimizing the synchronizing logic circuits necessary in the device interface.

When the data break request arrives, the computer completes the current instruction, generates an Address Accepted pulse (at TP1, the beginning of the break cycle) to acknowledge receipt of the request, then enters the Break state to effect the transfer. The Address Accepted pulse can be used in the device interface to clear the break request flip-flop, increment the content of the address register, etc. If the Break Request signal is removed before TP4 time of the data break cycle, the computer performs the transfer in one 1.6 µsec cycle and returns to programmed operation.

[GIF Image of Figure 5-15]

Figure 5-15. Device Interface Logic for Single-Cycle Data Break Input Transfer

Output Data Transfers

Timing of operations occurring in a single- cycle output data break is shown in Figure 5-16. Basic logic circuits for the device interface used in this type of transfer are shown in Figure 5-17. Address and control signal generators are similar to those discussed previously for input data transfers, except that the Transfer Direction signal must be at ground potential to specify the output transfer of computer information. An output data register (OB in Figure 5-17) is usually required in the device interface to receive the computer information. The device must supply strobe pulses for all data transfers out of the computer (programmed or data break) since circuit configuration and timing characteristics differ in each device.

When the data break request arrives, the computer completes the current instruction and generates an Address Accepted pulse as it enters the Data Break cycle. At TP1 time the address supplied to the PDP-12 is loaded into the MA, and the Break state is entered. Not more than 900 nsec after TP1 (at TP3 time), the content of the device- specified core memory address is read and available in the MB (This word is automatically rewritten at the same address during the last half of the Break cycle and is available for programmed operations when the data break is finished.) Data Bit signals are available as static levels of ground potential for binary 0's and +3v for binary l's. The MB is changed at TP3 time of each computer cycle, so the data word is available in the MB for approximately 1.6 µsec to be strobed by the device interface.

Generation of the strobe pulse by the device interface can be synchronized with computer timing through use of timing pulses BTS2 or BTS5, which are available at the computer interface. In addition to a timing pulse (delayed or used directly from the computer), generation of this strobe pulse should be gated by condition signals that occur only during the Break cycle of an output transfer. Figure 5-17 shows typical logic circuits to effect an output data transfer. In this example, BTS5 and B BREAK set the BREAK ENABLE flip-flop which remains set for one computer cycle (unless successive cycles are requested). This enabling signal samples the buffered MB lines into the data inputs of a D type flip-flop. At BTS2 time the data will be clocked into the Output Buffer flip-flops. Note that BTS2 can generate a strobe pulse only during a BREAK ENABLE cycle. Interface input gates are M101; output bus drivers are M623.

By careful design of the input and output gating, one register can serve as both the input and the output buffer register. Most DEC options using the data break facility have only one data buffer register with appropriate gating to allow it to serve as an output buffer when the Transfer Direction signal is at ground potential or as an input buffer when the Transfer Direction signal is +3v.

Memory Increment

In this type of data break the content of core memory at a device- specified address is read into the MB, is incremented by 1, and is rewritten at the same address within one 1.6 µsec cycle. This feature is particularly useful in building a histogram of a series of measurements, such as in pulse -height analysis applications. For example, in a computer- controlled experiment that counts the number of times each value of a parameter is measured, a data break can be requested for each measurement, and the measured value can be used as the core memory address to be incremented (counted).

Signal interface for a memory increment data break is similar to an output transfer data break except that the device interface generates an increment MB signal and does not generate a strobe pulse (no data transfer occurs between the PDP-12 and the device). Timing of memory increment operations appear in Figure 5-18.

	 - Timing Diagram - To be done -
Figure 5-18. Memory Increment Data Break Timing Diagram

An interface for a device using memory increment data breaks must supply twelve Data Address signals, a Transfer Direction signal, a Cycle Select signal, and a Break Request signal to the computer data break facility as in an output transfer data break. In addition, a ground potential increment MB signal must be provided at least 250 nanoseconds before TP3 time of the Break cycle. The signal can be generated in the device interface by AND combining the B Break Computer Output signal, the output transfer condition of the Transfer Direction signal, and the Condition signal in the device that indicates that an increment operation should take place. When the computer receives this increment MB signal, it forces the MB control element to generate a Carry insert signal at TS3 time to increment the content of the MB.

Three-Cycle Data Breaks

Timing of input or output 3-cycle data breaks is shown in Figure 5-19. The 3-cycle break uses the block transfer control circuits of the computer. The block transfer control provides an economical method of controlling the flow of data at high speeds between PDP-12 core memory and fast peripheral devices, e.g., drum, disc, magnetic tape and line printers. allowing transfer rates in excess of 208 kc.

The 3-cycle data break facility provides separate current address and word count registers in core memory for the connected device, thus eliminating the necessity for flip-flop registers in the device control. When several devices are connected to this facility, each is assigned a different set of core locations for word count and current address, allowing interlaced operations of all devices as long as their combined rate does not exceed 208 kc. The device specifies the location of these registers in core memory, and thus the software remains the same regardless of what other equipment is connected to the machine. Since these registers are located in core memory, they may be loaded and unloaded directly without the use of IOT instructions. In a procedure where a device request to transfer data to or from core memory, the 3-cycle data break facility performs the following sequence of operations:

  1. An address is read from the device to indicate the location of the word count register. This address is always the same for a given device; thus it can be wired in and does not require a flip-flop register.
  2. The content of the specified address is read from memory and 1 is added to it before rewriting. If the content of this register becomes 0 as a result of the addition, a WC Overflow pulse will be transmitted to the device. To transfer a block of N words, this register is loaded with N during programmed initialization of the device. After the block has been fully transferred this pulse is generated to signify completion of the operation.
  3. The next sequential location is read from memory as the current address register. Although the content of this register is normally incremented before being rewritten, an increment CA inhibit (+1 CA Inhibit) signal from the device may inhibit incrementation. To transfer a block of data beginning at location A, this register is program initialized by loading with A-1.
  4. The content of the previously read current address is transferred to the MA to serve as the address for the data transfer. This transfer may go in either direction in a manner identical to the single-cycle data break system. The 3-cycle data break facility uses many of the gates and transfer paths of the single-cycle data break system, but does not preclude the use of standard data break devices. Any combination of 3-cycle and single-cycle data break devices can be used in one system, as long as a multiplexer channel is available for each. Two additional control lines are provided with the 3-cycle data break. These are:
In summary, the 3-cycle data break is entered similarly to the single-cycle data break, with the exception of supplying a ground-level Cycle Select signal to allow entry of the WC (Word Count) state to increment the fixed core memory location contining the word count. The device requesting the break supplies this address as in the 1-cycle data break, except that this address is fixed and can be supplied by wired ground and +3 signals, rather than from a register. Following the WC state a CA (Current Address) state is entered in which the core memory location following the WC address is read, incremented by one, restored to memory, and used as the transfer address (by MB = ~ MA). Then the normal B (Break) state is entered to effect the transfer.
- Timing Diagram - To be done -
Figure 5-19. Three Cycle Data Break Timing Diagram