Intel and AMD aren't the only companies working to improve microprocessor design. Last week, IBM Research announced that it had demonstrated an effective means of building three dimensional integrated circuits (3D ICs), chips in which the transistors sit not only side by side but on top of each other as well. In theory, such a manufacturing technique can significantly boost performance by increasing the number of transistors packed into a chip and decreasing the space between those transistors.

"We have techniques that show you can take device layers and stack them on top of each other, and we've done this with one of our leading-edge device technologies," says Dr. John Warlaumont, director of silicon technology with IBM Research. Specifically, the company has demonstrated the techniques with its current 13 nanometer (nm) manufacturing process, building 3D ICs with silicon-on-insulator substrate and copper wire interconnects.

Today, manufacturers build chips across a single plane of silicon substrate, etching transistors into the silicon using tiny beams of ultraviolet light. They then connect these transistors using millions of tiny copper wires, building layer after layer of these wires atop the substrate. If you want to connect a transistor at one end of the chip, for instance, to a transistor at the other end, you have to run a wire from the first transistor, up out of substrate, across the length of the chip, and then back into the substrate.

Typically, you can improve the performance of such chips simply by shrinking each transistor. The smaller a chip's transistors, the quicker electrons can shuttle between them and the faster the chip can perform each calculation. Unfortunately, building smaller transistors is getting more and more difficult. As transistors get smaller, they tend to consume more power and emit more heat. The insulators separating various parts of the transistor get thinner, and electrons tend to leak from one part to another. Furthermore, the technology will soon reach a point where transistors are only a few atoms wide, and can't get any smaller.

With its 3D ICs, IBM has found a different means of improving chip performance. Rather than limiting all the transistors to a single layer of substrate, the company can stack transistor layers, putting one on top of another on top of another. This speeds calculations in two ways: It lets manufacturers pack more transistors into a given chip, and it reduces the average length of the wires running between transistors. To connect a pair of transistors, wires no longer need to run across the length of the chip. Conductors can run between the stacked layers of transistors, instead. Transistors that were once at opposite ends of the chip, for instance, can now sit directly above and below each other.

In the long run, this could also improve overall PC design. Manufacturers could, for instance, build a PC's memory subsystem directly into the CPU simply by adding another layer of transistors—not only reducing the distance between transistors on the CPU proper, but also between those in the CPU and in memory. "You can actually improve overall machine performance without actually improving the performance of the processor itself," says Warlaumont.

Some researchers have tried to manufacture this sort of 3D chip by sequentially building its many layers of transistors, actually depositing or growing the silicon for the second layer on top of the first layer and so on. Unfortunately, this technique tends to degrade the quality of not only the newest layer but also the layer beneath it. IBM takes a different approach. In essence, it builds each layer separately and then connects them after the fact. "We're able to stack the layers while maintaining very high performance levels at each layer," claims Warlaumont.

IBM will present the details of its 3D IC techniques at the International Electron Devices Meeting (IEDM), to be held in San Francisco December 9 through 11.