GEC 4000 series explained

The GEC 4000 was a series of 16/32-bit minicomputers produced by GEC Computers Ltd. of the UK during the 1970s, 1980s and early 1990s.


GEC Computers started as Elliott Automation with the then ageing Elliott 900 series, and needed to develop a new range of systems. Three ranges were identified, known internally as Alpha, Beta, and Gamma. Alpha appeared first and became the GEC 2050 8-bit minicomputer. Beta followed and became the GEC 4080. Gamma was never developed, so a few of its enhanced features were consequently pulled back into the GEC 4080. The principal designer of the GEC 4080 was Dr. Michael Melliar-Smith and the principal designer of the GEC 4060 and GEC 4090 was Peter Mackley.

The 4000 series systems were developed and manufactured in the UK at GEC Computers Borehamwood offices in Elstree Way. Development and manufacture transferred to GEC Computers new Dunstable factories in Woodside Estate, Dunstable in the late 1970s. In 1979, GEC Computers was awarded the Queen's Award for Technical Achievement for the development of the 4000 series, particularly Nucleus.[1] By 1991, the number of systems manufactured was falling off, and manufacture was transferred to GPT's Beeston, Nottinghamshire factory, and development returned to Borehamwood. The last systems were manufactured around 1995, although there are still a few GEC 4220 systems operating in 2016 with maintenance provided by Telent and some GEC 4310 still operating in 2013.


The GEC 4000 series hardware and firmware included a pioneering facility known as Nucleus.[2] Nucleus implements a number of features which are more usually implemented within an operating system kernel, and consequently operating systems running on GEC 4000 series systems do not need to directly provide these features themselves. Nucleus firmware cannot be reprogrammed by any code running on the system, and this made the systems particularly attractive to a number of security applications.

Nucleus performs:[3]

There is no provision for running any Supervisor/Privileged/kernel mode code on the 4000 systems—all operating system code runs as processes. Hence, device drivers, file system code, and other features which are often found within operating system kernels must be run in processes on the 4000 systems. Inherent in this is that they are all running in their own address spaces, protected from the actions of each other, just as all processes are.

Nucleus is configured by a set of system tables, and processes which have a need to modify the operation of nucleus are given access to the relevant system tables. This would be the case for processes which directly change the state of other processes, processes which allocate and delete memory segments, processes which can change the routing of messages between other processes or change the mapping of I/O devices to processes, etc. Normally system table access is limited to relatively few trusted processes, and other processes which need to perform operations such as loading processes, allocating memory, etc. will pass a message to the relevant trusted process which it will vet before performing the action and replying.

Instruction set

The 4000 series has a CISC instruction set. It has 8-bit bytes, big-endian, byte-addressable memory, two's complement arithmetic, base-16 excess-64 floating point format (same as IBM System/360).[4]

The model numbers less than 4090 are 16-bit processors, and model numbers from 4090 upwards are mixed 16-bit and 32-bit processors. This relates to pointer sizes available to programs. All systems support 16-bit pointers, which is known as CST (Current Segment Table) addressing. The 32-bit systems also support 32-bit pointers, known as PAS (Paged Address Space) addressing. Each process has a PAST (Program Accessible Segment Table) which lists which of the system's memory segments the program is permitted to access. CST addressing allows 4 of the PAST entries to be mapped at addresses 0KiB, 16KiB, 32KiB, and 48KiB, giving the 16-bit/64KiB address space. Programs which use more than 64KiB of memory must explicitly map the PAST entries they require at any moment into their 4 CST entries, although Nucleus will automatically map different code segments into the CSTs. PAS addressing allows programs to view their address space as a flat 32-bit address space, with successive PAST entries appearing every 16KiB, and Nucleus performing the PAST entry segment mapping automatically. The 32-bit systems support both CST and PAS addressing mixed in the same process. All instructions are 16 bits wide, except for some PAS addressing instructions which are 32-bits wide. Instructions can only be run from CST address space.

The 32-bit A register is the main accumulator register. There is a 32-bit B register too, which is most commonly used together with the A register as a 64-bit BA register for double precision floating point operations. A 16-bit X register is used mainly for array indexing, and two 16-bit Y and Z registers are used as 16-bit pointers. A 16-bit L register points to function local data, and a G register always contains zero which can be used as a 16-bit global pointer, and also an 8-bit, 16-bit, or 32-bit zero value. The 16-bit S (sequence) register points to the next instruction to be obeyed. The 8 bit EC register contains condition codes bits. (Some of this is illustrated in the much simpler instruction set of the GEC 2050.) A read-only keys register allows programs to read the value set on the front panel toggle switches (keys) by the operations staff. No 32-bit PAS pointer register exists—32-bit PAS pointers always reside in memory in the 16-bit CST address space, and are accessed by using a 16-bit pointer. There is no instruction set support for a stack. There are a number of registers inaccessible to programs which are used by Nucleus, such as the hardware segment registers which point to the running process's 4 CSTs and master segment and PAS segments, and the system tables.

The instruction set contains instructions which operate register-register, store-register, register-store, and store-store. There are a set of string manipulation instructions which operate on variable lengths of store, copying, comparing, or scanning for a pattern. There are a number of Nucleus instructions which do things such as send message to another process or a peripheral device, receive a message or interrupt, change a CST entry to point to a different segment which is accessible to the process, etc.

The 4080 has a two-stage instruction pipeline. This becomes a four-stage pipeline for the 4220, the highest-performing system in the series. The entry-level 415x and 4x6x systems have only a single-stage pipeline.

The normal operating mode of the CPU is called Full Nucleus. All systems also support a limited mode of operation called Basic Test. In Basic Test mode, Nucleus is disabled, I/O is performed differently, and only a single program can run, restricted to the bottom 64KiB of store, but all other non-nucleus and non-PAS instructions operate normally. This mode is used very early during booting to set up the system tables required by Nucleus, before obeying a Switch Full Nucleus instruction. Once the system has switched to Full Nucleus, it cannot return to Basic Test mode without operator intervention at the front panel, in effect killing any operating system which was running. Basic Test mode is also used to run certain test software (hence the name).


The 4000 I/O design is based around having a number of Input/Output Processors known as IOPs, each of which interfaces between the store and a set of I/O controllers. The IOPs are controlled by the Nucleus function in the CPU, but once an I/O event is triggered, they operate autonomously without interaction with the CPU until the I/O completes. The Normal Interface IOPs can each support up to 255 or 256 simultaneous I/O operations, each on a separate Way. The I/O controllers on each IOP would each occupy one or more Ways, depending on how many simultaneous I/O operations they need to handle. The IOP polices each Way's access to main store, allowing only access to successive memory locations defined for the I/O operation that Way is currently performing. The earlier IOPs performed 8-bit and 16-bit wide store accesses, with a burst mode for doing up to 8 transfers together for higher throughput I/O controllers. The later IOPs added 32-bit wide store accesses.

All systems have at least 1 IOP. On the 4080, this first IOP was called the Basic Multiplexer Channel,[5] or BMC, and the 4080 front panel provides for controlling both the CPU and the BMC. The entry level 415x and 4x6x systems have their first IOP (Integral Multiplexer Channel, or IMC) integrated into the Nucleus firmware, and thus I/O operations on the IMC did have some impact on CPU performance, although the 4x6x systems could have additional external IOPs added too. The 4000 series Nucleus i/o instructions and system tables allow for up to 8 IOPs, although most of the models in the 4000 series range had some type of hardware limitation which reduced this. The 408x systems had 4-ported store, with the CPU and first IOP sharing one of these, and up to 3 additional IOPs connected to the remaining store ports. (Early documentation shows these additional store ports were also designed to connect additional CPUs, although this was not a configuration which was ever sold using 4080 processors.) Later models had more varied number of store ports, depending on how many store port boards could be fitted into the system. The 4190 could support the full complement of 8 IOPs, and the 4190D supported 8 IOPs with 2 CPUs.

Some commonly used I/O Controllers are the interval timer, system console controller, punched tape reader and punch controllers, line printer controller (all these use just a single Way), a number of SMD (and earlier disk bus interface) disk controllers for controlling up to four drives (all using 2 Ways), Pertec PPC magnetic tape controllers for up to four ½" tape drives, and a number of multi ported synchronous and asynchronous serial communication controllers (using between 4 and 32 Ways). A digital I/O board (using 4 Ways) was commonly used for direct process control interfacing, and for providing a fast parallel link between systems. A CAMAC crate controller was also available (again, used for process control interfacing). The Normal Interface bus which these controllers plug into is a published interface,[6] and many customers also built their own controllers for their own specific process control requirements. Also, the earlier GEC 2050 minicomputer used an 8-bit version of the Normal Interface, and most I/O Controllers could be used on both ranges of systems.

All the IOPs designed and built through the 1970s provided the same Normal Interface bus for I/O Controllers, and the I/O controllers could generally be used in any of them. In the 1980s, some more specialised IOPs were designed. A Direct Memory Access Director (DMAD) IOP allowed for a new type of I/O controller which had more freedom to access main memory, and allowed the design of more intelligent communications controllers. A SCSI IOP generated a SCSI bus for attaching more modern disks, and also included an integrated Interval Timer, system console controller, and Calendar Clock so that an additional Normal Interface IOP and separate controllers was not required to support just these functions.


Users of GEC 4000 series systems included many British university physics and engineering departments, the central computing service of University College London (Euclid) and Keele University, the JANET academic/research network X.25 switching backbone, Rutherford-Appleton Laboratory,[7] Daresbury Laboratory, Harwell Laboratory, NERC, Met Office, CERN, ICI, British Telecom, SIP (Italian telco), Plessey, British Steel Corporation and BHP Steel real-time control of rolling steel mills, British Rail and London Underground for real-time train scheduling, London Fire Brigade and Durham Fire Brigade command and control systems, Suffolk Constabulary, and most of the National Videotex systems in the world including the Prestel viewdata service.

At the Rutherford-Appleton Laboratory a GEC 4000 system was used to control the synchrotron and injectors used for the ISIS neutron spallation source until 1998.

A GEC 4080M was also used as the central processor for the radar system of the ill-fated Nimrod AEW.3 airborne early warning aircraft.[8]


A number of variants of the GEC 4000 processor were produced, including (in approximate chronological order):


Several operating systems were available for the GEC 4000 series, including the following:

Programming languages available included Babbage (a high-level assembly language), FORTRAN IV, CORAL 66, ALGOL, APL (programming language) and BASIC.

See also


Notes and References

  1. Web site: GEC Computers wins Queens Award. 21 April 1979. 2011-01-15.
  2. Web site: Central Processor Unit Nucleus Manual. December 1977. GEC 4000 Computer. 2009-06-15.
  3. P. J. Denning, "ACM president's letter: computer architecture: some old ideas that haven't quite made it yet", Communications of the ACM, 24 (9), 1981, page 553.
  4. Web site: Central Processor Unit Instruction Set (GEC 4080). December 1977. GEC 4000 Computer. 2009-06-15.
  5. Web site: C.P.U. Basic Multiplexer Channel. December 1977. GEC 4000 Computer. 2009-06-15.
  6. Web site: User Hardware Handbook – Interfaces (GEC 4080). 4–25. April 1977. GEC 4000 Computer. 2009-06-15.
  7. Web site: The last of the British minis. Engineering Computing Newsletter. 2017-01-07.
  8. Web site: BAe Nimrod AEW 3. 2009-05-17.