Synchronous State Machine

Discussion in 'Homework Help' started by ElijahSykes, Mar 11, 2007.

  1. ElijahSykes

    Thread Starter New Member

    Sep 20, 2006
    Hi, I'm attempting a question on Digital Electronics which goes as follows:

    Give a synchronous circuit, using flip-flops and logic gates,
    that produces a sequence of 3 glitch free output pulses each time its input changes from 0 to 1.

    Apart from the output and input, the only other connection should be a clock.
    Changes in input which are faster than the clock can be ignored.
    When in train, the output should have a frequency which is half the frequency of the clock.

    --- So far I have drawn a state diagram with six states

    State: 000 001 011 010 110 111
    Output: 0 1 0 1 0 1

    '000' is the start state, and its output is 0.

    when the input ( A ) is 0, the state machine stays in state '000'

    when the input ( A) goes high, there is a transition from state '000' to '001',
    and then regardless of how the input changes, the state machine moves through states '001' -> '011' -> '010' -> '110' -> '111' and finally -> '000' back to the start state.

    As you can see from the table, as we make the transitions through from
    '001' -> '011' -> '010' -> '110' -> '111' the output will pulse high 3 times as required.

    The problem is.. I dont know how to turn this into a circuit using FF's and gates :(

    Any ideas? Thanks!
  2. n9352527

    AAC Fanatic!

    Oct 14, 2005
    You need to assign each bit to its own FF. For example, if your states are XYZ, then you need three FFs with respective outputs of X, Y and Z. Then you need to figure out the transition for each FF, e.g. output X goes from 0 to 1 when the state transitions from 010 to 110, then you need to figure out the input to this FF so that it transitions at that moment only.

    After you've done this for all FFs, post your attempt here and we will have a look.