Efinix’s Programmable Chips Could Push AI Out to the Edges

Startup gets $9.5 million to develop smaller, more flexible FPGAs

A computer chip with a brain illustration on it
Photo: Yuichiro Chino/Getty Images

By its cofounder’s reckoning, Efinix is in the right place at the right time. Engineers are struggling to squeeze AI, and especially its deep learning variant, into chips where cost and power are real constraints.

The startup, based in Santa Clara, Calif., plans to deliver a new kind of field-programmable gate array (FPGA) technology that is about one-quarter the size of comparable chips, consumes half the power, and is considerably less complex to construct. That combination—what Efinix calls Quantum programmable technology—could help push deep learning and AI in general away from central computers and servers and out toward where the data they work on is being generated, according to cofounder, president, and CEO Sammy Cheung.

FPGA’s have been using the same basic architecture for decades. From a high-level, it looks like a checkerboard, with alternating sections that are dedicated to either routing or logic. Cheung and cofounder, FPGA-expert Tony Ngai, came up with a new scheme. Instead of each square of the board having a dedicated function, each square—called an eXchangeable Logic and Routing cell (XLR)—can be programmed to perform either purpose.

Traditional FPGA routing blocks have to be designed to handle the worst case scenario: the most complex set of interconnections possible. Because of that, modern FPGAs need a full 10 to 14 layers of metal to form all the interconnects. Those layers of metal and their accompanying insulation act as parasitic capacitors, draining away power.

But because the role of each block is flexible in the Quantum programmable tech, the new design doesn’t need to worry about that worst case. If a logic block needs particularly complex routing, all you need to do is assign an extra one of its neighboring blocks to do the routing. That means the Quantum system is inherently smaller and requires only seven layers of metal interconnect. The reduced metal greatly decreases the power draw from parasitic capacitance, while also making it simpler to integrate the architecture into another chip, such as a System-on-Chip or an applications specific integrated circuit (ASIC).

Efinix plans to begin producing products with development partners starting in 2018 thanks to a US $9.5 million round of funding that completed last week. Interestingly, the biggest contributor was leading FPGA-maker Xilinx. “Efinix’s solution can address a wide variety of applications that are typically not served by today’s FPGAs,” Salil Raje, senior vice president of the software and IP products group at Xilinx, said in a press release. “We are excited to be an investor and look forward to working with them.”

“We’re not going to compete with Xilinx,” says Cheung. “Instead, we can expand market for FPGA.” That market is worth about $5 billion today, he says, but it’s not growing very fast. But “we can see a market that’s $10 billion.”

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