Tackling the rising cost-of-test for semiconductor devices


Click to EnlargeKenneth A Ramsey,

As IC's get more powerful to meet consumer demand, and this same demand drives the prices ever lower, semiconductor device manufacturers are faced with one of the toughest challenges yet to emerge in their business. How do we continue to drive down the costs of these new chips when each new version becomes more complex to test and requires increasingly powerful testers? Over the past 10+ years, silicon designers have done a great job in adopting standards for their CAE tools. It is now possible to use "best-in-class" design tools because of the extensive use of standards among various CAE suppliers. Likewise, in the fabrication area, standards have played a large part in reducing the cost of building the chips. But when it comes to final production testing of the ICs, a lack of standards and the increasing complexity of the ICs being demanded by the marketplace has caused the cost-of-test to escalate, not decrease.

Studies have shown that packaging and test now account for, on average, about 50% of the total product cost for an IC; and this number is projected to rise to over 75% within the next few years. The rising cost of semiconductor device testing is now one of the main challenges to manufacturers. How are manufacturers addressing this new challenge? There are three major trends that are now emerging.

Strip testing allows devices to be production final tested in a massively parallel configuration while still in their leadframe or laminate array rather than one (or a few) at a time. The benefits have been proven in production by subcontractors and IDMs alike. Increased tester utilization of 10%-15%, higher first pass yields of 2%-4%, higher parallelism, far less jams and the ability to handle very small parts (3mmx3mm and below) are documented benefits of moving to strip testing over singulated testing. Strip testing is not for every device, but for those devices (and volumes) that make sense, strip test is a proven way to dramatically reduce the cost-of-test, often by as much as 40% or more.

Higher parallelism during testing of singulated devices is also becoming more widely used. While it clearly has benefits in some cases, it also suffers from the fact that high parallelism test handlers (either gravity or pick-and-place) for singulated parts are increasingly expensive compared to traditional singulated handlers and are still generally limited to parallelism of 32-up and below. Some manufacturers now report that their capex budget for "test" is now almost equally split between testers and test handlers. This is because testers are generally decreasing in cost while traditional singulated and pick-and-place test handlers are generally increasing in cost. This increasing cost for test handlers is due to a desire for higher parallelism and for the ability to handle ever decreasing device sizes.

Wafer probe has always been a key part of the IC testing process. Improvements in wafer probe with higher parallelism and increased accuracy have helped give rise to the concept of wafer-level packaging (WLP). In an effort to drive down the costs of a new device by eliminating the traditional plastic packaging, manufacturers are turning to WLP. In WLP, the device is singulated and then fully functionally tested, with higher levels of parallelism, at wafer probe and shipped to the customer for direct mounting on the PC board. The economics of WLP are rapidly approaching the point that makes it cost effective compared to traditional packaging.

We are seeing a dramatic change in how testing of ICs is accomplished. It's no longer reasonable or feasible to expect that those old technologies will meet the demands of an increasingly complex and competitive industry. Higher parallelism, either for final packaged devices or for wafer level products, will be an indispensable part of any successful test organization, because it has been proven to drive down the cost-of-test.

Kenneth A Ramsey is EVP at MCT Worldwide, LLC, 121 South 8th Street, Suite #960,Minneapolis MN 55402 USA; (612) 436-3240.

Solid State Technology | Volume 54 | Issue 3 | March 2011

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