ASIC/FPGA Encryption Cores

Stargate Semiconductor offers a family of CipherTIME® encryption cores that accelerate both AES encryption and decryption. The Federal Information Processing Standard FIPS approved the Advanced Encryption Standard FIPS-197 in the summer of 2001 and it has quicklybecome the encryption technology standard for the internet, wireless communications, and many other areas that require security.



As with many computationally intensive algorithms such as encryption, they are usually implemented in software and run on fast DSP's and RISC processors. These solutions work fine in most cases but the demand for speed from our internet and data networks continues to rise, making it increasingly more difficult to maintain wire speeds using these methods. CipherTIME cores are designed specifically to address this problem. By implementing a hardware specific circuit to perform redundant cycle-consuming tasks such as encryption, much higher processing performance can be achieved while freeing up valuable cycles from the hosting processor. DSP's and RISC processors typically need many more cycles to process the same data because most of the math is processed in a serial manner making data encryption beyond 10Gbps speeds nearly impossible to do. By comparison, a 128-bit block of AES data will take a DSP or RISC processor about 1500 cycles to process while the SGCIPH40 will process the same date in 11 cycles.



Dedicated hardware will process most of the data in parallel, thereby greatly increasing throughput and also reducing the total number of cycles which ultimately reduces power. This benefits portable applications such as Cell Phones, PDA's and other battery operated devices where power consumption needs to be kept to a minimum.


The SGCIPH40 core, processes data at 2.9Gbps when implemented in 250MHz technology and can perform both encryption and decryption. When implemented in .12um technology or better the SGCIPH40 will reach 400MHz or more yielding throughput of 4.65Gbps. Blocks to be encrypted and decrypted may be interleaved on 128-bit boundaries while maintaining its rated throughput. ECB, CBC, and Timer modes are supported and newer cores introduced later this year will support all modes. CipherTIME® cores have simple synchronous interfaces and are designed to integrate easily into many Application Specific Integrated Circuits (ASIC). With the SGCIPH40 targeting medium speed applications available today, 2 additional cores, the SGCIPH20 and the SGCIPH60, will be introduced later this year addressing the lower speed 145-290 Mbps and the higher speed 44.8 Gbps markets respectively.