Power Supply Design Considerations for Modern FPGAs

by Dennis Hudgins, National Semiconductor , TechOnline India - January 06, 2010

Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power on, and soft-start requirements, can result in unreliable power up or potential damage to the FPGA.



Output Voltage Requirements

The first criteria to consider when designing a power supplies for FPGAs are the voltage requirements for the different supply rails. Most FPGAs have specifications for the CORE and IO voltage rails, and many require additional auxiliary rails that may power internal clocks, phase lock loops or transceivers. Table 1 provides the voltage levels and tolerances for several popular FPGAs.

Table 1. Voltage Requirements for Common Modern FPGAs (click on image to enlarge).

Since FPGAs generally specify several permissible voltage levels for the IO, the voltage selected is dictated by the external digital circuitry. To provide flexibility, the FPGA will generally provide multiple IO banks that can be powered separately allowing the FPGA to interface with various logic families. For simplicity, the solutions illustrated in this article will assume all IO banks are powered off of a single power supply rail.

The core voltage supplies the internal logic configuration blocks of the FPGA and is where many of the internal digital path processes occur. As such, the current demanded by the core will vary greatly depending on the percent utilization of the FPGA. Most FPGA vendors provide design tools that estimate core current requirements based on the internal blocks utilized.

Over time the voltages used to power the core have been steadily dropping. Modern cores like the Stratix III can operate off of voltages as low as 0.9V. Lower core voltages are enabled by finer geometry silicon processes, and are valuable in keeping the power dissipated in the FPGA to a reasonable level. With process technologies designed to operate at lower voltage levels, keeping within the core voltage tolerance requirements has become more challenging for the power supply designer.

{pagebreak}Output Capacitance and Transient Considerations

A good power supply design will keep the core voltage within tolerance at all times. Most of the power supply transient concerns can be managed by properly selecting the bypass and bulk capacitances for the power supply. In general, every core ball or pin connection should be bypassed directly under the FPGA with high-quality X5R or X7R ceramic capacitors. The values recommended for each of these capacitors range from 1 µF to 10 µF and will generally be specified by the FPGA manufacturer. These capacitors provide a charge when the FPGA needs to rapidly draw large spikes of current during high speed operations. Likewise, the bulk capacitance should be selected to provide charge during large steps of current which tend to occur during power on, application start, or a change in application state. Before increasing the amount of output capacitance to solve transient droop issues, changes to the power supply should be made that do not involve an increase in PCB area or component count. The response to a load transient is dictated by the large signal response time that consists of ramping the inductor current to the correct operating level and the small signal response of the control loop.

Transient Response Optimizations

To optimize the transient response, ensure the supply is switching at the highest possible frequency. This will allow use of a small inductor and reduce the large signal response time. Typical high performance power supply solutions can be designed to have crossover frequencies as high as one-tenth to one-fi fth the switching frequency.

Pushing the crossover frequency too high may result in ringing at the output during a load transient indicating poor phase margin. Any ringing in the output should be avoided; this may result in instability with external component variation or when operating at temperature extremes.

AUX Voltage Considerations

Many FPGAs require a third power supply commonly referred to as the auxiliary rail or AUX. Since the AUX rail may power internal clocks, phase lock loops, or transceivers, the amount of output voltage ripple on this rail should be minimized. In some cases, additional ferrite beads and capacitors filtering may be needed to meet the application or FPGA noise requirement. In applications where noise is extremely important, a low noise, high PSRR LDO, like the LP3878, should be considered instead of a switching converter.

{pagebreak}Sequencing Requirements

The sequencing requirements can vary depending on the particular FPGA being used, and many newer FPGAs specify no sequencing is required. While this is technically true for the FPGA, it is not the optimal way to design a power solution.

National offers several devices to address sequencing requirements. The LM3880 is designed to address sequential sequencing of multiple supply rails. This device is available in a small SOT-23 package and can sequence up to three supply rails.

Figure 1. Simplified Buck Converter Schematic

Many options are available to control the up-and-down, three-flag outputs sequencing timing. National also provides devices to support customized flag order and timing. Figure 1 illustrates a typical application circuit for the LM3880.

Voltage tracking is another method of sequencing power supplies applicable to FPGAs and many processors. The most common, and generally recommended, method to power up FPGAs and other processors is to have the CORE voltage track the I/O voltage during startup as shown in Figure 2.

Figure 2. Startup voltage tracking

This power up technique is known as simultaneous startup, and its primary advantage is that it avoids turning on any parasitic conduction paths that may exist between the CORE and IO supply rails. Turning on a parasitic conduction path may lead to unreliable startup or even damage to the FPGA or DSP.

Figure 3. Typical voltage tracking configuration

Some of National's devices that feature voltage tracking include the LM20k family of high performance synchronous DC/DC converters, as well as the LM3743 controller. Figure 3 illustrates a typical voltage tracking configuration for these devices.

{pagebreak}Start-up / Power On Requirements

When sequential sequencing is used in systems with multiple voltage rails, as is the case with many FPGA solutions, it is likely that an output of one of the power supplies could be pre-biased through various parasitic conduction paths. In this situation, how the power supply handles this pre-biased state can have an impact on long-term system reliability, or even the ability of the power supply or FPGA to successfully start. To avoid the pitfalls associated with a pre-biased startup, the power supply should not pull the output low if a pre-biased condition exists. Figure 4 illustrates how a pre-biased condition should be handled when the output is pre-biased to three different voltage levels.

Figure 4. Pre-biased startup of the LM3743

All power solutions featured in this publication are capable of properly handling a pre-biased start up. Power supplies used to power both the CORE and IO must be monotonic during power on to avoid FPGA startup problems. A monotonic startup continuously increases until the output reaches the final value. The critical area for monitonicity for most modern core voltage rails occurs between 0.5V to 0.9V. This is when the FPGA initializes the internal logic blocks to valid operating states.

Soft-Start Requirements

Using soft-start for both the core and IO voltage rails is highly recommended, even if not specified by the FPGA manufacturer. Slowly ramping the input voltage reduces the inrush currents seen in some FPGAs. Using soft-start also reduces the current needed to charge the output capacitance of the power supply and will decrease the voltage droop on the input bus during start-up.

The start-up or soft-start requirements for several FPGAs are summarized in Table 2.

Table 2. Required Start-Up/Soft-Start Times

A startup time of 10 ms generally limits the capacitive inrush currents to an acceptable level while meeting the requirements for most FPGAs and DSPs.

{pagebreak}Application Examples

The application examples shown below implement requirements previously discussed for powering FPGAs. These solutions are meant to be guidelines for selecting the correct devices and circuit topologies to meet the FPGA power requirements.

Figure 5. 2A Core and I/O Solution from a 12V Bus (click on image to enlarge)

Figure 5 features the dual output LM26400 to provide the CORE and IO voltages with current capability up to 2A from a 12V input bus. This solution is optimal for use in the Cyclone and Spartan families of FPGAs; it may also be used in Stratix and Virtex designs where the FPGA utilization is low. This solution provides a monotonic startup with soft-start to limit inrush startup currents. Sequencing is performed with the LM3880. The startup sequence will be the CORE followed by the IO, and then by the AUX rails. The LM3880 features an integrated precision enable circuit that allows the user to set the turn on voltage with two external resistors. An additional N-FET device is used to drop the 12V supply rail down to the operating voltage range of the LM3880. The LP3878 is used to power the 2.5V AUX rail. This device was selected based on the excellent noise performance (18 mV RMS) and high PSRR.


Figure 6. 2A CORE and I/O solution with voltage tracking from a 12V bus (click on image to enlarge)

Figure 6 uses the synchronous LM20242 device capable of supplying 2A of output current. This solution is also ideal for lower output current FPGAs and features a monotonic startup with voltage tracking. Th e LM20242 also utilizes current mode control that offers reduced component count and easy compensation. The LM20242 is a full-featured device with many fault protection features such as over-voltage protection (OVP), under-voltage protection (UVP), thermal shutdown, and an accurate current limit. The synchronous operation of the LM20242 offers improved efficiency over non-synchronous devices resulting in cooler operation and increased reliability.

Figure 7 illustrates the LM20125 being used to power both the CORE and I/O for load currents up to 5A. Since the LM201xx family of devices shares the same pin-out, higher or lower currents can be obtained by interchanging the devices. These full featured devices offer voltage tracking, programmable soft-start, and 1.5% voltage accuracy at the feedback pin. The LM20125 leads the industry in both power density and efficiency for a 5A integrated FET device. Efficiencies as high as 97% are achievable due to 35 mΩ integrated FETs. The LM20125 is off ered in a small TSSOP-16 package and is fully protected with a high accuracy current limit, over-voltage protection, and thermal shutdown.

Figure 7. 5A Core and I/O solution with voltage tracking from a 5V bus (click on image to enlarge)

The circuit shown in Figure 8 utilizes the LM3743 for powering both the CORE and IO. This controller is capable of supporting designs up to 20A and features a SS/TRACK pin to provide a monotonic simultaneous start-up. The LM3743 provides increased system reliability by offering both high- and low-side current limit as well as output under voltage protection. The device also features a hiccup mode protection that eliminates thermal runaway during fault conditions.

Figure 8. High current LM3743 based power supply solution (click on image to enlarge)

The LM20125 is used to power the auxiliary voltage rail and has a compatible SS/TRK pin. National offers a wide range of products that support the power requirements of the latest generation of FPGAs. These power solutions can support the sequencing, soft-start, and voltage tolerance requirements for the newest families of FPGAs, as well as handle challenges such as pre-biased outputs and demanding transient response needs.

About the authord Dennis Hudgins is the low voltage applications manager at National Semiconductor Corp.'s Tucson Design Center.


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