CSS Mixed Signal ASIC Solutions

From Concept through Production,
your Mixed Signal ASIC Solution.


Analog Trimming with On-chip EEPROM

March 23rd, 2009 by Frank


Most of our mixed signal ASIC designs benefit greatly by including the ability to trim key analog circuits.  These often include an amplifier gain/offset, a bandgap reference voltage, a bias current generator or the frequency of an oscillator or filter.  A small amount of nonvolatile memory, coupled with an array of FET switches, resistors and capacitors can provide the equivalent of a discrete DIP switch, trim pot or trim capacitor.  An integrated version of these components also has the advantage of providing electronic trimming.

The most versatile type of memory for storing a trim setting is an EEPROM (Electrically Erasable Programmable Read Only Memory).  As the name implies, it can be written and erased electrically and therefore allows a trim setting to be changed numerous times, either at device test or in the application circuit.  A conventional EEPROM contains a memory core, surrounded by peripheral circuits (row/column drivers, sense amps, etc.).  It may require significant die area and special process steps, both of which may drive the cost of the IC to unacceptable levels.  What’s really needed for holding a trim setting is a small, efficient EEPROM that does not significantly impact cost.

Our nonvolatile registers provide an ideal solution for storing trim settings.  The core memory circuit is a self-contained, nonvolatile latch (NV Latch).  Each NV Latch includes its own level shifter and sense amp, so they can be distributed anywhere they are needed.  They automatically power up to their last programmed state and draw essentially no static current (just junction leakage current – typically less than 1nA).  They can be mated to a wide variety of digital interface circuits to provide serial and parallel read/write access.

Our NV Latch cell does not require any special processing during wafer fabrication, so including it in a design does not add processing steps (or cost).  Even though each bit is completely self-contained, it is still a very area efficient memory.  In the table below, the area required for conventional and latch based EEPROMs are listed.  As expected, when a large number of bits are required, a conventional EEPROM is the densest configuration.  For applications requiring less than several hundred bits, a latch based architecture can be much smaller (and flexible).  For example, a 16 bit NV register requires under 20 square mils or about 1.08 square mils per bit.  This is about the same density per bit as a 0.5K EEPROM, but can be added in 16 bit increments and distributed throughout the IC.  A conventional EEPROM typically has a minimum size of several hundred square mils, corresponding to 256 to 1K bits.  (As the number of bits is reduced, the peripheral circuits dominate the total area required for the memory, making very small memories impractical.)  When less than 100 bits are required, an NV Register can be more than 10 times smaller than a conventional EEPROM.

 EEPROM Area (Conventional vs. NV Latch)


Size (bits)

Total Area

(sq. mils)


(sq. mils)


NV Latch

Size (bits)

Total Area

(sq. mils)


(sq. mils)


















































If you are an IC designer and would like to explore the features of our NV Registers for your own design, you can download specifications for our “Classic” and “High Density” macro cells.  Calculators for our latch based and conventional EEPROMs are also available.  (These are interactive tools that provide EEPROM area estimates for different memory configurations.)  You can download specifications and calculators by visiting our Products/IP Products web page.  Look for “16K EEPROM”, “High Density NV Register” and “NV Register” (Classic Version).

Our library of NV Registers provide a very versatile memory for storing analog trim settings.  Because they require minimal area and no extra processing steps, they have little or no impact on part cost, but can significantly improve part performance.  (They often reduce cost by improving yield when a spec is tight.)  We have found these small EEPROMs so useful that almost all of our mixed signal designs use them.  In addition to storing trim settings, we often use them to save counter states (odometers), configuration data and part ID’s.  For more examples of typical applications, see our “Products/Applications Overview” web page.








Make Your Ex Gf Come Back


Why Develop a Mixed Signal ASIC?

March 3rd, 2009 by Keith



Our ASIC customers are fully aware of all the advantages of mixed signal ASICs, but for those who have never considered one, this top-level review should be helpful. When compared to a system designed with Standard ICs, a mixed signal ASIC can reduce power, size and production costs and improve performance and reliability. The importance of these advantages varies with the application and your needs.

Power is often a significant consideration. Custom mixed signal ASICs can considerably reduce the power consumption of your electronic system. With power as a primary concern, the logic for a custom ASIC can efficiently be implemented in a state machine and avoid the power consumption of a microcontroller clock solution. Also, analog functions in a mixed signal ASIC can be optimized for low power operation, a feature not often available in Standard ICs. At CSS we find that system power can often be reduced to a small fraction of what it would be in a system built with Standard ICs.

On the other hand, speed may be more important than power. You have the option of a speed/power trade-off in the design of a custom ASIC. Or, perhaps noise is a critical issue in your design. The point is that with a custom mixed-signal ASIC, the characteristics most critical for your application can be optimized during the design of the ASIC.

Analog performance may also improve with a mixed signal ASIC. Here, CSS has a particular advantage. We have developed the capability to trim important analog functions using nonvolatile memory (EEPROM) cells built into the ASIC. For example, with this capability we can trim out production variations and set amplifier gains as needed to meet critical specifications.


A custom ASIC will also improve your system reliability. The reduction in component count and their required interconnects at the board level provides for a significant improvement in reliability.

Finally, a custom mixed signal ASIC can significantly reduce your production costs. This is often the primary motivating factor for developing an ASIC. The production cost of a custom ASIC can be considerably less than the Standard IC components it replaces. In addition, the reduction in components will reduce the system assembly costs.

The downside of a custom ASIC often presented is that they are expensive and time consuming to develop. The development cost (NRE) of an ASIC should be compared to the savings it will provide in production. Our experience at CSS is that when a custom ASIC is compared to the Standard ICs it replaces, the development NRE can typically be recovered in a year of production savings.

Development time for a custom mixed signal ASIC is, of course, longer than the development time using Standard ICs. Development time depends on the complexity of the ASIC and the experience of the ASIC design team. CSS has extensive design experience in the development of custom ASICs. By using a proven development process and use of previously designed cells whenever possible, we are able to develop a custom ASIC in a relatively short time.

Finally, in considering the development of a custom ASIC, you need to consider how much knowledge of ASIC development is required and what internal resources are necessary for your development to be successful. Our customers are always pleased to find that they can acquire a mixed signal ASIC without the need to dedicate staff to the job or to cope with all of the technical aspects. We provide a turn-key ASIC solution.