Scientific Method —

Computing with nanotechnology may get a boost from neural networks

New research from Hewlett-Packard suggests that the unreliability of …

I always love to see a refreshingly honest comment on the outlook for research prospects, which is why this abstract caught my attention with its first sentence: "Nanodevices have terrible properties for building Boolean logic systems: high defect rates, high variability, high death rates, drift, and (for the most part) only two terminals." The paper is about applying nanotechnology, or rather, nanodevices towards computation. In some senses this is inevitable, since the relentless drive for increased performance forces manufacturers to pack their transistors into smaller and smaller areas. However, if you thought the transition to 95nm was rocky, just wait till you try going to a 10nm feature size.

The basic idea is that nanotechnology components cannot be complex. Instead, functionality is built up by combining simple objects, like crossbars. From there it is just a matter of time and patience as you place component after component, right? Well, no actually, these guys will have so many components that they cannot be designed and put together in any reasonable time, but rather self assemble into random networks. In this way, the device should look a lot like a field programmable gate array, which essentially provide a circuit designer a way to make very high performance logic circuits without the overhead associated with a CPU.

And that should give you a clue as to where the problems really begin. Not every building block works—in fact, a lot of building blocks don't work. Not every interconnect is fully functional and you—the programmer—has no idea which building blocks and which interconnects do or do not work. Researchers recognize that trying to program such a device would be impossible and are proposing additional steps that make programming possible.

Initially, the compiler is given a chip of unknown functionality and a logic circuit to fit onto that chip. Its first step is to hand the chip to a piece of analysis software that attempts to characterize the chip and map out any defects. The compiler then attempts to design its circuit around the imperfections in the chip. Unfortunately, this really ignores three problems. Firstly, these devices are really bad, and building blocks that are functional now may not be functional a little bit later on. Secondly, no one knows if a chip of usable size can even be characterized in a reasonable amount of time. Finally, routing on a chip with a known number of gates is computationally intensive problem—it takes several minutes to compile a circuit consisting of 10-30,000 gates—that will not be improved by having imperfections.

In this paper, a researcher from Hewlett-Packard is suggesting an alternative approach to the problem. Instead of characterizing the device post-characterization, it is treated rather like a neural network. However, the nanoscale building blocks are all linear (they multiply and add), which would normally preclude a neural network. Snider proposes that these are integrated around nonlinear components fabricated using standard lithographic techniques. This works because not many nonlinear elements are needed and they can be spaced such that the density of the nanoscale building blocks is not greatly affected. The linear elements then act to weight the input into the nonlinear elements.

Depending on the construction of the crossbars, the weighting to inputs of the nonlinear elements can be adjusted on the fly. This allows the network to heal itself as linear elements fail. It also provides a programming mechanism (self-learning) that makes an end-run around the device characterization and compilation problem.

These results are all theoretical at present, but they provide an alternative way forward in the face of some seemingly intractable problems.

Nanotechnology, 2007, DOI: 10.1088/0957-4484/18/36/365202

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