In a Radio420x FPGA design, the design clock is typically the clock received from the Radio420 on FMCCLK0. This clock is set to the same frequency as the Radio420's ADCs and DACs. To run the design at a specific frequency, the Radio420's ADC and DAC clock must be initialized to that frequency.
For example, in the Radio420 Record/Playback example, the ADC/DAC frequency is set (to 40.96MHz) using this define:
 To change the design clock frequency, simply replace FMCRADIO_DATARATE_REF_30_72MHZ_40DOT96MHZ with the frequency value in samples per second.
ex.: #define ACQUISTION_FREQ 10000000
Note: The ADC and DAC frequency is set at the number of I samples + Q samples per seconds sent or received. Therefore, if the design expects 10 million I samples and 10 million Q samples per second, the frequency should be set to 20000000.