Original URL: http://www.theregister.co.uk/2003/06/12/amd_and_intel_scientists_outline/

AMD and Intel scientists outline future chip tech

Tri-gate, fully depleted SOI, metal gates and strained silicon lead the way

By Tony Smith

Posted in Channel, 12th June 2003 09:43 GMT

AMD's boffins continue to explore ways to create ever more powerful processors, and the company this week outlined a couple of the avenues its research is taking. So did its arch-rival, Intel.

Both firms' work is focused on the transistor the key CPU building block. AMD has long touted the benefit of silicon-on-insulator (SOI) designs, and this week said it had measured the fastest PMOS (P-channel metal-oxide semiconductor) transistor speed ever published, equivalent to a 30 per cent speed increase over previously published transistor designs.

AMD's new transistor uses fully depleted SOI (FDSOI), a technique it announced it was working on earlier this year.

SOI works by placing an insulating oxide between a silicon substrate and the silicon that makes up transistor switch. It improves over traditional MOS transistors by reducing the switch's capacity to hold charge - its 'capacitance' - and thus reducing the time it takes for the switch to flip on and off.

When a transistor is switched on, it has to charge up before the current will flow through the switch. The greater the switch's capacitance, the longer that takes. Equally, when the transistor is switched off, current continues to flow until the switch has been emptied of charge. SOI reduces the switch's capacitance significantly, so the transistor operates much more quickly.

SOI transistors are harder to make than traditional MOS transistors because the different physical structures of the silicon and the insulator can lead to electrical imperfections where the two materials meet, slowing the switch down and allowing current to leak. Essentially, the silicon ceases to have a pure crystalline structure, degrading its performance as a semiconductor.

SOI implementations typically use a thick, 'partially depleted' silicon films to overcome these defects - a sort of half-way house between the traditional transistor and the perfect SOI component, which would use thin, 'fully depleted' silicon films.

AMD also said researching strained silicon - a favourite of Intel researchers - but in conjunction with metal gate technology to deliver a 20-25 per cent NMOS (N-channel metal-oxide semiconductor) performance gain over existing strained-silicon transistors.

The metal gates are constructed from Nickel Silicide rather than conventional polysilicon. Essentially, the new material conducts charge better than the old one, speeding the flow of electrons through the transistor. That allows the chip maker to reduce the gate thickness and make it easier to scale transistors down as fabrication processes move to 65nm and below.

Strained silicon involves depositing silicon onto a substrate whose atoms are spaced further apart than silicon atoms usually are. Because atoms inside compounds tend to line up with one another, the silicon atoms move further apart to align themselves with substrate's atoms. This essentially stretches and 'strains' the silicon, the upshot of which is that the resistance to the flow of electrons is reduced, speeding electron flow by up to 70 per cent. Transistors made from strained silicon get a 35 per cent performance boost over regular transistors of the same size.

Adding metal gate technology provides a further 20-25 per cent increase in performance, AMD's scientists say.

They also applied metal gates to their FDSOI transistor, contributing to the 30 per cent performance gain they experienced there.

Intel, meanwhile, has demonstrated a 30nm tri-gate transistor. The transistor's gate controls the flow of current through the device - it's what allows the transistor to act as a switch and thus combine with other transistors to form logic gates, from which computational devices can be built.

Traditional 'planar' transistors use a single gate sitting on top of the silicon (which itself sits on top of the substrate). Intel's tri-gate transistor has gate material on each side of the silicon as well as on top, like a saddle over the silicon's back. Because the gate only controls current through the layers of silicon it's closest to, having gate material on three sides of the silicon activates current through more of the material than on one side alone, the top. That improves the ability of the transistor to switch on quickly, and thus its performance.

Intel announced tri-gate transistors last year, but this week it said it had scaled the device down to 30nm. The company was demonstrating a 60nm device this week, but it can show the device can be easily reduced to half that size. Work on the transistor has reached the point where the company can begin developing it for commercial use, it said, though it put no timescale on it. But fabbing tri-gate transistors can be done using the same processes used to fab today's transistors. ®