Boost ADC performance at Gsample rates, with digital enhancement

September 18, 2015 // By Graham Prophet
Swedish company Signal Processing Devices has issued a note on its IP for FPGAs, a digital time-interleaved ADC mismatch error correction IP-core; the ADX4 IP is used to enhance ADC performance, and the company has published figures for improved results obtainable with three off-the-shelf ADCs from leading semiconductor manufacturers.

When pushing the sampling rates of high-resolution analogus-to-digital converters (ADCs) into the Giga samples per second range, the limit of what can be achieved with single-core ADC implementations is quickly approached. The solution to further increase the sampling frequency is to time-interleave several ADC cores whereby the ADC cores take turns in converting samples into digital format.

However, when time-interleaving several ADCs, differences in gain and phase-response (including time-skew), as well as DC offset between the individual ADCs, produce nonlinear distortion called aliasing that is typically the main performance limitation of time-interleaved ADC arrays. These differences are usually referred to as mismatch errors and are very challenging to remove by purely analogue design [refinements] and careful circuit layout. As an example, in order for a 4 Gsample/sec time-interleaved ADC to achieve 80 dB spurious-free-dynamic-range (SFDR) for a 2 GHz input signal, a time-skew less than 8 fsec is required - a time alignment so short that it corresponds to the propagation delay of a wire length of 1.2 mm.

The figure shows a comparison of three different Gsample/sec time-interleaved ADCs with respect to unwanted aliasing spurs generated due to mismatch. The ADCs used in this test are the Analog Devices AD9625 (2.5 Gsample/sec, 12-bit resolution), Texas Instruments ADC12J4000 (4.0 Gsample/sec, 12-bit resolution), and the E2V EV10AQ190 (5 Gsample/sec, 10-bit resolution). The broken lines represent the “raw” performance of each device. As can be seen, the unwanted aliasing spur levels differ between the different ADCs but common to all time-interleaved ADCs in general is the fact that effects of phase-response mismatches (and time-skew) grow worse with frequency. This is clear from the measurement results in the figure. It should also be noted that the AD9625 operates at a lower sampling rate than the ADC12J4000 and the EV10AQ190 and therefore the mismatch spur level comparison is made over two Nyquist bands for this device.

With digital mismatch error correction the mismatch errors