Darlington transistor

From Wikipedia, the free encyclopedia
Jump to: navigation, search
Circuit diagram of a Darlington pair using NPN transistors


The Darlington configuration was invented by Bell Laboratories engineer Sidney Darlington in 1953. He patented the idea of having two or three transistors on a single chip sharing a collector.[2]

A similar configuration but with transistors of opposite type (one NPN and one PNP) is the Sziklai pair, sometimes called the "complementary Darlington."


View of the chip in an MJ1000

A Darlington pair is like a set of feeders with a high current gain (approximately the product of the gains of the two transistors). In fact, integrated devices have three leads (B, C and E), broadly equivalent to those of a standard transistor.


\beta_\mathrm{Darlington} = \beta_1 \cdot \beta_2 + \beta_1 + \beta_2


\beta_\mathrm{Darlington} \approx \beta_1 \cdot \beta_2

Darlington pairs are available as integrated packages or can be made from two discrete transistors; Q1 (the left-hand transistor in the diagram) can be a low power type, but normally Q2 (on the right) will need to be high power. The maximum collector current IC(max) of the pair is that of Q2. A typical integrated power device is the 2N6282, which includes a switch-off resistor and has a current gain of 2400 at IC=10A.

A Darlington pair can be sensitive enough to respond to the current passed by skin contact even at safe voltages. Thus it can form the input stage of a touch-sensitive switch.



One drawback is an approximate doubling of the base/emitter voltage. Since there are two junctions between the base and emitter of the Darlington transistor, the equivalent base/emitter voltage is the sum of both base/emitter voltages:

V_{BE} = V_{BE1} + V_{BE2} \approx 2V_{BE1}\!

For silicon-based technology, where each VBEi is about 0.65 V when the device is operating in the active or saturated region, the necessary base/emitter voltage of the pair is 1.3 V.

Another drawback of the Darlington pair is its increased "saturation" voltage. The output transistor is not allowed to saturate (i.e. its base-collector junction must remain reverse-biased) because the first transistor, when saturated, establishes full (100%) parallel negative feedback between the collector and the base of the second transistor.[3] Since collector/emitter voltage is equal to the sum of its own base/emitter voltage and the collector-emitter voltage of the first transistor, both positive quantities in normal operation, it always exceeds the base-emitter voltage. (In symbols, \mathrm{V_{CE2} = V_{CE1} + V_{BE2} > V_{BE2}} \Rightarrow \mathrm{V_{C2} > V_{B2}} always.) Thus the "saturation" voltage of a Darlington transistor is one VBE (about 0.65 V in silicon) higher than a single transistor saturation voltage, which is typically 0.1 - 0.2 V in silicon. For equal collector currents, this drawback translates to an increase in the dissipated power for the Darlington transistor over a single transistor. The increased low output level can cause troubles when TTL logic circuits are driven.


The Darlington pair has more phase shift at high frequencies than a single transistor and hence can more easily become unstable with negative feedback (i.e., systems that use this configuration can have poor phase margin due to the extra transistor delay).

See also[edit]


  2. ^ Darlington’s Contributions to Transistor Circuit Design

External links[edit]