Why Low-Power Analog Solutions Are Lacking

Just like the digital side, analog needs to fit in the power budget. Getting there is the next big challenge.


By Luke Lang
The need for low-power design has been well documented. The demand for low-power design solutions is at an all-time high. Just take a quick glance through the 2010 Design Automation Conference advanced program, and you’ll see that the word “low-power” appears repeatedly. These are exciting times for anyone associated with low-power design.

Recent developments in low-power design methodology have produced the concept of a power format file to specify the power intent of a chip. The separation of functional intent (RTL) and power intent (power format file) allows consistent understanding of the power intent by all tools at different stages of the design. This is especially important since any power intent specified in the RTL will not be part of a synthesized netlist. This concept has worked very well over the past four years and resulted in hundreds of successful low-power designs.

However, a deeper look at the current low-power landscape shows that most tools and methodologies only address the RTL-to-GDS flow for synthesizable logic. Just like digital designers, analog/mixed-signal designers also have low-power requirements to meet. Why is it that a low-power solution in this space is conspicuously absent? Let’s take a look at some of the reasons for the current void.

Nature of design
At the risk of over-simplification, the difference between digital and analog design can be summed up as design with massive combinations (digital) versus ultra precision (analog). The typical digital designer deals with millions of gates and employs a variety of tools to deal with the massive combination and sequence of events. Digital simulation, synthesis, logic equivalence checking, static timing analysis, and automatic place and route are some of the commonly used tools by digital designers.

The analog designer, on the other hand, deals with much smaller circuits, but these circuits must operate with far greater precision than a digital circuit. Let’s take a Phase-Locked Loop (PLL) as an example. It consists of two counters (dividers), an input reference clock, and an output clock. The precise specifications of jitter, duty cycle, and lock time are very difficult to meet over a wide range of process, voltage, and temperature. However, the analog designer usually only needs a SPICE simulator to get his/her job done.

Without a doubt, low-power design adds complexity to the design flow. Over the years, digital designers have learned to reduce design complexity with EDA tools. Analog designers have pretty much stuck with schematics and SPICE simulation. Analog behavioral models have been developed to improve simulation speed, but the analog arena has pretty much been dominated by design and simulation.

Top-down vs. bottom-up
Due to massive combinations, a digital chip requires a team of digital designers working together to complete the design. Digital designers employ a top-down design methodology to manage design complexity and facilitate cooperation within the team.

In contrast, analog designers are more individualistic. They typically design one or more circuits by themselves, not as a team. There may be a block-level integration and verification engineer or team that connects the analog circuits together, codes the analog behavioral model, and runs simulation to ensure that connected circuits will function properly. But the design flow is definitely bottom-up with few to no top-level constraints.

Since the digital designers are used to working with various design files, such as RTL and SDC, it is much easier for them to embrace the concept of a power format file. The analog designers tend to be more skeptical of the need and benefit of a power format file. After all, you can’t get more accurate results than SPICE.

RTL vs. schematic
RTL has no power/ground nets and no low power cells. Therefore, it makes a lot of sense to code a power format file and have the tools insert and verify the LP cells. Analog schematic includes all the PG nets and LP cells. An analog designer would ask, why do we need power intent when everything is in the schematic? Besides, a SPICE simulator does not need any power intent file. Therefore, generating a power intent file appears to take a lot of manual work without any benefit.

The challenge for the future is to develop low-power design tools and methodologies that are appropriate for the analog/mixed-signal world. I will have more to say about this topic in future blogs.

— Luke Lang is a staff solutions engineer at Cadence Design Systems.


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