Inside AMD’s Hammer: the 64-bit architecture behind the Opteron and Athlon 64

It's Hammer time at Ars Technica, as our CPU guru Hannibal looks at the …

Converting code: the front end

Increases in the execution core's ability to efficiently schedule, and therefore to consume, more code per cycle are worthless if the front end can't keep the execution core fed. Hammer reorganizes the fetch and decode phases of the original Athlon pipeline in order to increase the average number of instructions per cycle that the front end can deliver to the execution core.

Hammer's front end also features an improved branch predictor, which helps to ensure that the front end stays full of instructions in the event of a change in the flow of the code stream. Keeping Hammer's more deeply pipelined front end supplied with instructions is essential if the front end's improved decoding hardware is going to be put to good use.

Producing code and data: caching and memory

Hammer sports three features aimed at getting code and data from main memory to the processor as quickly as possible: an on-die memory controller, improved caches, and a so-called "large workload" translation look-aside buffer (TLB). I'll talk in more detail about these features later in the article, but for now it's sufficient to note that they're all aimed at complementing the Hammer's increased consumption capacity by increasing main memory's effective production capacity.

Front end and pipeline detail

The following diagram shows instruction flow in the Hammer processor. If you've seen diagrams of the Athlon, then most of this diagram should be familiar. The main differences between this diagram and a similar one of the Athlon lie in the processor's front end. I noted previously that Hammer reorganized the Athlon's front end for more efficient decoding, and in this section we'll take a look at exactly how that reorganization was done.

Figure 2: The Hammer's Architecture

Let's take a look at a chart comparing Hammer's pipeline to that of the Athlon. Don't worry if you don't recognize all of the stages, because we'll walk through them in a moment.

? Athlon Hammer

Fetch Fetch1
2 Scan Fetch2

Align1 Pick
4 Align2 Decode1
5 Decode1 (EDEC) Decode2
6 Decode2 (IDEC/Rename) Pack
7 Schedule Pack/Decode
8 AGU/ALU Dispatch
9 L1 Address Generation Schedule
10 Data Cache AGU/ALU
11 ? Data Cache 1
12 ? Data Cache 2

You'll notice that the Hammer's pipeline is longer than that of the Athlon, a feature that will allow the new processor to scale to higher clockspeeds. The changes to the Hammer's pipeline occur mainly in the front end, and in this section we'll take a look at how the K7's front end has been reorganized to produce the K8.

Expand full story

You must to comment.