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I am studying High Electron Mobility Transistors (HEMT), but I simply cannot understand how they work in the way described by the references I've read on the Internet.

This is what I understand so far: The idea is to decrease scattering and therefore increase mobility by separating the conducting electrons by the ionized donor atoms that are necessary to provide these electrons. Therefore, these transistors are made up of a metal gate, a highly doped n++ semi-conductor (used to supply the mobile carriers), an undoped n spacer region, and a lightly p-doped region. When put together, the undoped n spacer region and lightly doped p region form a heterojunction as both Fermi levels need to be the same AND the ionization energies need to remain constant too. This heterojunction is in the shape of a triangular well on the side of the p-doped semiconductor. So, electrons are able to tunnel in from the n side into the triangular well on the p-side where they stay trapped and separated from ions and can therefore reach high velocities. This triangular region of high mobility electrons is called a 2DEG (2D electron gas)

I hope so far all I've said is correct. (Please correct me if I'm wrong). This is where I get puzzled:

  1. This heterojunction always exists no matter what voltage is applied on the gate. Consequently, there will always be a 2DEG region at the interface between the p and n semiconductors, so a conducting channel between source and drain will always exist (the transistor will always be on). HOW does the gate control this channel ? What bias should be applied on the gate and what are its effects on the 2DEG (and on the conductivity of the device)?

  2. The source and drain regions extend vertically across the different regions (n++, spacer, p). In order to have high mobility, we want the channel between drain and source to be in the 2DEG. So we want the electrons to flow there because that is where they are able to reach the highest speeds because there is hardly no scattering there. However, what stops the electrons from flowing through the n++ region between gate and spacer? It seems to me there are 2 paths for the electrons to follow.

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This is more of an engineering question. Don't know if it''s on - topic here. Maybe a moderator will advise you soon? – Dimensio1n0 Jun 22 '13 at 13:28
@dimension10 This question suitable for Physics.SE, because OP want to have low-level understanding of processes in HEMT. – Sigrlami Jun 22 '13 at 13:51
Welcome to Physics.SE, Percy. As originally written your question had some problem. First it asked several distinct questions; the Stack Exchange model calls for one question per "question". Secondly some parts of it seemed to address purely engineering matters like cost/performance tradeoffs. I've left the bits which seem to form a single core question about the physics of this class of components. – dmckee Jun 22 '13 at 16:34

2 Answers 2

In general the structure is more complex. Carriers for the 2D channel are provided by remote donors in a barrier. In addition, there can be a n-doped region at the surface, which facilitates electrical contacts but also saturates surface states in the channel region. Therefore this usually does not result in a conducting channel.

  1. By applying a gate voltage, you can "tilt" the bandstructure and by this deplete the 2D channel or flood it with electrons from the donors in the barrier. This is how the transistor works.

  2. You are describing the 2DEG structure only. The geometry for a fully functional transistor is more complex. One needs a well defined channel region, drain and source contact regions and a gate contact, which is insulated from the 2DEG. This structure is defined through lithographic steps, where also the n++ region could potentially be etched away, in case it would lead to a parasitic channel. Usually the doping is low enough to only saturate surface states without forming a second channel.

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you asked this a while ago, but I found it while searching for a similar question about HEMTs of my own. @engineer's answer for your first part is good but I think I can answer both, and more fully. Hopefully it'll be of help to someone else if you're past this now.

  1. A diagram from John Davies' "Physics of Low Dimensional Semiconductors" is very helpful for describing this. Here is the picture you've probably seen a lot:

enter image description here

And here's the picture that will answer your question:

enter image description here

As you can see, if you apply the right threshold voltage, you can essentially create an analog of the "flatband condition", and the well completely disappears. It can be a little tricky to solve for that threshold voltage, and to do it properly it needs to be done numerically.

  1. This question is answered perfectly in the same book (which is very good, if you can get it), under the section of "Parallel conduction" (p. 340). The Boltzmann transport equation (see Ashcroft and Mermin) tells you that conduction really only happens right around the Fermi Level, because it integrates over the product of the density of states and $\partial f/\partial \epsilon$ (where $f$ is the Fermi Dirac distribution and $\epsilon$ is the energy).

So, you can see that in the first figure, neither the spacer or the n++ region's conduction bands are close to the Fermi Level (though they mention that if you apply a certain voltage, they can get close enough for them to start conducting).

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