Advances in 3-D Electronics


The earliest electrical circuits appeared to be 3-D; discrete wires interconnecting circuit elements in 3 dimensions. The advent of ICs and PCBs shaped a well-structured, 2-D world for electronics. Racking PCBs by interconnecting from board to board using a backplane created pseudo-3-D architectures. Flex and rigid-flex substrates gained popularity in portable electronics and military applications by building 3-D-finished configurations that fit into small, odd-shaped spaces. The routing and performance was still 2-D; but electronics had “volume.” Early 3-D approaches included memory-stacking in dual-in-line packages (DIPs) with overlapping leads soldered together. One company* pioneered the memory cube by stacking bare memory die. Patterning metallization along the edges of the cube formed the Z-direction interconnections.

As 2-D reaches its limitations, the need for 3-D electronics grows. Research efforts and corresponding 3-D approaches offer an increased number of solutions. One approach stacks thinned die on a substrate, wire bond, and overmold. Stacked-die packaging has driven developments in wire bonding, die thinning (and handling of thin die), die-attach adhesives, and molding. Two-die stacks are common, and 3- and 4-die stacks are entering production. Wire-bonded, 8-die stacks have been built.

An alternate approach is to flip chip-assemble one die onto the surface of another die, and wire-bond this second die into the package. A redistribution pattern may be needed to mate the flip chip die to the wire-bond die. A method demonstrated with memory die to eliminate wire bonds uses thru-die metallized vias, which provide contact pads on both the top and the bottom of the silicon die, and allows stacking of the die and interconnection by solder assembly. Die assembly on flex substrates, followed by folding of the flex to create a 3-D package (with 2-D interconnections), has been commercialized.

Stacking of packages is also being used to address the cumulative-die-yield issue. Although the size and weight advantages of die stacking are not provided, it allows testing of the individual packages prior to stacking.

Die- and package-stacking results in 3-D “stove pipes,” which are assembled on a 2-D circuit board. This can increase volumetric efficiency, and potentially electrical performance, between the die in the stack. The technologies are limited to low I/O counts, and/or high levels of interconnectivity between the die (packages).

The next level up in 3-D integration is the stacking of 2-D modules. The Z-axis interconnections between stacked modules are routed along the edge of the stack. Signals from the interior of one module must travel to the edge of the module, up the edge, and into the interior of another module. This is a pseudo-3-D architecture because Z-axis interconnects are not available at the point of need. A recent variation on 3-D modules involves embedding thinned-silicon die into a build-up substrate, such as laminate, thin film, or flex. This way, Z-axis connections can be distributed through the volume of the assembly, not just at the edges.

The need to parallel-process pixel data in real time is driving the development of 3-D wafer stacking for imaging arrays. With current imaging systems, the data from a pixel must be transferred to the edge of the die before it can be processed. This becomes a time-delay problem with ever-increasing image sizes. With 3-D wafer stacking, the processing elements are fabricated in wafers stacked directly below each pixel, creating massively parallel processing corresponding to massively parallel pixels. This elegant solution to a specific, high-performance challenge requires specially designed and fabricated wafers.

Some fundamental challenges still remain before true 3-D packaging can be widely used. To extend technology beyond memory die and achieve a truly 3-D system-in-package, low-cost, Z-axis interconnections internal to the 3-D structure are needed. Reducing electronics volume reduces surface area. This raises the question of how to get the heat out of the 3-D volume. While a manageable issue for low power, portable applications, and memory, it is a concern that must be addressed if the technology is to be implemented for other applications. Test, burn-in, and high-speed die sort to achieve high assembly yields for systems with a large number of complex die is another challenge the industry faces. 3-D design, partitioning, and routing tools are needed to support advancement of this technology for more complex systems.

System-level, 3-D packaging is the holy grail of the advanced packaging world, and will provide us with a host of interesting challenges and opportunities.

* Irvine Sensors

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R. WAYNE JOHNSON, Ph.D., professor, may be contacted at Auburn University, 162 Broun Hall/ECE Dept., Auburn, AL 36849; 334/844-1880; E-mail: