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This article explains some of the specific properties of MIPS caches. The Wikipedia CPU cache article is more introductory.

Cache Policies

MIPS processors implement several different cache policies. Virtually indexed or tagged caches tend to please hardware implementors, physically indexed caches are favoured by software people.

Physically indexed, physically tagged

This policy is implemented by the R2000 and R3000 processors. It avoids aliases by it's very nature, so doesn't need any cache flushes. It's therefore the prefered cache policy of software implementors.

Physically indexed, virtually tagged

This cache policy is implemented by the R6000. It's believed to be the only processor which ever implemented it. Some literature calls this policy outright useless but nevertheless something must have appealed the R6000 designers enough to go for it. Just to makes things even a little more interesting the R6000 cache and TLB implementations are closely related again in a unique way.

Virtually indexed, physically tagged

Probably the most wide-spread cache policy in modern MIPS processors. While being the favorite of hardware implementors it requires very careful software managment of caches. A few processors have such caches but also a sufficient degree of cache associativity to make them look to software like they're actually physically indexed, physically tagged, thus also inherting their software properties. The R10000 family has a unique solution in that it resolves aliases in hardware, invisible to the programmer. So while the hardware actually suffers from alias this never becomes software visible and caches effectivly behave like physically indexed, physically tagged caches.

Virtually indexed, virtually tagged

A policy that maximises the pains of cache managment if applied to writeback caches. In the MIPS world it therefore only has been used for the instruction caches of the R8000 and the SB1 and 20kc cores and only with an additional address space identifier as a tag. The net result pleases hardware implementors because instruction cache lookup can start before completion of the address translation in the TLB. It also inflicts little pain on the OS implementation.


Caches suffering from aliases are sometimes known as non-coherent. This terminology isn't used in the MIPS world however as for cache managment software there still is a relation.

Cache aliases are also known as synonyms in the literature but the MIPS world prefers the term aliases.

Common Abreviations

instruction cache.
data cache.
secondary cache.
physically indexed, physically tagged.
physically indexed, virtually tagged.
virtually indexed, physically tagged.
virtually indexed, virtually tagged.

Software interfaces

Linux/MIPS provides different interfaces for use by kernel and userspace.

Userspace cache manipulation interfaces

Kernel internal cacheflushing functions

Again this class of functions can be subdivided into two subclasses. These are the generic Linux kernel cache functions which strinctly work for memory managment purposes only. They are implemented for all architectures.

flushes entire cache
flushes the specified mm context's cache lines
flush_cache_page(mm, vmaddr, pfn) 
flushes a single page
flush_cache_range(vma, start, end) 
flushes a range of pages
flush_icache_range(start, end) 
flush a range of instructions
flushes(wback&invalidates) a page for dcache
flush_icache_page(vma, pg) 
flushes(invalidates) a page for icache

The details of these functions are documented in cachetlb.txt. For performance reasons and due to architectural needs for the MIPS architecture a class of additional MIPS-specific functions exists:

flush signal trampoline. This function is used to install signal and fpu emulator trampolines. It assumes that the trampoline fits into a single cacheline. Current signal trampolines are only 8-byte in size for all processors except on the RM7000 and RM9000 processors where a particular workaround is needed to deal with some undesirable behaviour of the processor when fetching the trampoline's instructions.
Flush the entire instruction cache. This function is called on ASID-overflow by the context switching code on processors that feature virtually indexed, virtually tagged I-caches.
Flushes a page from the data cache. This operation is used purely internally by flush_dcache_page() and update_mmu_cache() as the low-level function to do the actual cache manipulation.


Caches are a very complex topic and thanks to the increasing importance of caches for modern architecture running at high clockspeeds subject to ongoing research. This page only tries to cover the MIPS specifics. For a more general understanding of caches, their relation to operating systems and how to exploit them UNIX(R) for Modern Architectures is a recommended book.