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up vote 100 down vote accepted






Further Reading
Cache (Computing) on Wikipedia

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There are a lot of good points raised in the other answers, but one factor appears to be missing: address decoding latency.

The following is a vast oversimplification of how memory address decoding works, but it gives a good idea of why large DRAM chips ar generally quite slow.

When the processor needs to access memory, it sends a command to the memory chip to select the specific word it wants to use. This command is called a Column Address Select (we'll ignore row addresses for now). The memory chip now has to activate the column requested, which it does by sending the address down a cascade of logic gates to make a single write that connects to all the cells in the column. Depending on how it's implemented, there will be a certain amount of delay for each bit of address until the result comes out the other end. This is called the CAS latency of the memory. Because those bits have to be examined sequentially, this process takes a lot longer than a processor cycle (which usually has only a few transistors in sequence to wait for). It also takes a lot longer than a bus cycle (which is usually a few times slower than a processor cycle). A CAS command on a typical memory chip is likely to take on the order of 5ns (IIRC - it's been a while since I looked at timings), which is more than an order of magnitude slower than a, processor cycle.

Fortunately, we break addresses into three parts (column, row, and bank) which allows each part to be smaller and process those parts concurrently, otherwise the latency would be even longer.

Processor cache, however, does not have this problem. Not only is it much smaller, so address translation is an easier job, it actually doesn't need to translate more than a small fragment of the address (in some variants, none of it at all) because it is associative. That means that along side each cached line of memory, there are extra memory cells that store part (or all) of the address. Obviously this makes the cache even more expensive, but it means that all of the cells can be queried to see whether they have the particular line of memory we want simultaneously, and then the only one (hopefully) that has the right data will dump it onto a bus that connects the entire memory to the main processor core. This happens in less than a cycle, because it is much simpler.

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The CPU cache is a smaller, faster memory space which stores copies of the data from the most recently used main memory locations.

The buffer cache is a main memory area which stores copies of the data from the most recently used disk locations.

The browser cache is directory or similar space which stores copies of the data from the most recently visited websites by users.

Reference: How Computer Memory Works

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protected by maple_shaft Mar 31 '14 at 11:03


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