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CMOS Digital Integrated Circuits Analysis Design 3rd Edition

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Chapter: Problem:

9.1 Consider the CMOS circuit shown in Fig. P9.1 that was designed to drive a total capacitive load of CL = 0.2 pF. For the n-channel devices, assume zero bias threshold voltage VT0 = 1.0V and transconductance parameter k′n= 50 μA/V2. For the p-channel devices, assume VT0 = -1.0 V and k′p = 25 μA/V2. For all the devices, assume the W/L ratios for each device is shown in the figure. The initial voltage across the load capacitor CL is 0 V. The waveform at input E is identically 0V for all time. For the clock CK and the rest of the inputs, the waveforms are also shown in the figure. Sketch the voltage waveform across the load capacitor CL and provide clear marking of the 50% crossings along the time axis in nanoseconds for both rise and fall transitions. [Hint: The n-channel transistor group can be approximated by a single equivalent n-channel transistor and either an average current method or a state equation method may be used to compute the required delay times.


Figure P9.1

Chapter: Problem:
  • Step 1 of 1

    Since the input E is kept low all the time, only A,B,C and F branches are conducting, thus, the equivalent transistor of nMOS block has


    Thus, the circuit can be reduced to an inverter circuit with



    (i) Charge up phase:

    Assume the time it takes for the transistor to stay in saturation region is τs then,


    The time it takes from saturation region to 50% VDD is



    (ii) Falling phase:

    The equations are the same except the nMOS transconductance is twice that of pMOS.



    The plot is shown in the following.

Corresponding Textbook

CMOS Digital Integrated Circuits Analysis & Design 3rd edition 9780072460537 0072460539
CMOS Digital Integrated Circuits Analysis Design | 3rd Edition
9780072460537ISBN-13: 0072460539ISBN: Yusuf Leblebici, Sung Mo Kang, Sung Mo Steve KangAuthors: