Essentially, a new phase-locked loop (PLL)/synthesizer combines a voltagecontrolled oscillator (VCO) and a PLL in a package that is only slightly larger than a VCO alone. Dubbed the CPLL58- 4240-4240, this PLL/ synthesizer typically offers phase noise of -95 dBc/Hz at 10 kHz offset from the carrier while delivering at least +3 dBm output power. The VCO draws 5 VDC while the PLL requires 3 VDC. The PLL/synthesizer usually provides second harmonic suppression of -15 dBc. It operates at 4240 MHz with typical tuning steps of 2500 kHz. The CPLL58-4240-4240 only requires external frequency reference and supply voltages for the internal PLL and VCO. It is programmed using a standard threeline interface (data, clock, and load enable). The CPLL58-4240-4240 targets telecommunications, computers, radio equipment, base stations, and other electronic applications. It is housed in a 0.582-x-0.8- x-0.15-in. SMD package.


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