Turing Trains


computational train track layouts


Random Access Memory Cell

Computers need to store and retrieve data from memory. Random Access Memory (RAM) provides a number of memory loations that data can be read from or written to.

The circuit shows 4 memory locations of 3 bits each. The RAM is controlled from register Z. Bits 1 and 2 hold the address. Bits 4, 5 and 6 hold the data to be written into memory, or the data retrieved from memory. Bit 3 is set to 0 to read, or 1 to write.


Only points in the Z register are operable. Set them to read data from, or write data to specific memory locations.

multiplier circuit
Click layout to pause/run train Click points to switch 0/1 Click start circle to reset train/points
lazy point Lazy points switch between upper 0 or lower 1 branch lines
Trains arriving on a branch line switch the point to that line
sprung point Sprung points allow branch line trains to join the main line
All main line trains go straight ahead and never 'branch off'


  1. The read/write points are bypassed so that they are not switched by the train on its return journey.

Turing Trains | cr31.co.uk | 2018


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