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SDR based module for Low Power WAN nodes development

Rizwan, Muhammad (2020) SDR based module for Low Power WAN nodes development.

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Abstract:In the present digital and high-speed wireless era, there is an increased need to meet the data services demand while maintaining the power consumption to a minimum. It is always a compromise between critical requirements with the lesser critical ones. Wireless Sensor Networks (WSN) have revolutionized the common man’s life with their enhanced usage in a multitude of applications ranging from personal space to industrial monitoring. The Internet of Things (IoT) is a sub-domain of the WSN which has been used in several applications such as health monitoring, temperature monitoring, humidity monitoring, pressure monitoring, and calculating electricity consumption in smart meters. In an application, a sensor node is present where data rates and energy requirements are low except for smart power meters. Smart power meter sensors have the main power supply as a primary energy source, so power consumption is not an issue there. Due to the appealing features of sensor nodes, they are being deployed almost in every field. Although sensor nodes are an attractive choice due to their appealing features, they can pose some additional challenges. One of the key challenges is their accessibility in case of an update of the technology, a protocol, or a new physical layer installation. Since a network consists of hundreds of sensor nodes that are spread over a geographical area, the only plausible option in before mentioned circumstances is the redeployment of nodes. In addition, most of the nodes are placed in a hardly accessible area; replacement is not desirable due to logistics and installing issues. In our work, we focus on the development of a reconfigurable Low Power Wide Area Network (LPWAN) nodes, to circumvent the challenges and make the upgrading process cost-effective and simple. We investigate several software-defined radio (SDR) choices, and present a hybrid solution for final implementation. The hybrid solution consists of a Field Programmable Gate Array (FPGA), a microcontroller, and a radio frequency (RF) transceiver chip. A point to point transceiver is designed and tested at a data rate of 100 bps using quadrature phase shift keying (QPSK) modulation. A sensor node works on low data rates, which require narrowband filters for improving signal-to-noise ratio (SNR) and sample rate conversion. Two types of low pass filters are simulated for sample rate conversion and efficient hardware resources realization. The Finite Impulse Response (FIR) filters are simulated in the initial design due to the simplicity and ease of implementation on hardware. The FIR filters are easy to implement, but they have high hardware resource requirements due to extensive multipliers usage. The cascaded integrator-comb (CIC) low pass filters are efficient in such applications due to their multiplier-less structure, but the passband droop limits their advantages. Moreover, hardware resources are fewer in a sensor node for minimizing power consumption on a coin cell battery. The proof of concept is verified and analyzed through simulations in the Simulink. It is deduced that the CIC filters are an optimum solution for resource constraint design, and cascading an FIR filter at the lower sampling frequency side can correct the passband droop . A successful transmission and reception of a 200-bit packet verify the proof of concept in Hardware Description Language (HDL) based simulations. The MATLAB HDL coder shortens the development time by directly generating the HDL codes for the system design. The block diagram developed in the Simulink can serve as a basic structure on which new physical layers can be implemented and verified for the sensor node.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Electrical Engineering MSc (60353)
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