Translate page

Tuesday, February 22, 2011

Clock Reconvergence Pessimism (CRP) basic

Full Form :

CRP : Clock Reconvergence Pessimism.

What is CRP (Clock Reconvergence Pessimism)?

As the "convergence" means (dictionary) "the occurrence of two or more things coming together". So we can assume that its also related to 2 clock path coming together. (Please refer the another blog for understanding the Clock path- Static Timing Analysis Basic: Part1 "Timing Paths")

Now lets assume 2 flip-flop circuit as shown in the figure.

Clock Reconvergence Pessimism
As you can see that flop share a common clock but are placed physically at the different places in the same die. Or in other way you can say that Launch clock path and capture clock path (Please refer Static Timing Analysis Basic: Part1 "Timing Paths" for defination of Launch and Capture Clock path)  share a common segment in the clock tree till the point know as "common point" (in above fig you can see that "common point" is written as "The clock path common to both flops till this point"). The 2 clock path diverse from that point.

As we know that every cell has two type of delay as a part of its specification, "Max Delay" and "Min delay". There are several scenario in the design where we use either max delay or min delay of a particular cell. Such as best case analysis (BC), worst case (WC) analysis, OCV (on chip variation) analysis during timing analysis.

Lets consider that max delay and min delay of the common segment is as
Max delay=1.2ns
Min Delay=1.0ns.

Now, if during timing analysis a condition arise where you have to use max delay for one timing path and min delay for another timing path (such as during OCV analysis), you have to use 2 different values for a common path. But practically same set of cells can't be behave different for different clock path.

For example, for a setup check, it uses the maximum delay for the launch clock path (1.2ns + delay because of rest of the circuit in the launch path) and the minimum delay for the capture clock path (1.0ns + delay because of rest of the circuit in the launch path.

In a physical design, however, the cells along the common portion of the clock tree cannot simultaneously achieve their maximum and minimum delay values. Thus there will be a single value of delay to the common point that will be propagated to both the launching and capturing clock paths. This conflicts with our timing analysis method described above since we utilise two sets of delay values at the common point.

Therefore our timing report contains artificially introduced pessimism that is derived from our usage of max and min delay for the launching and capturing paths along this common portion of the clock network. The value of this pessimism, is the difference between max and min delay at the common point in the clock network.
The amount of pessimism due to this effect (in this example, 0.2 ns) is called "clock reconvergence pessimism".

Clock reconvergence pessimism = (maximum clock delay) - (minimum clock delay)

Note: Above situation is identical for hold checks also.
Similar type of situation can arise in different type of circuit also. Lets discuss one of that. Please see the following fig.

Schematic of a reconvergent clock
The two clock paths that feed into the multiplexer cannot be active at the same time, but an analysis could consider both the shorter and longer paths for one setup or hold check. This results in different launch and capture clock path delays and the consequent pessimism.

How to remove CRP ?

Automated correction of this inaccuracy is called clock reconvergence pessimism removal (CRPR). By default , most of the tools (EDA tools for timing calculation) disable this feature (automated correction). By you can enable this feature by setting one/more variables during timing analysis. Different Tools have different variable for this. For that please refer the USER GUIDE or MANUAL of corresponding tool.



  2. hi sir..Excellent explanation...
    Ex:Max=5,Min=2...CRP=5-2=3;(i did not understand this 3 imples what??)
    SLACk=Arrival Time-Requried Time(3(only common path of A.T)-3(common path of R.T))=0 finally common path delay not impacting on slack.)
    if i took only max(5-5) also final slack=0 or if i took min(3-3) also=0 for common pathes....why we are define this formula???

    1. Hi Praveen,

      First of all ... I become confuse with your figures. But I got your point... As such the solution is in the blog itself. :)

      There are 2 types of Slack- Setup Slack and Hold Slack.

      Setup Slack= required time (min) - Arrival time (max)
      so when you are calculating these delay and if there is any common path between Arrival path and Required path -- then for that common path you are calculating the dealy 2 times (1st max delay as per Arrival path ; 2nd min delay as per required time).

      So just to avoid this situation-- we have the concept of CRP.

      Please refer the STA blog for more detail regarding the calculation of setup and hold.

      I hope you get my point. Let me know in case of any confusion.

  3. hi,
    Nice explanation. I have one doubt in CRPR.
    Suppose, If the timing path is Half-Cycle path, then how to calculate the CRPR. Can any one explain this with some suitable diagrams?

    1. no effect -- even if the timing path is half cycle or full cycle.
      here we are talking about the delay. Max delay and min delay of a path/cell. So this will be same whether the path is half cycle or full cycle.

    2. hi,
      in case of half cycle paths, CRPR calculation will be different because the rise & fall delays of cells in the common path are different. this delay difference cant be removed. but tool will remove the difference which is smaller in the below two cases.
      1) difference with rise delay in common path
      2) difference with fall delay in common path

    3. The calculation you are talking about .. is part of max and min delay calculation of common path. so if you have calculated the max and min delay of the common path considering all the factors .. then there is no difference whether it's a half cycle or full cycle.

    4. I agree with Anon1. CRP calculation for half-cycle path will be different. By default, Primetime will not remove CRP for half-clock paths.
      It is not valid to assume the launch edge (say clock rising, coming from PMOS) will be similar to the capture edge (clock falling, coming from NMOS). What applies to the posedge doesn't necessarily apply to the negedge.

  4. sir,
    first of all thank u very much for this blog. this is very helpful for a student like me !!!!
    i hav doubt , why we need this CRPR?? The worst case will be "with out CRPR ",right? ie max delay-for launching & min delay for capturing!!!(if we set the crpr it will take only one value to the common cell delay for both launching and capturing path)
    and what will b the value of that common cell delay taken by the tool if we enable crpr?

    1. due to my understanding, the worst case will be "with out CRPR", but it will not happen in the real world. So by default we need to enable CRPR.

      When we enable CRPR, if you are running setup time check, the common cell will use max delay timing info, if you are running hold time check, the common cell will use min delay timing info. I am not sure about it, just my 2 cents. Anybody knows about it please help on this.

    2. looks like still confusion .... CRP is the difference between the max and min delay of the common path. This is the value which indicate how much is the pessimism. (Means worst possible outcome).
      So in general we don't enable CRPR (automated way to correct this pessimism) because it takes a lot of time (Tool run time increases a lot).
      Without enabling CRPR, we calculate the slack or say timing violations. if every thing is good then no need to enable this but if there are violations in certain paths, we enable CRPR mode in the tool for those paths.
      Tool automatically remove the pessimism (as per it's algorithm) and then check the violations. Now if no of violation decreases (which should be), then the final number of violations are considered as real violations. Because now we are talking about practically possible violation (at least not considering non-practical situation of having min and max delay simultaneously in few cells).
      Now if you are asking about what will be that common value - It depends on the tool algorithm.

  5. Hi. Amazing explanation.
    I have a qn, so can I infer that one cannot do multiple corner OCV analysis for clock paths which are converging?

    In that case most of the paths fall under the category which you explained.

    1. you can do that if you are doing multiple corner analysis. Point is if you are doing analysis in a specific corner and then you want to use 2 different value for a single path - we should avoid that.

      hope I am able to ans your question.

  6. Hi,

    when i am using primetime, in report_timing report I can see this CRPR added in clock path. But this value should be removed right? or am i understanding in a wrong way? please correct me if i am wrong

    1. report is for setup or hold ?

    2. Hi,
      It's fine both way, as long as it is being done correctly. The difference can either be added to the min path or subtracted from the max path. Either way should be correct.

  7. hi, i have one question, does clock reconvergence pessimism removal ( CRPR ) the same s Common Path Pessimism Removal ( CPPR ), i am a little confused with these two. thank you very much.

    1. These are same. Actually CPPR - is Clock path pessimism Removal

    2. Hi,

      I would like to know do we consider CRPR for hold violation. I mean to say how we consider the CRPR number in hold timing report.

      Here I have attached a snapshot of the setup timing report where we add the CRPR number with the required time to remove the extra pessimism.

      UCKBUF0/C (CKB ) 0.045 10.045 r
      UCKBUF2/C (CKB ) 0.054 10.098 r
      UFF1/CK (DF ) 0.000 10.098 r
      clock reconvergence pessimism 0.011 10.110
      clock uncertainty -0.300 9.810 r

      Kindly get back to us.

      Thanks in Advance.


  8. Hi,
    I have a question about CPPR in STA report.
    As I have a XOR clock circuit in design ( clk_xor = clk_src ^ reg_clk_src_polarity), and I use clk_xor into the module A. (create_clk on clk_src)
    In the timing report(MAX), it show launch path clcok is from clk_src, capture path clock is from clk_src'. As in the module A, it should be same clock edge input in real case (reg_clk_src_polarity is config register), how could I avoid the timing violation ? ( I need to set_case_analysis 0/1 reg_clk_src_polarity seperately report_timing or some else tool can avoid different edge into module A ?)

    Startpoint: u_A/cnt_reg_0_
    (rising edge-triggered flip-flop clocked by clk_src)
    Endpoint: u_A/cnt_reg_0_
    (rising edge-triggered flip-flop clocked by clk_src')
    Path Group: clk_src
    Path Type: max
    Min Clock Paths Derating Factor : 0.900(cell) 1.000(net)

    Point Incr Path
    clock clk_src (rise edge) 0.000 0.000
    clock network delay (ideal) 0.000 0.000
    0.000 0.000 r
    u_A/cnt_reg_0_/Q <-
    0.381 0.381 f
    u_A/U2/ZN 0.344 0.725 r
    u_A/cnt_reg_0_/D <-
    0.000 0.725 r
    data arrival time 0.725

    clock clk_src' (rise edge) 1.250 1.250
    clock network delay (ideal) 0.000 1.250
    clock reconvergence pessimism 0.000 1.250
    clock uncertainty -0.500 0.750
    u_A/cnt_reg_0_/CP 0.750 r
    library setup time -0.049 0.701
    data required time 0.701

    data required time 0.701
    data arrival time -0.725
    slack (VIOLATED) -0.024

  9. My brother recommended I might like this website. He was entirely right.
    This post actually made my day. You can not imagine just
    how much time I had spent for this information!

  10. Awesome! Its actually awesome piece of writing, I
    have got much clear idea regarding from this post.



Must Read Article

Related Posts Plugin for WordPress, Blogger...

Follow by Email