﻿ Dive Into Bluespec System Verilog
Warning: This tutorial assumes basic knowledge of HDLs

What is Bluespec System Verilog (also called just Bluespec or, simply BSV)?

  • BSV is a more recently developed hardware description language (HDL).
  • The language is primarily for synthesizing the gate design, not for verification.
  • Since most industry tools largely require Verilog these days, BSV can compile into Verilog. It is acceptable to think of BSV as a verilog creation tool. This feature also makes it easy to fit into the Verilog code most projects have laying around.

Why this BSV tutorial?

The Bluespec resources available do an outstanding job learning the technical nitty gritty of the language. It is highly suggested the reader reference them for questions. Or even that they already understand the basics. This tutorial ramps up quickly. Where these resources fall short is helping the designer think efficiently in terms of rules and the other features of the language. In this tutorial, we are trying to think about these new features as soon as possible.

Why Learn Bluespec System Verilog?

Verilog was created in the 1980’s and even with the upgrade of System Verilog, the language lacks much of the innovation present in modern languages. If you know languages like Python, Scala, or some Lisp derivative, you’ll understand what I mean. Many EDA industry veterans have a hard time with this. To an extent Verilog is great. A veteran can create any desired circuit in a well practiced, familiar manner.

However, as programming languages have evolved over time, dominate traits have come forward. These language features are now considered highly desirable and System Verilog lacks many of them. We will be going over some of these features in this tutorial.

The argument about whether these new features are important is a difficult one to have. The inherent difficulty in deciding whether or not a language feature is important is that a designer needs to be proficient with that feature in order to truly judge it. Usually, new language discussions are unproductive because of this. If everyone in the room doesn’t know why it is nice to use higher order functions like map() and fold(), the discussion is largely based on human persuasions such as natural leadership and how articulate the speakers are.

That being said, an unbiased viewer can look around the realm of algorithmic languages and see a consistent trend toward and championing of these features.

Hold on now. Not use (System) Verilog?

Yes. I’m completely serious. By modern standards (System) Verilog sucks. These languages can produce the exact same circuits, but the thought processes and worries of the designer are very different.