3-D Integration Is the Way to Go



he need for system-size reduction, high-performance interconnects, and heterogeneous integration of true system-on-chip (SoC) is driving the packaging world towards 3-D chip integration. The most popular 3-D package is the stacked-die package, which uses standard BGA technology to create a 3-D die-stack. Although this approach is interesting because it uses the existing infrastructure, there are limitations to consider when developing advanced systems and scaled semiconductor devices.

The ideal alternative should allow for high-density 3-D interconnects, as high-speed and low-power applications demand short interconnects with low parasitic capacitance. Impact on the active front-end-of-line (FEOL) and back-end-of-line (BEOL) area should be minimal. It should allow for stacking different die sizes and answer the known-good-die (KGD) problem. Finally, it should be cost-effective and easily applicable in industrial production chains.

Figure 1. IMEC´s 3-D packaging and interconnection roadmap for 3-D-SIP, 3-D-WLP and 3-D-SIC technology families.
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The most mature technology is 3-D system-in-package (SiP), which consists of clearly defined sub-systems, each integrated as individual SiPs. In this way, only modest 3-D interconnect density is needed and testing of different SiP layers is relatively simple. This 3-D-SiP technology is particularly interesting for realizing so-called ambient-intelligence systems consisting of different subsystems such as a radio layer, an application layer, and a power-management layer. These 2-D subsystems can be stacked on top of each other, realizing a dense 3-D-SiP system.

3-D interconnection schemes that use wafer-level packaging (WLP) infrastructure to realize 3-D electrical connections increase interconnect complexity further. One process has been developed using 3-D through-silicon vias (TSVs) that consist of a 2- to 5-µm-thick polymer isolation layer deposited by spin or spray coating, electroplated copper, and a polymer coating on top. Wafers are then stacked using a method similar to flip-chip mounting. A simple process flow makes this method cost effective and reduces capacitance and thermo-mechanical stresses. Another 3-D-WLP option is stacking of thin dice on active device wafers using multilayer thin-film technology to interconnect the thin die with the host wafer. This enables a high degree of system-level flexibility, and high integration density. Furthermore, dice of different sizes can be stacked on top of each other and thin-film passive components can easily be integrated in the stack.

Ultimately, 3-D interconnection can be done using silicon-foundry technology. This approach, creating very high density vertical interconnects, is still being explored at R&D centers. The technology is being used to connect large circuit blocks with global and intermediate BEOL on-chip interconnects, but also to connect small circuits, logic gates, and transistors with interconnects at the local BEOL wiring hierarchy in the true 3-D-stacked-IC approach. In the latter case, vias are mostly realized after finalizing the IC process. At one R&D facility,* however, copper nails are used between the FEOL and BEOL processes. 3-D stacking is performed as a die-to-wafer bonding process, similar to 3-D WLP; the difference is that copper-copper direct bonding is used rather than a solder joint or micro-bump connection. This approach shows several advantages: minimal impact on CMOS wafer design and processing, a high module yield (only KDG are stacked), and no impact on BEOL. Because the copper nails are very small, there is only a small exclusion area on the FEOL.

All these 3-D approaches exist next to each other. Their specific characteristics make them suited for specific applications. They are indispensable to enable further system miniaturization and performance enhancement. 3-D integration definitely is the way to go.


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ERIC BEYNE, program director, may be contacted at IMEC, Kapeldreef 75, B3001 Leuven, Belgium; +32 16 281 880; E-mail: