Date: 20010712 From: Uwe Zimmermann To: Multiple recipients of list CHIPDIR-L Subject: Open inputs (Re: Hot Chip) Andy wrote > I would disagree. Admittedly it's been a while since I used ordinary TTL > chips in a design, but I recall seeing curves of power dissipation vs. > frequency (for a gate or a flop). They certainly were a lot flatter than > CMOS (which is almost exactly linear with frequency), but not as flat as ECL > (which truly was almost a flat horizontal line). As you approached the > upper freq. limit for a TTL device, the power vs. freq. plot would curve > somewhat more upwards. You're right about the upward bending of the TTL power consumption at highest frequencies, but this makes according to my sources only a factor of 2-3 compared to the DC power consumption which is valid up to about 1-10MHz. Here is what TI has to say about design rules concerning unused inputs: General rule - don't let them float, as Andy and I stated earlier... -------------------- quote on -------------------- 3 Unused Inputs In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used. Such parts should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. A rule that must be observed under all circumstances is: All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. As a result of the input circuits of bipolar devices, a high level is established at open-circuited inputs. The voltage at such an input corresponds to the threshold voltage of the input circuit (about 1.4 V or 1.1 V with devices from the SN74LS family). In a test of the function of such a circuit, this order of voltage at the input, in general, indicates that this circuit is open. CMOS inputs are of such high impedance that the smallest change on the open input can generate any undesired logic level. A slight change of the capacitance at the unconnected input, for example, by bringing the hand close to the package, can so change the effective voltage at the input that a high level can change into a low level, or vice versa. Additionally, for the same reasons mentioned, unconnected inputs may react to all kinds of coupled-in interference voltages, and the behavior of the circuit can no longer be predicted. With gates, another solution is to connect unused inputs to an input of the same gate that is in use. The function of the device is unaffected. This circuit arrangement can be used equally well with AND (NAND) as with OR (NOR) gates (see Figure 9). Here, connecting the inputs together increases the capacitive load on the driver stage and, with bipolar circuits, also increases the dc current drain. In many cases, the simple method shown here cannot be used, especially if the unused inputs are not part of the same gate function. In this case, a defined logic level must be applied to the unused inputs. If a low level is required, the input should be directly connected to GND; if a high level is required, it should be connected with a voltage source corresponding with a high level. In general, this is the positive supply voltage V CC . Figure 10 shows how, in the previously mentioned cases, a fixed potential should be connected to unused inputs. Note that a high level should be applied to the unused inputs of an AND (NAND) function and a low level to unused inputs of an OR (NOR) function. Devices with multiple-emitter inputs (SN74 and SN74S series) are exceptions. Since no voltage greater than 5.5 V should be applied to the inputs (because if exceeded, the base-emitter junction at the inputs breaks down), the inputs of these devices must be connected to the supply voltage V CC via series resistor R S (see Figure 11). This resistor should be dimensioned such that the current flowing into the gate or gates, which results from overvoltage, does not exceed 1 mA. But, because the high-level input current of the circuits connected to the gate flows through this resistor, the resistor should be dimensioned so that the voltage drop across it still allows the required high level. Equations 1 and 2 are for dimensioning resistor R S , and several inputs can be connected to a high level via a single resistor if the following conditions are met: RS(min) = (VCCP - 5.5V)/1 mA RS(max) = (VCC(min) - 2.4V)/(n * IIH) Where: n = number of inputs connected IIH = high input current (typical 40 uA) VCC(min) = minimum supply voltage VCC VCCP = maximum peak voltage of the supply voltage V CC (about 7 V) If part of a device is unused, the unused-input rules should be applied. If, for example, in an application only one flip-flop from a dual flip-flop type SN74ALS74 is used, all inputs of the unused flip-flop should be connected to a defined logic level, which, in this case, could be either low or high. -------------------- quote off -------------------- Uwe. -- Author: Uwe Zimmermann