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I am sampling a video signal from a linear imager. I noticed when the illumination is just at the intensity when the ADC increases by another MSB bit at the output, the noise occurs. That is, when ADC transitions from 0111 to 1000, 01111 to 10000 and so on. It happens at every transition. At least, this is how it appears to me. What could be the source of such noise?

enter image description here

I suspect, this happens somewhere on the digital side of the circuit. Here's the quantitative profile of the image intensity at the line20:

enter image description here

Here's the sample clock signal before and after the gate buffer:

yellow: 0-3.3V


enter image description here

EDIT: In short: the problem was with timing that is discussed in this post and the bad grounding that is discussed here

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I would assume it to be just an effect from the switching off of those outputs on the adc. The noise goes away thereafter the ADC has switched to 1000, right? –  Funkyguy Jul 18 '14 at 14:43
@ShannonStrutz Well, as I increase the illumination, the brightness on the image increases. But at some point, the noise appears. As I keep increasing the illumination, the noise goes away and the image gets brighter. After increasing the illumination even more, the noise appears again. Then disappears. And so on until ADC saturation. –  Naz Jul 18 '14 at 14:49
On the image above, I could not produce a good intensity gradient to demonstrate the noise with periodic occurrence relative to illumination intensity. –  Naz Jul 18 '14 at 14:51
Okay, that makes sense. Then my first instinct would be that is coming from the internal switching of the ADC –  Funkyguy Jul 18 '14 at 14:52
Look at the power supply rails with a 'scope... (AC coupled maybe) Then try some more bypass capacitance. I'll sometimes add a bit of resistance (1-10 ohms) in the supply line to the "noisy" chip with a bypass cap after the R. (Maybe bypass caps on both sides.) –  George Herold Jul 18 '14 at 15:02

2 Answers 2

up vote 6 down vote accepted

Placeholder's valid comments notwithstanding, the noise you are seeing is indicative of a timing skew problem among the digital bits coming out of the ADC. Instead of xxx10000 and xxx01111, you are occasionally getting xxx00000 and xxx11111.

I see the clock going into the ADC, but I don't see the next place in the datapath where the data is clocked again. Be sure that the timing delays (resistors, buffer, connectors, wiring, etc.) on the data lines still meet the setup and hold requirements for wherever that reclocking occurs. Pay attention to clock skew among the boards, too.

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I sample the signal from via NI PCI6259. The sampling trigger is the same clock as for the ADC. I assume the signal from CPLD is identical, then it follows identical SGLs, one for each. I expect that the PCI board lags the trigger clock because of: 1) small delay in the buffer and 2) the setup delay in the PCI internal circuitry. But then, I could have random noise not correlated with 2^n transitions. Right? –  Naz Jul 18 '14 at 15:42
I skimmed through the manual for the PCI6259, but couldn't easily see its setup/hold requirements for the digital inputs. Can you try sampling the data on the opposite edge of the clock? –  Dave Tweed Jul 18 '14 at 15:55
Strangely, do not see the difference. –  Naz Jul 18 '14 at 15:58
I just halfed sampling frequency and noise disappeared. Any clues? –  Naz Jul 18 '14 at 16:02
It means we're on the right track. What sampling frequency are you using? You never said. –  Dave Tweed Jul 18 '14 at 16:04

I'll start off by saying that you appear to be taking care of a few things correctly. Controlling edge rates(resistors), adding a buffer/driver (745402) etc.

Well you can probably rule out the ADC internal workings, Analog is an excellent company, they know what they are doing and they've sold lots of those devices, and I've used these devices in this exact application with good results.

Now for the constructive criticism.

The ADC is a very sensitive device (wide BW and high level of conversion) you have to be careful.

Power supplies:

  • for these applications I typically run dedicated LDO's, filters before (Pi filters with L's and C's) and after for the buffers and the ADC's - all separate.

Clock driver for ADC:

  • rail bounce on the clock source manifests itself in jitter on the sampling aperture which manifests itself in MSB counting noise. - separate power supply and driver form the clock. The SGL (Single gate Logic) is your friend.

Layout - Layout and yet again layout:

  • Is very important. BE aware of image current flow, the return paths of the signals that are running to the buffers. Ground plane splits etc. etc.

Some more obscure things: - some resistor packs are nasty, additional inductance and cross -coupling capacitance. It wouldn't necessarily affect your results here. I tend to use individual resistors (0402)

As per DaveTweed excellent observation (re timing skew) one solution is to replace the buffers in your schematic with D ff's /latches to reclock the data and buffer it at the same time. I normally do that and Dave's comment reminded me.

After update (comments about clocking);

I never, ever , ever allow FPGA, CPLD inputs into an ADC. I either run a separate clock source or if I have to have a specific clock frequency that is generated, I reclock using SGL's (D FF's) at a higher frequency (paying attention to setup and hold times of course). The reason for this is that the structure of FPGA's and CPL's causes a lot of power rail sourced jitter in the timing of the outputs from these devices. This jitter in turn interacts with the sampling window of the aperature period of the ADC front end causing noise problems.

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Please, see the update. My ADC has a separate LDO power supply (ADC_Vcc). The clock comes from a CPLD through an SGL, where CPLD and SGL share the same power supply. I do use PI filters with ferite beads. Regarding the layout, that's my first experience, but I have a second ground plane, with no splits, though. Could you please, see if that would be a problem? –  Naz Jul 18 '14 at 15:24
@Naz I updated the post. However, that probably would NOT have the pattern that you are seeing (i.e. SSO - Simultaneously Switching Outputs) on majority movement. However, I will note that having your SGL on the same rails at the CPLD is a big issue. Are you feeding the data back into teh same CPLD? –  placeholder Jul 18 '14 at 15:33
the data is fed to NI PCI6259 for sampling. However, eventually it will be fed back to the CPLD or FPGA. Why is it a big issue? –  Naz Jul 18 '14 at 15:49

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