4-tick Logic
by Nyles Heise

Why 4-Tick?

The designs of WireWorld machines that I am aware of all have used 6-tick, or higher, devices. The basic logic devices have the simplest constructs if signals are spaced at least 6 cells apart. I am not showing any the 6-tick devices on the page. If you're interested, a very good presentation on this subject can be found on Karl Scherer's web site. The devices presented here all require my 4-tick methodology. Some of the layouts were done by Karl.

4-tick logic gates are more complicated but have an advantage in two areas: speed and size.

In some situations 4-tick logic is 1/3 faster than 6-tick. An example is the binary multiplier, where strings of inputs are supplied to a logic machine that produces a new output every 4 ticks. But even in a sequential, clocked machine dominated by random logic 4-tick offers several advantages. Clock loops are 4-cell rather than 6. And wiring is generally easier, since there are only 4 phases to match at the input to all logic gates.

As with speed, the area of portions of designs are about 1/3 less for 4-tick than 6-tick. 4-tick loops have data packed one bit per every four cells rather than every six. The random logic area, however, may take more space with 4-tick since some 4-tick elements are more complicated and larger than 6-tick.

Why Can't 6-Tick Devices be Used at a 4-Tick Speed?

Basically most 6-tick logic elements are constructed from three underlying elements: the OR, ANDNOT (A AND NOT B), and XOR gates. They are shown here. Inputs come from the left, and outputs leave to the right.

Three Underlying Elements

The OR gate actually works at 3-tick or higher, however, the ANDNOT and XOR gates do not work if the data is spaced at 4 cells. The reason they don't work at 4-tick is that for some combinations of inputs the electron from one input does not have time to die out, and consequently it blocks the other input from entering the gate.

Here's how a normally operating ANDNOT gate works with 6-tick inputs. The leftmost configuration shows the gate at a particular point in time. The next 8 show how the electrons move for the next 8 clock times. The allowing electron, A, is the bottom input. The inhibiting electron, B, in the top input. Notice in the second last configuration that an inhibiting electron has blocked the second allowing electron from passing through the gate.

Operational ANDNOT Gate, 6-tick

And here's what happens if the data is spaced 4 cells apart. The inhibiting electron is blocked from entering the gate and both allowing electrons pass through.

Malfunctioning ANDNOT Gate, 4-tick

The Birth of 4-Tick Logic

It turns out there is a way to make all logic gates work at 4-tick speeds. For the ANDNOT gate, the trick is to keep the inhibiting electron from being blocked by an allowing electron when the previous inhibiting electron was absent. One way this can be done is by ORing the inhibiting signal with a 4-tick loop whose electron is one tick later in phase. We are in effect blocking the allowing electron from blocking the inhibiting electron. (Er, is that a double negative?) Here's a functioning 4-tick ANDNOT gate.

Operational ANDNOT Gate, 4-tick

The 4-tick Logic Gates

If you have a NOR gate you can construct any other logic gate you want. Or if you have a NAND. Or an OR and Inverter. Or and AND and an Inverter. In this section we present a set of 4-tick logic gates, sufficient to build a complex machine such as the binary multiplier or Turing machine. The logic in each of these is made up of the gates presented here.


The 4-tick loop appendage is the way I originally envisioned blocking unwanted electrons, however, there is another approach. For the ANDNOT gate the only time this allowing electron must be blocked is when the allowing electron is present. So instead of using a 4-tick appendage to OR with the inhibiting electron, the allowing electron itself can be used, delayed by 1-tick. This eliminates the 4-tick loop, which always has an electron, even when both inputs are off. Layout of the second version was done by Karl Scherer.

Two configurations for the 4-tick ANDNOT

True AND Gate

The ANDNOT gate is not a real AND gate. The normal configuration for a 6-tick AND gate is made up of two ANDNOT gates. Another possibility is an INVERTER and an ANDNOT gate. The AND gate I'm showing here is of the latter type. It is a very pleasing configuration laid out by Karl Scherer.

True 4-tick AND Gate

The Exclusive OR

The story for the XOR is similar to that of the ANDNOT, except that both electrons need to be blocked. Again two approaches exist, adding a 4-loop appendage or ORing each input with the 1-tick delay of the other input. Part of the 6-tick XOR layout exists for the purpose of blocking reverse traveling electrons. About half of the normal 6-tick XOR cells are not needed since the 4-tick has its own blocking method.

Two configurations for the 4-tick XOR

The Inverter

The inversion of a signal, A, is done by using the fact that the XOR of A and 1 is NOT A. The Inverter can be viewed as a very compact XOR, 4-tick loop, and diode. There are two possible locations for the loop.

Two configurations for the 4-tick Inverter

The Set/Reset Latch

The Set/Reset latch has two inputs, Set and Reset (duh!) and one output, the state of the latch. It is in effect made up or three elements, a 4-tick loop, an OR gate, and an ANDNOT gate. The ANDNOT gate must be of the 4-loop appendage type. The latch can be either set dominant or reset dominant, depending upon where the set signal is applied. The RS Latch is used in the Binary Multiplier.

The 4-tick Set/Reset Latch

The Trigger Latch

The Trigger latch, or flip-flop, has one input and one output. When the input is present the output changes state. The latch is very compact, indeed, smaller than 5-tick, 6-tick, or higher. The trigger latch is used in the Turing Unary Multiplier.

The 4-tick Trigger Latch

Complex Representation

There are two ways of looking at 4-cycle logic. The first is that the gates are slightly more involved than 6-cycle, requiring a delayed 1 bit to be ORed with inputs before the actual logic gates.

Another way is the following. Normal representation of data is 1 = HT00 and 0 = 0000. Call this the Real representation. Most 4-cycle logic actually works with a Complex representation of 1 = HT00 and 0 = 0HT0. If signals are complex then the gates become very simple. Many take less space than the 6-cycle equivalents. The outputs of most gates are Real, however, so must be converted to Complex at some point. Simple Real-to-Complex and Complex-to-Real converters exist.

There are way too many cool configurations to go over in detail, so I'm going to pick out a few of the neatest. More are given in Karl Scherer's Heise_WireWorld to Zillions of Games.

Complex ANDNOT

The 4-tick ANDNOT presented above has a Real allowing input and a Complex inhibiting input. A more versatile layout exists when both inputs are Complex. The inhibiting input must enter at the midpoint of the gate, but the allowing input may enter from either end and from any one of three directions.

Three Configurations for the Complex 4-tick ANDNOT

Complex XOR

The Complex 4-tick XOR is not only smaller than a 6-tick XOR, but also more versatile. One of the inputs must touch exactly two of the cells in the gate, but the other may touch the normal two or only one. And if it touches only one it may come from one of several directions. Without this feature the 4-tick Trigger latch would not exist.

Six Configurations for the Complex 4-tick XOR


The real inversion of a Complex signal is generated very efficiently. You may note that this is an application of the Complex ANDNOT gate, where one of the inputs is the signal to be inverted and the other a 4-tick ONE.

The Complex 4-tick INVERTER

Complex OR

Even the Complex OR gate is smaller than the Real version. Yes, even the OR gate. Not much, but I amazingly saved a little space in the multiplier by using the Complex version.

Complex 4-tick OR


Real signals must often be converted to Complex. Occasionally it's nice to convert Complex to Real. Simple converters exist.

Real-to-Complex and Complex-to-Real 4-tick Converters

4-tick-type n-tick Logic

Say what? There are cases where the 4-tick concept produces smaller n-tick devices than the normally accepted ones.

6-tick Inverter

A close call is the inverter. The 4-tick inverter can be made into a 6-tick version by merely increasing the loop from 4 to 6. I think it takes a little less space. If not, it at least gives another option.

New 6-tick Inverter

6-tick AND

This AND gate was derived from a similar gate in Mark Owen's computer. It is placed in this section because it uses an inhibiting signal that is one tick different in timing from the allowing signal, like the complex gates. This time the inhibiting signal is one tick ahead of the allowing electron. The funtion performed by the gate is Z = A AND (B OR NOT(C)). The left AND gate has C=1, the right gate has C=A. The latter version is smallest AND gate I know of. Once again, thanks to Mark Owen for the basic concept of the gate.

New 6-tick AND Gates

n-tick Trigger Latch

The best example of 4-tick technology in 6-tick design is the Trigger Latch. The new version is vastly smaller that any 6-ticks that I've seen. Again, the 4-tick latch is make into a 6-tick version by increasing the loops from 4 to 6. An 8-tick version can be make by increasing the main data loop to 8. It turns out the that an appendage loop of only 4 works. 4, 6, and 8-tick Trigger Latches are shown.

4, 6, and 8-tick Trigger Latches

Other Cutesy Things

I'm sure there's lots more stuff to be discovered. Every time I think I've nailed something I come up with a better, faster way of doing it.

Here's a major minuscule, Negative-Logic, 4-tick, Real, RS latch.

As I was working on 4-tick logic I was musing over how to make the ANDNOT work. It just didn't do what I wanted. Well, it does do something. And what that is is (is that a double is? Guess it is if that's you definition of is) a negative logic, set dominant, set/reset latch.

The problem with the ANDNOT is that inhibiting electrons get blocked when the gate is on and allowing electrons continue to come. But if you think about it, that's just what you want a latch to do. In this case electrons are flowing into both inputs and out of the output. The latch is off, and both inputs of off. The latch can be set by stopping electrons from flowing into the allowing input. Now if the set is removed, electrons flow into the allowing input, the latch stays set until electrons stop flowing into the inhibiting input, that is, reset is applied.

I know. Negative logic is confusing. But it works! The allowing leg is the negative Set and the inhibiting leg is the negative Reset. The output of the latch is also negative logic.

The reason I'm so excited about this gate, is that it is as small as the OR gate!!! Not including input and output cells, the area of the device is 1 by 3!!!

Negative-Logic, 4-tick, Real, RS Latch

All the Logic

I've put most of the devises shown here into an MCell file.

All The Logic

The MCell Source Code. You'll need Mirek's Cellabration to run it.