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An EPIC tale.
















A preview of Intel's IA-64
by Hannibal

Overcoming bottlenecks in today's architectures
The real bottlenecks inherent in today's architectures come in the form of barriers to parallelism.  Let's look at what these barriers are, how they hinder parallelism, and how EPIC and IA-64 tries to overcome them.

Basically, the entire EPIC design philosophy can be summed up by the following: make use of parallel power whenever and wherever possible; and if it's not possible, make it possible.  It's all about filling those execution slots each cycle. Unused execution slots are a no-no.  If you've got four integer ops that don't depend on each other, do them all in one cycle.

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The more feature sizes shrink, the more transistors we can cram on a chip.  The more transistors we can cram on a chip, the more functional units we can have crunching numbers in parallel.  The more functional units we can have, the more execution slots we get each clock cycle.  So the key to increasing performance is in keeping those execution slots full.  In order to fill all of those execution slots each cycle, we've got to do more than just extract the parallelism that's in the code; we've got to create parallelism in code that previously had none.  This task isn't always easy to accomplish.

Branches and predication

When you're trying to squeeze the maximum performance out of today's machines, branches will eat your lunch.  Intel estimates that 20% to 30% of processor performance is eaten up by branch mispredictions.  That's quite a lot of performance that's going to waste.

The problem with branches is that they limit your freedom to schedule the code for optimum performance. They do this by breaking the code into small blocks of instructions, blocks that have to wait for some conditional instruction to evaluate before they can execute. Say you're coming up on an IF-THEN-ELSE conditional. You have a few options. One is to first evaluate the IF, then, depending on the outcome, take either the THEN path or the ELSE path. The problem with this is you've got to wait for the IF to finish before you can go on. And while you're executing that IF instruction, all these other execution slots are going to waste.

One alternative to this would be to use branch prediction. While you're waiting for that IF to evaluate, just take a guess as to what the outcome will be and execute based on that guess. If you get it right, you haven't wasted any time; if you get it wrong…that's where that 20-30% performance hit comes into effect. But even assuming you get it right, you might still have a number of execution slots going to waste.

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Those empty slots could actually be doing some useful work. The IA-64 has a simple, yet elegant, way of handling this problem.

EPIC deals with the problems which branching introduces by just getting rid of branches whenever it can. When IA-64 comes upon a conditional branch, instead of trying to predict which branch the program will take, it just takes them both.  To understand how this process works, it's best to look at an example.

Say we're chugging along, and we come upon an IF-THEN-ELSE condition.  We start evaluating the IF condition, but instead of waiting for it to finish, or trying to guess its outcome, we can execute the code in the THEN branch in parallel with the code in the ELSE branch.  When the IF condition is finished evaluating we can throw out the branch we don't need.  How do we know which code we don't need? We use predicate flags.  We assign every instruction in the THEN branch the predicate flag P1, and every instruction in the THEN branch the predicate flag P2.   When the IF condition is done with its evaluation it just sets the appropriate predicate flag to signal which branch we want to keep.

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Predication is a prime example of how the compiler and the CPU will work together under IA-64.  The compiler assigns the predicate flags to the branches.  All the CPU has to do is set the flags when it does the conditional.  IA-64 has sixty-four one-bit predicate registers that help out with this chore.

Predication can give you a pretty serious performance boost.  A study by Scott Mahlke et al. at the University of Illinois shows that, given a hypothetical eight-wide machine, you can remove over 50% of the branches and over 40% of mispredicted branches with predication. Here's the abstract and a link to the report.

Next: Memory latency and speculation



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