Over the past weeks I’ve been exploring the architecture of microprocessors in general and AEMB’s in particular. I wish I can say I am done with dissecting AEMB but I ain’t. In this blog post I will give a quick overview about my project and give a functional description of the modules I managed to grasp in AEMB.

My project is to create a few versions of the AEMB. The first version is an adjustment to the threading model of AEMB to improve its performance when running single thread. The other version is optimized for low power consumption. Hopefully, depending on the progress a third version might be conceived.

In AEMB, the instruction Wishbone interface, “iwbif” and the instruction cache, “Iche” are the modules that handle reading instructions from memory and storing them in the cache. The edk63 version of AEMB has a cache that can store 512 words (32 bits per word). It keeps track of which instructions are in the cache through a look-up table. Each entry in this look-up table can keep track of the status of one cache line (16 words) . The highest most 21 bits of an instruction address is used as a tag value saved in the look-up table. The next 5 bits are used to select a word in the look-up table. The status of a word is expressed by a single bit. First when an instruction is needed the processor looks it up in the cache. It loads it if there was an instruction hit. On misses, “iwbif” fetches the instruction from memory.

AEMB creates its internal clock, reset and flags interrupts in the “pipe module. Moreover, the signal that switches between active threads, gpha is controlled in this module.

Instruction decoding takes place in the “ctrl” module. The opcode is decoded to identify the type of instruction and this information is forwarded to the rest of the processor. Addresses of operand and destination registers are obtained from the instruction word and saved into registers to free up the pipeline for the coming instruction. Further more, control signals for forwarding the operands or the destination are created in this module and if any forwarding is needed for those data to be used in the next cycle then it takes place in this module.

Hopefully next week I’ll be able to explain the whole architecture of AEMB.