8.2. General Register Organization

Memory access is very time-consuming, especially on today's computers, which typically have many wait-states. Compounding the technological limitations on memory speed is the fact than RAM memory banks are getting bigger. Bigger memory units means longer propagation delays in decoding the address.

Memory access is also expensive in terms of the instruction code size necessary to accommodate 32 or 64-bit addresses.

If many CPU registers are available for heavily used variables and intermediate results, we can avoid memory references much of the time, thus vastly increasing program execution speed, and reducing program size.

Figure 8-2 and the diagram below show the internal bus connections for a general register organized CPU. This CPU has up to 8 general-purpose registers, which we can call R0 through R7, and an ALU with up to 16 functions.

In a general-register organization such as this one, any two registers can be inputs to the ALU, and the results from the ALU can be stored in any register. When all registers are interchangeable, the architecture is orthogonal, or symmetric. An orthogonal processor is ideal for programmers, because they can use any register for any purpose. This is the other end of the spectrum from an accumulator-based architecture.

What are some possible control functions and microoperations for this CPU?


The combined bits for selecting registers and an ALU operation is called the control word.