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Rambus’s Terabyte Bandwidth Initiative looks to 2010, many-core era

How do you get data onto a chip with 100 cores, all of which may be reading …

For the past three years, Rambus has been laying the research groundwork for eventually answering a simple question: in a world with 100 cores on a single chip, how do you get enough data onto the chip to keep all those cores fed? At that point, a single system-on-chip (SoC) in a future game console may well need something on the order of a terabyte per second worth of bandwidth—some 20x the amount of bandwidth in today's PlayStation 3.

At the company's annual developer forum in Japan, Rambus has unveiled the first fruits of this research effort: the Terabyte Bandwidth Initiative. Let's take a quick look at the TBI and at the kinds of technologies that Rambus believes can take us into the realm of 1TB/s local bus transfers.

32x data rate: when DDR isn't enough

When I was first briefed on XDR some time ago, I marveled at the technology's 8x signaling rate. In my (positively ancient) RAM Guide, I describe double data rate (DDR) signaling as a technology that lets you transfer data on both the rising and falling edges of a bus clock, for a total of two transfers per clock. Similarly, octal data rate signaling uses eight transfers per clock, but Rambus isn't stopping at eight.

A diagram of DDR signaling, from my old
Understanding Bandwidth and Latency article.

For the TBI, Rambus is working on technology that does 32 data transfers per clock beat, so that each line can transmit 32 bits per clock cycle. That's a ton of per-pin bandwidth, and it means that bandwidth will scale pretty dramatically even at low clockspeeds as you add bus wires. For instance, on a 500MHz clock that's 16Gbps per wire, a number that can be doubled by simply adding a second data link.

If you do the math, 16 DRAMs x 16 Gbps x 32 bits per DRAM gives you 1 TB/s of bandwidth onto an SoC, hence the name of the initiative. Because this 16Gbps link is the real target of the TBI and 32x signaling is the vehicle, both TBI's other features are in service of 32x signaling. The two other features are briefly summarized below:

FlexLink for command/address routing: FlexLink is what Rambus is calling the command/address (C/A) wire in their TBI design. The idea behind FlexLink is pretty straightforward: since you're already doing 32x signaling on the data line of the bus, why not also do it on the command/address line, as well, instead of ratcheting down the bus multiplier on the C/A link. So both lines of the link use the same 32x signaling, not because you actually need that much bandwidth on the C/A link but because it simplifies the overall implementation.

FlexLink is an extension of the FlexPhase deskew technology used in Rambus's XDR interface. So FlexLink retains its predecessor's ability to re-align data and C/A signals after they've been transmitted over traces with different lengths and/or impedances.

Fully Differential Memory Architecture: The final piece of the TBI involves doing differential signaling on the data, C/A, and clock/strobe lines. Right now, XDR uses differential signaling on only the data lines, but at the terabyte/sec level they see the need for it on all of the lines.

Note that Intel is also looking to differential signaling for the medium-term future of board-level, chip-to-chip bandwidth in the 15Gbps range. The consensus seems to be that single-ended signaling isn't suitable for higher transfer rates, due to noise problems.

Plans and prototypes

Right now, TBI is still in the "research initiative" phase, much like Intel's Terascale initiative. And like Intel's Terascale, Rambus has built a prototype to test some of the ideas mentioned above. The TBI prototype consists of three 65nm, chips, an SoC stand-in, and two simulated DRAMs. For the latter, Rambus tried to mimic the characteristics of a DRAM that might exist in the 2010-2011 timeframe, and they were able to get a potentially usable signal (it would need cleanup) between the SoC and the DRAMs at a 32x data rate.

Rambus is aiming for 2010 or later with the technologies in TBI.

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