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Machine Descriptions

A machine description has two parts: a file of instruction patterns (`.md' file) and a C header file of macro definitions.


See the next chapter for information on the C header file.

Everything about Instruction Patterns


A define_insn is an RTL expression containing four or five operands:




  2. The RTL template (see section RTL Template) is a vector of incomplete RTL expressions which show what the instruction should look like. It is incomplete because it may contain match_operand, match_operator, and match_dup expressions that stand for operands of the instruction.





  4. The output template: a string that says how to output matching insns as assembler code. `%' in this string specifies where to substitute the value of an operand. See section Output Templates and Operand Substitution.

    When simple substitution isn't general enough, you can specify a piece of C code to compute the output. See section C Statements for Assembler Output.

  5. Optionally, a vector containing the values of attributes for insns matching this pattern. See section Instruction Attributes.

Example of define_insn

Here is an actual example of an instruction pattern, for the 68000/68020.

(define_insn "tstsi"
  [(set (cc0)
        (match_operand:SI 0 "general_operand" "rm"))]
{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
    return \"tstl %0\";
  return \"cmpl #0,%0\"; }")

This is an instruction that sets the condition codes based on the value of a general operand. It has no condition, so any insn whose RTL description has the form shown may be handled according to this pattern. The name `tstsi' means "test a SImode value" and tells the RTL generation pass that, when it is necessary to test such a value, an insn to do so can be constructed using this pattern.

The output control string is a piece of C code which chooses which output template to return based on the kind of operand and the specific type of CPU for which code is being generated.

`"rm"' is an operand constraint. Its meaning is explained below.

RTL Template

The RTL template is used to define which insns match the particular pattern and how to find their operands. For named patterns, the RTL template also says how to construct an insn from specified operands.

Construction involves substituting specified operands into a copy of the template. Matching involves determining the values that serve as the operands in the insn being matched. Both of these activities are controlled by special expression types that direct matching and substitution of the operands.

(match_operand:m n predicate constraint)
This expression is a placeholder for operand number n of the insn. When constructing an insn, operand number n will be substituted at this point. When matching an insn, whatever appears at this position in the insn will be taken as operand number n; but it must satisfy predicate or this instruction pattern will not match at all.

Operand numbers must be chosen consecutively counting from zero in each instruction pattern. There may be only one match_operand expression in the pattern for each operand number. Usually operands are numbered in the order of appearance in match_operand expressions.

predicate is a string that is the name of a C function that accepts two arguments, an expression and a machine mode. During matching, the function will be called with the putative operand as the expression and m as the mode argument (if m is not specified, VOIDmode will be used, which normally causes predicate to accept any mode). If it returns zero, this instruction pattern fails to match. predicate may be an empty string; then it means no test is to be done on the operand, so anything which occurs in this position is valid.

Most of the time, predicate will reject modes other than m---but not always. For example, the predicate address_operand uses m as the mode of memory ref that the address should be valid for. Many predicates accept const_int nodes even though their mode is VOIDmode.

constraint controls reloading and the choice of the best register class to use for a value, as explained later (see section Operand Constraints).

People are often unclear on the difference between the constraint and the predicate. The predicate helps decide whether a given insn matches the pattern. The constraint plays no role in this decision; instead, it controls various decisions in the case of an insn which does match.

On CISC machines, the most common predicate is "general_operand". This function checks that the putative operand is either a constant, a register or a memory reference, and that it is valid for mode m.

For an operand that must be a register, predicate should be "register_operand". Using "general_operand" would be valid, since the reload pass would copy any non-register operands through registers, but this would make GNU CC do extra work, it would prevent invariant operands (such as constant) from being removed from loops, and it would prevent the register allocator from doing the best possible job. On RISC machines, it is usually most efficient to allow predicate to accept only objects that the constraints allow.

For an operand that must be a constant, you must be sure to either use "immediate_operand" for predicate, or make the instruction pattern's extra condition require a constant, or both. You cannot expect the constraints to do this work! If the constraints allow only constants, but the predicate allows something else, the compiler will crash when that case arises.

(match_scratch:m n constraint)
This expression is also a placeholder for operand number n and indicates that operand must be a scratch or reg expression.

When matching patterns, this is equivalent to

(match_operand:m n "scratch_operand" pred)

but, when generating RTL, it produces a (scratch:m) expression.

If the last few expressions in a parallel are clobber expressions whose operands are either a hard register or match_scratch, the combiner can add or delete them when necessary. See section Side Effect Expressions.

(match_dup n)
This expression is also a placeholder for operand number n. It is used when the operand needs to appear more than once in the insn.

In construction, match_dup acts just like match_operand: the operand is substituted into the insn being constructed. But in matching, match_dup behaves differently. It assumes that operand number n has already been determined by a match_operand appearing earlier in the recognition template, and it matches only an identical-looking expression.

(match_operator:m n predicate [operands...])
This pattern is a kind of placeholder for a variable RTL expression code.

When constructing an insn, it stands for an RTL expression whose expression code is taken from that of operand n, and whose operands are constructed from the patterns operands.

When matching an expression, it matches an expression if the function predicate returns nonzero on that expression and the patterns operands match the operands of the expression.

Suppose that the function commutative_operator is defined as follows, to match any expression whose operator is one of the commutative arithmetic operators of RTL and whose mode is mode:

commutative_operator (x, mode)
     rtx x;
     enum machine_mode mode;
  enum rtx_code code = GET_CODE (x);
  if (GET_MODE (x) != mode)
    return 0;
  return (GET_RTX_CLASS (code) == 'c'
          || code == EQ || code == NE);

Then the following pattern will match any RTL expression consisting of a commutative operator applied to two general operands:

(match_operator:SI 3 "commutative_operator"
  [(match_operand:SI 1 "general_operand" "g")
   (match_operand:SI 2 "general_operand" "g")])

Here the vector [operands...] contains two patterns because the expressions to be matched all contain two operands.

When this pattern does match, the two operands of the commutative operator are recorded as operands 1 and 2 of the insn. (This is done by the two instances of match_operand.) Operand 3 of the insn will be the entire commutative expression: use GET_CODE (operands[3]) to see which commutative operator was used.

The machine mode m of match_operator works like that of match_operand: it is passed as the second argument to the predicate function, and that function is solely responsible for deciding whether the expression to be matched "has" that mode.

When constructing an insn, argument 3 of the gen-function will specify the operation (i.e. the expression code) for the expression to be made. It should be an RTL expression, whose expression code is copied into a new expression whose operands are arguments 1 and 2 of the gen-function. The subexpressions of argument 3 are not used; only its expression code matters.

When match_operator is used in a pattern for matching an insn, it usually best if the operand number of the match_operator is higher than that of the actual operands of the insn. This improves register allocation because the register allocator often looks at operands 1 and 2 of insns to see if it can do register tying.

There is no way to specify constraints in match_operator. The operand of the insn which corresponds to the match_operator never has any constraints because it is never reloaded as a whole. However, if parts of its operands are matched by match_operand patterns, those parts may have constraints of their own.

(match_op_dup:m n[operands...])
Like match_dup, except that it applies to operators instead of operands. When constructing an insn, operand number n will be substituted at this point. But in matching, match_op_dup behaves differently. It assumes that operand number n has already been determined by a match_operator appearing earlier in the recognition template, and it matches only an identical-looking expression.

(match_parallel n predicate [subpat...])
This pattern is a placeholder for an insn that consists of a parallel expression with a variable number of elements. This expression should only appear at the top level of an insn pattern.

When constructing an insn, operand number n will be substituted at this point. When matching an insn, it matches if the body of the insn is a parallel expression with at least as many elements as the vector of subpat expressions in the match_parallel, if each subpat matches the corresponding element of the parallel, and the function predicate returns nonzero on the parallel that is the body of the insn. It is the responsibility of the predicate to validate elements of the parallel beyond those listed in the match_parallel.

A typical use of match_parallel is to match load and store multiple expressions, which can contain a variable number of elements in a parallel. For example,

(define_insn ""
  [(match_parallel 0 "load_multiple_operation"
     [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
           (match_operand:SI 2 "memory_operand" "m"))
      (use (reg:SI 179))
      (clobber (reg:SI 179))])]
  "loadm 0,0,%1,%2")

This example comes from `a29k.md'. The function load_multiple_operations is defined in `a29k.c' and checks that subsequent elements in the parallel are the same as the set in the pattern, except that they are referencing subsequent registers and memory locations.

An insn that matches this pattern might look like:

 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
  (use (reg:SI 179))
  (clobber (reg:SI 179))
  (set (reg:SI 21)
       (mem:SI (plus:SI (reg:SI 100)
                        (const_int 4))))
  (set (reg:SI 22)
       (mem:SI (plus:SI (reg:SI 100)
                        (const_int 8))))])

(match_par_dup n [subpat...])
Like match_op_dup, but for match_parallel instead of match_operator.

(address (match_operand:m n "address_operand" ""))
This complex of expressions is a placeholder for an operand number n in a "load address" instruction: an operand which specifies a memory location in the usual way, but for which the actual operand value used is the address of the location, not the contents of the location.

address expressions never appear in RTL code, only in machine descriptions. And they are used only in machine descriptions that do not use the operand constraint feature. When operand constraints are in use, the letter `p' in the constraint serves this purpose.

m is the machine mode of the memory location being addressed, not the machine mode of the address itself. That mode is always the same on a given target machine (it is Pmode, which normally is SImode), so there is no point in mentioning it; thus, no machine mode is written in the address expression. If some day support is added for machines in which addresses of different kinds of objects appear differently or are used differently (such as the PDP-10), different formats would perhaps need different machine modes and these modes might be written in the address expression.

Output Templates and Operand Substitution

The output template is a string which specifies how to output the assembler code for an instruction pattern. Most of the template is a fixed string which is output literally. The character `%' is used to specify where to substitute an operand; it can also be used to identify places where different variants of the assembler require different syntax.

In the simplest case, a `%' followed by a digit n says to output operand n at that point in the string.

`%' followed by a letter and a digit says to output an operand in an alternate fashion. Four letters have standard, built-in meanings described below. The machine description macro PRINT_OPERAND can define additional letters with nonstandard meanings.

`%cdigit' can be used to substitute an operand that is a constant value without the syntax that normally indicates an immediate operand.

`%ndigit' is like `%cdigit' except that the value of the constant is negated before printing.

`%adigit' can be used to substitute an operand as if it were a memory reference, with the actual operand treated as the address. This may be useful when outputting a "load address" instruction, because often the assembler syntax for such an instruction requires you to write the operand as if it were a memory reference.

`%ldigit' is used to substitute a label_ref into a jump instruction.

`%=' outputs a number which is unique to each instruction in the entire compilation. This is useful for making local labels to be referred to more than once in a single template that generates multiple assembler instructions.

`%' followed by a punctuation character specifies a substitution that does not use an operand. Only one case is standard: `%%' outputs a `%' into the assembler code. Other nonstandard cases can be defined in the PRINT_OPERAND macro. You must also define which punctuation characters are valid with the PRINT_OPERAND_PUNCT_VALID_P macro.

The template may generate multiple assembler instructions. Write the text for the instructions, with `\;' between them.

When the RTL contains two operands which are required by constraint to match each other, the output template must refer only to the lower-numbered operand. Matching operands are not always identical, and the rest of the compiler arranges to put the proper RTL expression for printing into the lower-numbered operand.

One use of nonstandard letters or punctuation following `%' is to distinguish between different assembler languages for the same machine; for example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax requires periods in most opcode names, while MIT syntax does not. For example, the opcode `movel' in MIT syntax is `move.l' in Motorola syntax. The same file of patterns is used for both kinds of output syntax, but the character sequence `%.' is used in each place where Motorola syntax wants a period. The PRINT_OPERAND macro for Motorola syntax defines the sequence to output a period; the macro for MIT syntax defines it to do nothing.

As a special case, a template consisting of the single character # instructs the compiler to first split the insn, and then output the resulting instructions separately. This helps eliminate redundancy in the output templates. If you have a define_insn that needs to emit multiple assembler instructions, and there is an matching define_split already defined, then you can simply use # as the output template instead of writing an output template that emits the multiple assembler instructions.

If ASSEMBLER_DIALECT is defined, you can use `{option0|option1|option2}' constructs in the templates. These describe multiple variants of assembler language syntax. See section Output of Assembler Instructions.

C Statements for Assembler Output

Often a single fixed template string cannot produce correct and efficient assembler code for all the cases that are recognized by a single instruction pattern. For example, the opcodes may depend on the kinds of operands; or some unfortunate combinations of operands may require extra machine instructions.

If the output control string starts with a `@', then it is actually a series of templates, each on a separate line. (Blank lines and leading spaces and tabs are ignored.) The templates correspond to the pattern's constraint alternatives (see section Multiple Alternative Constraints). For example, if a target machine has a two-address add instruction `addr' to add into a register and another `addm' to add a register to memory, you might write this pattern:

(define_insn "addsi3"
  [(set (match_operand:SI 0 "general_operand" "=r,m")
        (plus:SI (match_operand:SI 1 "general_operand" "0,0")
                 (match_operand:SI 2 "general_operand" "g,r")))]
   addr %2,%0
   addm %2,%0")

If the output control string starts with a `*', then it is not an output template but rather a piece of C program that should compute a template. It should execute a return statement to return the template-string you want. Most such templates use C string literals, which require doublequote characters to delimit them. To include these doublequote characters in the string, prefix each one with `\'.

The operands may be found in the array operands, whose C data type is rtx [].

It is very common to select different ways of generating assembler code based on whether an immediate operand is within a certain range. Be careful when doing this, because the result of INTVAL is an integer on the host machine. If the host machine has more bits in an int than the target machine has in the mode in which the constant will be used, then some of the bits you get from INTVAL will be superfluous. For proper results, you must carefully disregard the values of those bits.

It is possible to output an assembler instruction and then go on to output or compute more of them, using the subroutine output_asm_insn. This receives two arguments: a template-string and a vector of operands. The vector may be operands, or it may be another array of rtx that you declare locally and initialize yourself.

When an insn pattern has multiple alternatives in its constraints, often the appearance of the assembler code is determined mostly by which alternative was matched. When this is so, the C code can test the variable which_alternative, which is the ordinal number of the alternative that was actually satisfied (0 for the first, 1 for the second alternative, etc.).

For example, suppose there are two opcodes for storing zero, `clrreg' for registers and `clrmem' for memory locations. Here is how a pattern could use which_alternative to choose between them:

(define_insn ""
        (const_int 0))]
  return (which_alternative == 0
          ? \"clrreg %0\" : \"clrmem %0\");

The example above, where the assembler code to generate was solely determined by the alternative, could also have been specified as follows, having the output control string start with a `@':

(define_insn ""
        (const_int 0))]
   clrreg %0
   clrmem %0")

Operand Constraints

Each match_operand in an instruction pattern can specify a constraint for the type of operands allowed. Constraints can say whether an operand may be in a register, and which kinds of register; whether the operand can be a memory reference, and which kinds of address; whether the operand may be an immediate constant, and which possible values it may have. Constraints can also require two operands to match.

Simple Constraints










`d', `a', `f', ...
Other letters can be defined in machine-dependent fashion to stand for particular classes of registers. `d', `a' and `f' are defined on the 68000/68020 to stand for data, address and floating point registers.





An immediate floating operand (expression code const_double) is allowed.

`G', `H'



For example, on the 68000 in a fullword instruction it is possible to use an immediate operand; but if the immediate value is between -128 and 127, better code results from loading the value into a register and using the register. This is because the load into the register can be done with a `moveq' instruction. We arrange for this to happen by defining the letter `K' to mean "any integer outside the range -128 to 127", and then specifying `Ks' in the operand constraints.





addl #35,r12



An operand that is a valid memory address is allowed. This is for "load address" and "push address" instructions.


`Q', `R', `S', ... `U'
Letters in the range `Q' through `U' may be defined in a machine-dependent fashion to stand for arbitrary operand types. The machine description macro EXTRA_CONSTRAINT is passed the operand as its first argument and the constraint letter as its second operand.

A typical use for this would be to distinguish certain types of memory references that affect other insn operands.

Do not define these constraint letters to accept register references (reg); the reload pass does not expect this and would not handle it properly.


Contrast, therefore, the two instruction patterns that follow:

(define_insn ""
        (plus:SI (match_dup 0)


(define_insn ""
        (plus:SI (match_operand:SI 1 "general_operand" "0")


(insn n prev next
  (set (reg:SI 3)
       (plus:SI (reg:SI 6) (reg:SI 109)))

the first pattern would not apply at all, because this insn does not contain two identical subexpressions in the right place. The pattern would say, "That does not look like an add instruction; try other patterns." The second pattern would say, "Yes, that's an add instruction, but there is something wrong with it." It would direct the reload pass of the compiler to generate additional insns to make the constraint true. The results might look like this:

(insn n2 prev n
  (set (reg:SI 3) (reg:SI 6))

(insn n n2 next
  (set (reg:SI 3)
       (plus:SI (reg:SI 3) (reg:SI 109)))

It is up to you to make sure that each operand, in each pattern, has constraints that can handle any RTL expression that could be present for that operand. (When multiple alternatives are in use, each pattern must, for each possible combination of operand expressions, have at least one alternative which can handle that combination of operands.) The constraints don't need to allow any possible operand--when this is the case, they do not constrain--but they must at least point the way to reloading any possible operand so that it will fit.


Multiple Alternative Constraints



(define_insn "iorsi3"

The first alternative has `m' (memory) for operand 0, `0' for operand 1 (meaning it must match operand 0), and `dKs' for operand 2. The second alternative has `d' (data register) for operand 0, `0' for operand 1, and `dmKs' for operand 2. The `=' and `%' in the constraints apply to all the alternatives; their meaning is explained in the next section (see section Register Class Preferences).





Register Class Preferences



Constraint Modifier Characters

Here are constraint modifier characters.




Means (in a particular alternative) that this operand is written before the instruction is finished using the input operands. Therefore, this operand may not lie in a register that is used as an input operand or as part of any memory address.




(define_insn "addhi3"




(define_insn "extendhisi2"

Constraints for Particular Machines

Whenever possible, you should use the general-purpose constraint letters in asm arguments, since they will convey meaning more readily to people reading your code. Failing that, use the constraint letters that usually have very similar meanings across architectures. The most commonly used constraints are `m' and `r' (for memory and general-purpose registers respectively; see section Simple Constraints), and `I', usually the letter indicating the most common immediate-constant format.

For each machine architecture, the `config/machine.h' file defines additional constraints. These constraints are used by the compiler itself for instruction generation, as well as for asm statements; therefore, some of the constraints are not particularly interesting for asm. The constraints are defined through these macros:

Register class constraints (usually lower case).

Immediate constant constraints, for non-floating point constants of word size or smaller precision (usually upper case).

Immediate constant constraints, for all floating point constants and for constants of greater than word size precision (usually upper case).

Special cases of registers or memory. This macro is not required, and is only defined for some machines.

Inspecting these macro definitions in the compiler source for your machine is the best way to be certain you have the right constraints. However, here is a summary of the machine-dependent constraints available on some particular machines.

ARM family---`arm.h'
Floating-point register

One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 or 10.0

Floating-point constant that would satisfy the constraint `F' if it were negated

Integer that is valid as an immediate operand in a data processing instruction. That is, an integer in the range 0 to 255 rotated by a multiple of 2

Integer in the range -4095 to 4095

Integer that satisfies constraint `I' when inverted (ones complement)

Integer that satisfies constraint `I' when negated (twos complement)

Integer in the range 0 to 32

A memory reference where the exact address is in a single register (``m'' is preferable for asm statements)

An item in the constant pool

A symbol in the text segment of the current file

  • AMD 29000 family---`a29k.h'
    Local register 0

    Byte Pointer (`BP') register

    `Q' register

    Special purpose register

    First accumulator register

    Other accumulator register

    Floating point register

    Constant greater than 0, less than 0x100

    Constant greater than 0, less than 0x10000

    Constant whose high 24 bits are on (1)

    16 bit constant whose high 8 bits are on (1)

    32 bit constant whose high 16 bits are on (1)

    32 bit negative constant that fits in 8 bits

    The constant 0x80000000 or, on the 29050, any 32 bit constant whose low 16 bits are 0.

    16 bit negative constant that fits in 8 bits

    A floating point constant (in asm statements, use the machine independent `E' or `F' instead)

  • IBM RS6000---`rs6000.h'
    Address base register

    Floating point register

    `MQ', `CTR', or `LINK' register

    `MQ' register

    `CTR' register

    `LINK' register

    `CR' register (condition register) number 0

    `CR' register (condition register)

    Signed 16 bit constant

    Constant whose low 16 bits are 0

    Constant whose high 16 bits are 0

    Constant suitable as a mask operand

    Constant larger than 31

    Exact power of 2


    Constant whose negation is a signed 16 bit constant

    Floating point constant that can be loaded into a register with one instruction per word

    Memory operand that is an offset from a register (`m' is preferable for asm statements)

  • Intel 386---`i386.h'
    `a', b, c, or d register

    `a', or d register (for 64-bit ints)

    Floating point register

    First (top of stack) floating point register

    Second floating point register

    `a' register

    `b' register

    `c' register

    `d' register

    `di' register

    `si' register

    Constant in range 0 to 31 (for 32 bit shifts)

    Constant in range 0 to 63 (for 64 bit shifts)




    Standard 80387 floating point constant

  • Intel 960---`i960.h'
    Floating point register (fp0 to fp3)

    Local register (r0 to r15)

    Global register (g0 to g15)

    Any local or global register

    Integers from 0 to 31


    Integers from -31 to 0

    Floating point 0

    Floating point 1

  • MIPS---`mips.h'
    General-purpose integer register

    Floating-point register (if available)

    `Hi' register

    `Lo' register

    `Hi' or `Lo' register

    General-purpose integer register

    Floating-point status register

    Signed 16 bit constant (for arithmetic instructions)


    Zero-extended 16-bit constant (for logic instructions)

    Constant with low 16 bits zero (can be loaded with lui)

    32 bit constant which requires two instructions to load (a constant which is not `I', `K', or `L')

    Negative 16 bit constant

    Exact power of two

    Positive 16 bit constant

    Floating point zero

    Memory reference that can be loaded with more than one instruction (`m' is preferable for asm statements)

    Memory reference that can be loaded with one instruction (`m' is preferable for asm statements)

    Memory reference in external OSF/rose PIC format (`m' is preferable for asm statements)

  • Motorola 680x0---`m68k.h'
    Address register

    Data register

    68881 floating-point register, if available

    Sun FPA (floating-point) register, if available

    First 16 Sun FPA registers, if available

    Integer in the range 1 to 8

    16 bit signed number

    Signed number whose magnitude is greater than 0x80

    Integer in the range -8 to -1

    Floating point constant that is not a 68881 constant

    Floating point constant that can be used by Sun FPA

  • SPARC---`sparc.h'
    Floating-point register

    Signed 13 bit constant


    32 bit constant with the low 12 bits clear (a constant that can be loaded with the sethi instruction)

    Floating-point zero

    Signed 13 bit constant, sign-extended to 32 or 64 bits

    Memory reference that can be loaded with one instruction (`m' is more appropriate for asm statements)

    Constant, or memory address

    Memory address aligned to an 8-byte boundary

    Even register
  • Not Using Constraints

    Some machines are so clean that operand constraints are not required. For example, on the Vax, an operand valid in one context is valid in any other context. On such a machine, every operand constraint would be `g', excepting only operands of "load address" instructions which are written as if they referred to a memory location's contents but actual refer to its address. They would have constraint `p'.

    For such machines, instead of writing `g' and `p' for all the constraints, you can choose to write a description with empty constraints. Then you write `""' for the constraint in every match_operand. Address operands are identified by writing an address expression around the match_operand, not by their constraints.

    When the machine description has just empty constraints, certain parts of compilation are skipped, making the compiler faster. However, few machines actually do not need constraints; all machine descriptions now in existence use constraints.

    Standard Pattern Names For Generation

    Here is a table of the instruction names that are meaningful in the RTL generation pass of the compiler. Giving one of these names to an instruction pattern tells the RTL generation pass that it can use the pattern in to accomplish a certain task.

    Here m stands for a two-letter machine mode name, in lower case. This instruction pattern moves data with that machine mode from operand 1 to operand 0. For example, `movsi' moves full-word data.

    If operand 0 is a subreg with mode m of a register whose own mode is wider than m, the effect of this instruction is to store the specified value in the part of the register that corresponds to mode m. The effect on the rest of the register is undefined.

    This class of patterns is special in several ways. First of all, each of these names must be defined, because there is no other way to copy a datum from one place to another.

    Second, these patterns are not used solely in the RTL generation pass. Even the reload pass can generate move insns to copy values from stack slots into temporary registers. When it does so, one of the operands is a hard register and the other is an operand that can need to be reloaded into a register.

    Therefore, when given such a pair of operands, the pattern must generate RTL which needs no reloading and needs no temporary registers--no registers other than the operands. For example, if you support the pattern with a define_expand, then in such a case the define_expand mustn't call force_reg or any other such function which might generate new pseudo registers.

    This requirement exists even for subword modes on a RISC machine where fetching those modes from memory normally requires several insns and some temporary registers. Look in `spur.md' to see how the requirement can be satisfied.

    During reload a memory reference with an invalid address may be passed as an operand. Such an address will be replaced with a valid address later in the reload pass. In this case, nothing may be done with the address except to use it as it stands. If it is copied, it will not be replaced with a valid address. No attempt should be made to make such an address into a valid address and no routine (such as change_address) that will do so may be called. Note that general_operand will fail when applied to such an address.

    The global variable reload_in_progress (which must be explicitly declared if required) can be used to determine whether such special handling is required.

    The variety of operands that have reloads depends on the rest of the machine description, but typically on a RISC machine these can only be pseudo registers that did not get hard registers, while on other machines explicit memory references will get optional reloads.

    If a scratch register is required to move an object to or from memory, it can be allocated using gen_reg_rtx prior to reload. But this is impossible during and after reload. If there are cases needing scratch registers after reload, you must define SECONDARY_INPUT_RELOAD_CLASS and perhaps also SECONDARY_OUTPUT_RELOAD_CLASS to detect them, and provide patterns `reload_inm' or `reload_outm' to handle them. See section Register Classes.

    The constraints on a `movem' must permit moving any hard register to any other hard register provided that HARD_REGNO_MODE_OK permits mode m in both registers and REGISTER_MOVE_COST applied to their classes returns a value of 2.

    It is obligatory to support floating point `movem' instructions into and out of any registers that can hold fixed point values, because unions and structures (which have modes SImode or DImode) can be in those registers and they may have floating point members.

    There may also be a need to support fixed point `movem' instructions in and out of floating point registers. Unfortunately, I have forgotten why this was so, and I don't know whether it is still true. If HARD_REGNO_MODE_OK rejects fixed point values in floating point registers, then the constraints of the fixed point `movem' instructions must be designed to avoid ever trying to reload into a floating point register.

    Like `movm', but used when a scratch register is required to move between operand 0 and operand 1. Operand 2 describes the scratch register. See the discussion of the SECONDARY_RELOAD_CLASS macro in see section Register Classes.

    Like `movm' except that if operand 0 is a subreg with mode m of a register whose natural mode is wider, the `movstrictm' instruction is guaranteed not to alter any of the register except the part which belongs to mode m.

    Load several consecutive memory locations into consecutive registers. Operand 0 is the first of the consecutive registers, operand 1 is the first memory location, and operand 2 is a constant: the number of consecutive registers.

    Define this only if the target machine really has such an instruction; do not define this if the most efficient way of loading consecutive registers from memory is to do them one at a time.

    On some machines, there are restrictions as to which consecutive registers can be stored into memory, such as particular starting or ending register numbers or only a range of valid counts. For those machines, use a define_expand (see section Defining RTL Sequences for Code Generation) and make the pattern fail if the restrictions are not met.

    Write the generated insn as a parallel with elements being a set of one register from the appropriate memory location (you may also need use or clobber elements). Use a match_parallel (see section RTL Template) to recognize the insn. See `a29k.md' and `rs6000.md' for examples of the use of this insn pattern.

    Similar to `load_multiple', but store several consecutive registers into consecutive memory locations. Operand 0 is the first of the consecutive memory locations, operand 1 is the first register, and operand 2 is a constant: the number of consecutive registers.

    Add operand 2 and operand 1, storing the result in operand 0. All operands must have mode m. This can be used even on two-address machines, by means of constraints requiring operands 1 and 0 to be the same location.

    `subm3', `mulm3'
    `divm3', `udivm3', `modm3', `umodm3'
    `sminm3', `smaxm3', `uminm3', `umaxm3'
    `andm3', `iorm3', `xorm3'
    Similar, for other arithmetic operations.

    Multiply operands 1 and 2, which have mode HImode, and store a SImode product in operand 0.

    `mulqihi3', `mulsidi3'
    Similar widening-multiplication instructions of other widths.

    `umulqihi3', `umulhisi3', `umulsidi3'
    Similar widening-multiplication instructions that do unsigned multiplication.

    Signed division that produces both a quotient and a remainder. Operand 1 is divided by operand 2 to produce a quotient stored in operand 0 and a remainder stored in operand 3.

    For machines with an instruction that produces both a quotient and a remainder, provide a pattern for `divmodm4' but do not provide patterns for `divm3' and `modm3'. This allows optimization in the relatively common case when both the quotient and remainder are computed.

    If an instruction that just produces a quotient or just a remainder exists and is more efficient than the instruction that produces both, write the output routine of `divmodm4' to call find_reg_note and look for a REG_UNUSED note on the quotient or remainder and generate the appropriate instruction.

    Similar, but does unsigned division.

    Arithmetic-shift operand 1 left by a number of bits specified by operand 2, and store the result in operand 0. Here m is the mode of operand 0 and operand 1; operand 2's mode is specified by the instruction pattern, and the compiler will convert the operand to that mode before generating the instruction.

    `ashrm3', `lshrm3', `rotlm3', `rotrm3'
    Other shift and rotate instructions, analogous to the ashlm3 instructions.

    Negate operand 1 and store the result in operand 0.

    Store the absolute value of operand 1 into operand 0.

    Store the square root of operand 1 into operand 0.

    The sqrt built-in function of C always uses the mode which corresponds to the C data type double.

    Store into operand 0 one plus the index of the least significant 1-bit of operand 1. If operand 1 is zero, store zero. m is the mode of operand 0; operand 1's mode is specified by the instruction pattern, and the compiler will convert the operand to that mode before generating the instruction.

    The ffs built-in function of C always uses the mode which corresponds to the C data type int.

    Store the bitwise-complement of operand 1 into operand 0.

    Compare operand 0 and operand 1, and set the condition codes. The RTL pattern should look like this:

    (set (cc0) (compare (match_operand:m 0 ...)
                        (match_operand:m 1 ...)))

    Compare operand 0 against zero, and set the condition codes. The RTL pattern should look like this:

    (set (cc0) (match_operand:m 0 ...))

    `tstm' patterns should not be defined for machines that do not use (cc0). Doing so would confuse the optimizer since it would no longer be clear which set operations were comparisons. The `cmpm' patterns should be used instead.

    Block move instruction. The addresses of the destination and source strings are the first two operands, and both are in mode Pmode. The number of bytes to move is the third operand, in mode m.

    The fourth operand is the known shared alignment of the source and destination, in the form of a const_int rtx. Thus, if the compiler knows that both source and destination are word-aligned, it may provide the value 4 for this operand.

    These patterns need not give special consideration to the possibility that the source and destination strings might overlap.

    Block compare instruction, with five operands. Operand 0 is the output; it has mode m. The remaining four operands are like the operands of `movstrm'. The two memory blocks specified are compared byte by byte in lexicographic order. The effect of the instruction is to store a value in operand 0 whose sign indicates the result of the comparison.

    Compute the length of a string, with three operands. Operand 0 is the result (of mode m), operand 1 is a mem referring to the first character of the string, operand 2 is the character to search for (normally zero), and operand 3 is a constant describing the known alignment of the beginning of the string.

    Convert signed integer operand 1 (valid for fixed point mode m) to floating point mode n and store in operand 0 (which has mode n).


    Convert operand 1 (valid for floating point mode m) to fixed point mode n as a signed number and store in operand 0 (which has mode n). This instruction's result is defined only when the value of operand 1 is an integer.

    Convert operand 1 (valid for floating point mode m) to fixed point mode n as an unsigned number and store in operand 0 (which has mode n). This instruction's result is defined only when the value of operand 1 is an integer.

    Convert operand 1 (valid for floating point mode m) to an integer value, still represented in floating point mode m, and store it in operand 0 (valid for floating point mode m).

    Like `fixmn2' but works for any floating point value of mode m by converting the value to an integer.

    Like `fixunsmn2' but works for any floating point value of mode m by converting the value to an integer.

    Truncate operand 1 (valid for mode m) to mode n and store in operand 0 (which has mode n). Both modes must be fixed point or both floating point.



    Extract a bit field from operand 1 (a register or memory operand), where operand 2 specifies the width in bits and operand 3 the starting bit, and store it in operand 0. Operand 0 must have mode word_mode. Operand 1 may have mode byte_mode or word_mode; often word_mode is allowed only for registers. Operands 2 and 3 must be valid for word_mode.

    The RTL generation pass generates this instruction only with constants for operands 2 and 3.

    The bit-field value is sign-extended to a full word integer before it is stored in operand 0.

    Like `extv' except that the bit-field value is zero-extended.

    Store operand 3 (which must be valid for word_mode) into a bit field in operand 0, where operand 1 specifies the width in bits and operand 2 the starting bit. Operand 0 may have mode byte_mode or word_mode; often word_mode is allowed only for registers. Operands 1 and 2 must be valid for word_mode.

    The RTL generation pass generates this instruction only with constants for operands 1 and 2.

    Store zero or nonzero in the operand according to the condition codes. Value stored is nonzero iff the condition cond is true. cond is the name of a comparison operation expression code, such as eq, lt or leu.

    You specify the mode that the operand must have when you write the match_operand expression. The compiler automatically sees which mode you have used and supplies an operand of that mode.

    The value stored for a true condition must have 1 as its low bit, or else must be negative. Otherwise the instruction is not suitable and you should omit it from the machine description. You describe to the compiler exactly which value is stored by defining the macro STORE_FLAG_VALUE (see section Miscellaneous Parameters). If a description cannot be found that can be used for all the `scond' patterns, you should omit those operations from the machine description.

    These operations may fail, but should do so only in relatively uncommon cases; if they would fail for common cases involving integer comparisons, it is best to omit these patterns.

    If these operations are omitted, the compiler will usually generate code that copies the constant one to the target and branches around an assignment of zero to the target. If this code is more efficient than the potential instructions used for the `scond' pattern followed by those required to convert the result into a 1 or a zero in SImode, you should omit the `scond' operations from the machine description.

    Conditional branch instruction. Operand 0 is a label_ref that refers to the label to jump to. Jump if the condition codes meet condition cond.

    Some machines do not follow the model assumed here where a comparison instruction is followed by a conditional branch instruction. In that case, the `cmpm' (and `tstm') patterns should simply store the operands away and generate all the required insns in a define_expand (see section Defining RTL Sequences for Code Generation) for the conditional branch operations. All calls to expand `bcond' patterns are immediately preceded by calls to expand either a `cmpm' pattern or a `tstm' pattern.

    Machines that use a pseudo register for the condition code value, or where the mode used for the comparison depends on the condition being tested, should also use the above mechanism. See section Defining Jump Instruction Patterns

    The above discussion also applies to `scond' patterns.

    Subroutine call instruction returning no value. Operand 0 is the function to call; operand 1 is the number of bytes of arguments pushed (in mode SImode, except it is normally a const_int); operand 2 is the number of registers used as operands.

    On most machines, operand 2 is not actually stored into the RTL pattern. It is supplied for the sake of some RISC machines which need to put this information into the assembler code; they can put it in the RTL instead of operand 1.

    Operand 0 should be a mem RTX whose address is the address of the function. Note, however, that this address can be a symbol_ref expression even if it would not be a legitimate memory address on the target machine. If it is also not a valid argument for a call instruction, the pattern for this operation should be a define_expand (see section Defining RTL Sequences for Code Generation) that places the address into a register and uses that register in the call instruction.

    Subroutine call instruction returning a value. Operand 0 is the hard register in which the value is returned. There are three more operands, the same as the three operands of the `call' instruction (but with numbers increased by one).

    Subroutines that return BLKmode objects use the `call' insn.

    `call_pop', `call_value_pop'
    Similar to `call' and `call_value', except used if defined and if RETURN_POPS_ARGS is non-zero. They should emit a parallel that contains both the function call and a set to indicate the adjustment made to the frame pointer.

    For machines where RETURN_POPS_ARGS can be non-zero, the use of these patterns increases the number of functions for which the frame pointer can be eliminated, if desired.

    Subroutine call instruction returning a value of any type. Operand 0 is the function to call; operand 1 is a memory location where the result of calling the function is to be stored; operand 2 is a parallel expression where each element is a set expression that indicates the saving of a function return value into the result block.

    This instruction pattern should be defined to support __builtin_apply on machines where special instructions are needed to call a subroutine with arbitrary arguments or to save the value returned. This instruction pattern is required on machines that have multiple registers that can hold a return value (i.e. FUNCTION_VALUE_REGNO_P is true for more than one register).

    Subroutine return instruction. This instruction pattern name should be defined only if a single instruction can do all the work of returning from a function.

    Like the `movm' patterns, this pattern is also used after the RTL generation phase. In this case it is to support machines where multiple instructions are usually needed to return from a function, but some class of functions only requires one instruction to implement a return. Normally, the applicable functions are those which do not need to save any registers or allocate stack space.

    For such machines, the condition specified in this pattern should only be true when reload_completed is non-zero and the function's epilogue would only be a single instruction. For machines with register windows, the routine leaf_function_p may be used to determine if a register window push is required.

    Machines that have conditional return instructions should define patterns such as

    (define_insn ""
      [(set (pc)
            (if_then_else (match_operator
                             0 "comparison_operator"
                             [(cc0) (const_int 0)])

    where condition would normally be the same condition specified on the named `return' pattern.

    Untyped subroutine return instruction. This instruction pattern should be defined to support __builtin_return on machines where special instructions are needed to return a value of any type.

    Operand 0 is a memory location where the result of calling a function with __builtin_apply is stored; operand 1 is a parallel expression where each element is a set expression that indicates the restoring of a function return value from the result block.

    No-op instruction. This instruction pattern name should always be defined to output a no-op in assembler code. (const_int 0) will do as an RTL pattern.

    An instruction to jump to an address which is operand zero. This pattern name is mandatory on all machines.

    Instruction to jump through a dispatch table, including bounds checking. This instruction takes five operands:

      The index to dispatch on, which has mode SImode.

      The lower bound for indices in the table, an integer constant.

      The total range of indices in the table--the largest index minus the smallest one (both inclusive).

      A label that precedes the table itself.

      A label to jump to if the index has a value outside the bounds. (If the machine-description macro CASE_DROPS_THROUGH is defined, then an out-of-bounds index drops through to the code following the jump table instead of jumping to this label. In that case, this label is not actually used by the `casesi' instruction, but it is always provided as an operand.)

    The table is a addr_vec or addr_diff_vec inside of a jump_insn. The number of elements in the table is one plus the difference between the upper bound and the lower bound.

    Instruction to jump to a variable address. This is a low-level capability which can be used to implement a dispatch table when there is no `casesi' pattern.

    This pattern requires two operands: the address or offset, and a label which should immediately precede the jump table. If the macro CASE_VECTOR_PC_RELATIVE is defined then the first operand is an offset which counts from the address of the table; otherwise, it is an absolute address to jump to. In either case, the first operand has mode Pmode.

    The `tablejump' insn is always the last insn before the jump table it uses. Its assembler code normally has no need to use the second operand, but you should incorporate it in the RTL pattern so that the jump optimizer will not delete the table as unreachable code.

    Most machines save and restore the stack pointer by copying it to or from an object of mode Pmode. Do not define these patterns on such machines.

    Some machines require special handling for stack pointer saves and restores. On those machines, define the patterns corresponding to the non-standard cases by using a define_expand (see section Defining RTL Sequences for Code Generation) that produces the required insns. The three types of saves and restores are:

      `save_stack_block' saves the stack pointer at the start of a block that allocates a variable-sized object, and `restore_stack_block' restores the stack pointer when the block is exited.

      `save_stack_function' and `restore_stack_function' do a similar job for the outermost block of a function and are used when the function allocates variable-sized objects or calls alloca. Only the epilogue uses the restored stack pointer, allowing a simpler save or restore sequence on some machines.

      `save_stack_nonlocal' is used in functions that contain labels branched to by nested functions. It saves the stack pointer in such a way that the inner function can use `restore_stack_nonlocal' to restore the stack pointer. The compiler generates code to restore the frame and argument pointer registers, but some machines require saving and restoring additional data such as register window information or stack backchains. Place insns in these patterns to save and restore any such required data.

    When saving the stack pointer, operand 0 is the save area and operand 1 is the stack pointer. The mode used to allocate the save area is the mode of operand 0. You must specify an integral mode, or VOIDmode if no save area is needed for a particular type of save (either because no save is needed or because a machine-specific save area can be used). Operand 0 is the stack pointer and operand 1 is the save area for restore operations. If `save_stack_block' is defined, operand 0 must not be VOIDmode since these saves can be arbitrarily nested.

    A save area is a mem that is at a constant offset from virtual_stack_vars_rtx when the stack pointer is saved for use by nonlocal gotos and a reg in the other two cases.

    Subtract (or add if STACK_GROWS_DOWNWARD is undefined) operand 0 from the stack pointer to create space for dynamically allocated data.

    Do not define this pattern if all that must be done is the subtraction. Some machines require other operations such as stack probes or maintaining the back chain. Define this pattern to emit those operations in addition to updating the stack pointer.

    When the Order of Patterns Matters

    Sometimes an insn can match more than one instruction pattern. Then the pattern that appears first in the machine description is the one used. Therefore, more specific patterns (patterns that will match fewer things) and faster instructions (those that will produce better code when they do match) should usually go first in the description.

    In some cases the effect of ordering the patterns can be used to hide a pattern when it is not valid. For example, the 68000 has an instruction for converting a fullword to floating point and another for converting a byte to floating point. An instruction converting an integer to floating point could match either one. We put the pattern to convert the fullword first to make sure that one will be used rather than the other. (Otherwise a large integer might be generated as a single-byte immediate quantity, which would not work.) Instead of using this pattern ordering it would be possible to make the pattern for convert-a-byte smart enough to deal properly with any constant value.

    Interdependence of Patterns


    (set (pc)
         (if_then_else (cond (cc0) (const_int 0))
                       (label_ref (match_operand 0 "" ""))


    (set (pc)
         (if_then_else (cond (cc0) (const_int 0))



    (define_insn ""
      [(set (pc)
            (if_then_else (match_operator 0 "comparison_operator"
                                          [(cc0) (const_int 0)])

    In some cases machines support instructions identical except for the machine mode of one or more operands. For example, there may be "sign-extend halfword" and "sign-extend byte" instructions whose patterns are

    (set (match_operand:SI 0 ...)
         (extend:SI (match_operand:HI 1 ...)))
    (set (match_operand:SI 0 ...)
         (extend:SI (match_operand:QI 1 ...)))



    If a constraint in a pattern allows a constant, the reload pass may replace a register with a constant permitted by the constraint in some cases. Similarly for memory references. You must ensure that the predicate permits all objects allowed by the constraints to prevent the compiler from crashing.


    Defining Jump Instruction Patterns

    For most machines, GNU CC assumes that the machine has a condition code. A comparison insn sets the condition code, recording the results of both signed and unsigned comparison of the given operands. A separate branch insn tests the condition code and branches or not according its value. The branch insns come in distinct signed and unsigned flavors. Many common machines, such as the Vax, the 68000 and the 32000, work this way.


    The reason you can do this is that GNU CC always generates a pair of consecutive RTL insns, possibly separated by note insns, one to set the condition code and one to test it, and keeps the pair inviolate until the end.


    Some machines have compare-and-branch instructions and no condition code. A similar technique works for them. When it is time to "output" a compare instruction, record its operands in two static variables. When outputting the branch-on-condition-code instruction that follows, actually output a compare-and-branch instruction that uses the remembered operands.




    On some machines, the type of branch instruction generated may depend on the way the condition code was produced; for example, on the 68k and Sparc, setting the condition code directly from an add or subtract instruction does not clear the overflow bit the way that a test instruction does, so a different branch instruction must be used for some conditional branches. For machines that use (cc0), the set and use of the condition code must be adjacent (separated only by note insns) allowing flags in cc_status to be used. (See section Condition Code Status.) Also, the comparison and branch insns can be located from each other by using the functions prev_cc0_setter and next_cc0_user.


    Registers used to store the condition code value should have a mode that is in class MODE_CC. Normally, it will be CCmode. If additional modes are required (as for the add example mentioned above in the Sparc), define the macro EXTRA_CC_MODES to list the additional modes required (see section Condition Code Status). Also define EXTRA_CC_NAMES to list the names of those modes and SELECT_CC_MODE to choose a mode given an operand of a compare.



    (define_insn ""
      [(set (reg:CC_NOOV 0)
                       (match_operand:SI 1 "arith_operand" "rI"))
              (const_int 0)))]

    The SELECT_CC_MODE macro on the Sparc returns CC_NOOVmode for comparisons whose argument is a plus.

    Canonicalization of Instructions

    There are often cases where multiple RTL expressions could represent an operation performed by a single machine instruction. This situation is most commonly encountered with logical, branch, and multiply-accumulate instructions. In such cases, the compiler attempts to convert these multiple RTL expressions into a single canonical form to reduce the number of insn patterns required.

    In addition to algebraic simplifications, following canonicalizations are performed:

    Machine-Specific Peephole Optimizers

    In addition to instruction patterns the `md' file may contain definitions of machine-specific peephole optimizations.

    The combiner does not notice certain peephole optimizations when the data flow in the program does not suggest that it should try them. For example, sometimes two consecutive insns related in purpose can be combined even though the second one does not appear to use a register computed in the first one. A machine-specific peephole optimizer can detect such opportunities.

    A definition looks like this:

      "optional insn-attributes")














    Here is an example, taken from the 68000 machine description:

            (match_operand:DF 1 "register_operand" "ad"))]
      rtx xoperands[2];
      xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
    #ifdef MOTOROLA
      output_asm_insn (\"move.l %1,(sp)\", xoperands);
      output_asm_insn (\"move.l %1,-(sp)\", operands);
      return \"fmove.d (sp)+,%0\";
      output_asm_insn (\"movel %1,sp@\", xoperands);
      output_asm_insn (\"movel %1,sp@-\", operands);
      return \"fmoved sp@+,%0\";

    The effect of this optimization is to change

    jbsr _foobar
    addql #4,sp
    movel d1,sp@-
    movel d0,sp@-
    fmoved sp@+,fp0


    jbsr _foobar
    movel d1,sp@
    movel d0,sp@-
    fmoved sp@+,fp0


    (define_insn "divmodsi4"
            (div:SI (match_operand:SI 1 "general_operand" "0")
                    (match_operand:SI 2 "general_operand" "dmsK")))


              (div:SI (match_operand:SI 1 "general_operand" "0")
                      (match_operand:SI 2 "general_operand" "dmsK")))

    Defining RTL Sequences for Code Generation



    A define_expand RTX has four operands:










    (define_expand "ashlsi3"
      [(set (match_operand:SI 0 "register_operand" "")
              (match_operand:SI 1 "register_operand" "")
              (match_operand:SI 2 "nonmemory_operand" "")))]

      if (GET_CODE (operands[2]) != CONST_INT



    (define_expand "zero_extendhisi2"
      [(set (match_operand:SI 0 "general_operand" "")
            (const_int 0))
       (set (strict_low_part
                (match_dup 0)
            (match_operand:HI 1 "general_operand" ""))]



    (define_expand "zero_extendhisi2"
      [(set (match_operand:SI 0 "register_operand" "")
            (and:SI (subreg:SI
                      (match_operand:HI 1 "register_operand" "")
                    (match_dup 2)))]
         = force_reg (SImode, gen_rtx (CONST_INT,
                                       VOIDmode, 65535)); ")


    Defining How to Split Instructions

    There are two cases where you should specify how to split a pattern into multiple insns. On machines that have instructions requiring delay slots (see section Delay Slot Scheduling) or that have instructions whose output is not available for multiple cycles (see section Specifying Function Units), the compiler phases that optimize these cases need to be able to move insns into one-instruction delay slots. However, some insns may generate more than one machine instruction. These insns cannot be placed into a delay slot.

    Often you can rewrite the single insn as a list of individual insns, each corresponding to one machine instruction. The disadvantage of doing so is that it will cause the compilation to be slower and require more space. If the resulting insns are too complex, it may also suppress some optimizations. The compiler splits the insn if there is a reason to believe that it might improve instruction or delay slot scheduling.

    The insn combiner phase also splits putative insns. If three insns are merged into one insn with a complex expression that cannot be matched by some define_insn pattern, the combiner phase attempts to split the complex pattern into two insns that are recognized. Usually it can break the complex pattern into two patterns by splitting out some subexpression. However, in some other cases, such as performing an addition of a large constant in two insns on a RISC machine, the way to split the addition into two insns is machine-dependent.

    The define_split definition tells the compiler how to split a complex insn into several simpler insns. It looks like this:

      "preparation statements")

    insn-pattern is a pattern that needs to be split and condition is the final condition to be tested, as in a define_insn. When an insn matching insn-pattern and satisfying condition is found, it is replaced in the insn list with the insns given by new-insn-pattern-1, new-insn-pattern-2, etc.

    The preparation statements are similar to those statements that are specified for define_expand (see section Defining RTL Sequences for Code Generation) and are executed before the new RTL is generated to prepare for the generated code or emit some insns whose pattern is not fixed. Unlike those in define_expand, however, these statements must not generate any new pseudo-registers. Once reload has completed, they also must not allocate any space in the stack frame.

    Patterns are matched against insn-pattern in two different circumstances. If an insn needs to be split for delay slot scheduling or insn scheduling, the insn is already known to be valid, which means that it must have been matched by some define_insn and, if reload_completed is non-zero, is known to satisfy the constraints of that define_insn. In that case, the new insn patterns must also be insns that are matched by some define_insn and, if reload_completed is non-zero, must also satisfy the constraints of those definitions.

    As an example of this usage of define_split, consider the following example from `a29k.md', which splits a sign_extend from HImode to SImode into a pair of shift insns:

      [(set (match_operand:SI 0 "gen_reg_operand" "")
            (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
      [(set (match_dup 0)
            (ashift:SI (match_dup 1)
                       (const_int 16)))
       (set (match_dup 0)
            (ashiftrt:SI (match_dup 0)
                         (const_int 16)))]
    { operands[1] = gen_lowpart (SImode, operands[1]); }")

    When the combiner phase tries to split an insn pattern, it is always the case that the pattern is not matched by any define_insn. The combiner pass first tries to split a single set expression and then the same set expression inside a parallel, but followed by a clobber of a pseudo-reg to use as a scratch register. In these cases, the combiner expects exactly two new insn patterns to be generated. It will verify that these patterns match some define_insn definitions, so you need not do this test in the define_split (of course, there is no point in writing a define_split that will never produce insns that match).

    Here is an example of this use of define_split, taken from `rs6000.md':

      [(set (match_operand:SI 0 "gen_reg_operand" "")
            (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
                     (match_operand:SI 2 "non_add_cint_operand" "")))]
      [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
       (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
      int low = INTVAL (operands[2]) & 0xffff;
      int high = (unsigned) INTVAL (operands[2]) >> 16;
      if (low & 0x8000)
        high++, low |= 0xffff0000;
      operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
      operands[4] = gen_rtx (CONST_INT, VOIDmode, low);

    Here the predicate non_add_cint_operand matches any const_int that is not a valid operand of a single add insn. The add with the smaller displacement is written so that it can be substituted into the address of a subsequent operation.

    An example that uses a scratch register, from the same file, generates an equality comparison of a register and a large constant:

      [(set (match_operand:CC 0 "cc_reg_operand" "")
            (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
                        (match_operand:SI 2 "non_short_cint_operand" "")))
       (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
      "find_single_use (operands[0], insn, 0)
       && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
           || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
      [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
       (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
      /* Get the constant we are comparing against, C, and see what it 
         looks like sign-extended to 16 bits.  Then see what constant 
         could be XOR'ed with C to get the sign-extended value.  */
      int c = INTVAL (operands[2]);
      int sextc = (c << 16) >> 16;
      int xorv = c ^ sextc;
      operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
      operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);

    To avoid confusion, don't write a single define_split that accepts some insns that match some define_insn as well as some insns that don't. Instead, write two separate define_split definitions, one for the insns that are valid and one for the insns that are not valid.

    Instruction Attributes

    In addition to describing the instruction supported by the target machine, the `md' file also defines a group of attributes and a set of values for each. Every generated insn is assigned a value for each attribute. One possible attribute would be the effect that the insn has on the machine's condition code. This attribute can then be used by NOTICE_UPDATE_CC to track the condition codes.

    Defining Attributes and their Values


    (define_attr name list-of-values default)








    #define HAVE_ATTR_type
    enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
                     TYPE_STORE, TYPE_ARITH};
    extern enum attr_type get_attr_type ();


    Attribute Expressions


    (const_int i)

    The value of a numeric attribute can be specified either with a const_int or as an integer represented as a string in const_string, eq_attr (see below), and set_attr (see section Assigning Attribute Values to Insns) expressions.

    (const_string value)
    The string value specifies a constant attribute value. If value is specified as `"*"', it means that the default value of the attribute is to be used for the insn containing this expression. `"*"' obviously cannot be used in the default expression of a define_attr.


    (if_then_else test true-value false-value)

    (cond [test1 value1 ...] default)

    test expressions can have one of the following forms:

    (const_int i)
    This test is true if i is non-zero and false otherwise.

    (not test)
    (ior test1 test2)
    (and test1 test2)
    These tests are true if the indicated logical function is true.

    (match_operand:m n pred constraints)
    This test is true if operand n of the insn whose attribute value is being determined has mode m (this part of the test is ignored if m is VOIDmode) and the function specified by the string pred returns a non-zero value when passed operand n and mode m (this part of the test is ignored if pred is the null string).

    The constraints operand is ignored and should be the null string.

    (le arith1 arith2)
    (leu arith1 arith2)
    (lt arith1 arith2)
    (ltu arith1 arith2)
    (gt arith1 arith2)
    (gtu arith1 arith2)
    (ge arith1 arith2)
    (geu arith1 arith2)
    (ne arith1 arith2)
    (eq arith1 arith2)

    const_int and symbol_ref are always valid terms (see section Computing the Length of an Insn,for additional forms). symbol_ref is a string denoting a C expression that yields an int when evaluated by the `get_attr_...' routine. It should normally be a global variable.

    (eq_attr name value)
    name is a string specifying the name of an attribute.

    value is a string that is either a valid value for attribute name, a comma-separated list of values, or `!' followed by a value or list. If value does not begin with a `!', this test is true if the value of the name attribute of the current insn is in the list specified by value. If value begins with a `!', this test is true if the attribute's value is not in the specified list.

    For example,

    (eq_attr "type" "load,store")

    is equivalent to


    If name specifies an attribute of `alternative', it refers to the value of the compiler variable which_alternative (see section C Statements for Assembler Output) and the values must be small integers. For example,

    (eq_attr "alternative" "2,3")

    is equivalent to



    (attr_flag name)

    name is a string specifying one of a fixed set of flags to test. Test the flags forward and backward to determine the direction of a conditional branch. Test the flags very_likely, likely, very_unlikely, and unlikely to determine if a conditional branch is expected to be taken.

    If the very_likely flag is true, then the likely flag is also true. Likewise for the very_unlikely and unlikely flags.


    (define_delay (eq_attr "type" "cbranch")
      [(eq_attr "in_branch_delay" "true") 
       (and (eq_attr "in_branch_delay" "true") 
            (attr_flag "forward"))
       (and (eq_attr "in_branch_delay" "true")
            (attr_flag "backward"))])


    The very_likely and likely flags are true if the insn being scheduled is not a conditional branch. The The very_unlikely and unlikely flags are false if the insn being scheduled is not a conditional branch.


    Assigning Attribute Values to Insns

    The value assigned to an attribute of an insn is primarily determined by which pattern is matched by that insn (or which define_peephole generated it). Every define_insn and define_peephole can have an optional last argument to specify the values of attributes for matching insns. The value of any attribute not specified in a particular insn is set to the default value for that attribute, as specified in its define_attr. Extensive use of default values for attributes permits the specification of the values for only one or two attributes in the definition of most insn patterns, as seen in the example in the next section.

    The optional last argument of define_insn and define_peephole is a vector of expressions, each of which defines the value for a single attribute. The most general way of assigning an attribute's value is to use a set expression whose first operand is an attr expression giving the name of the attribute being set. The second operand of the set is an attribute expression (see section Attribute Expressions) giving the value of the attribute.

    When the attribute value depends on the `alternative' attribute (i.e., which is the applicable alternative in the constraint of the insn), the set_attr_alternative expression can be used. It allows the specification of a vector of attribute expressions, one for each alternative.

    When the generality of arbitrary attribute expressions is not required, the simpler set_attr expression can be used, which allows specifying a string giving either a single attribute value or a list of attribute values, one for each alternative.

    The form of each of the above specifications is shown below. In each case, name is a string specifying the attribute to be set.

    (set_attr name value-string)
    value-string is either a string giving the desired attribute value, or a string containing a comma-separated list giving the values for succeeding alternatives. The number of elements must match the number of alternatives in the constraint of the insn pattern.

    Note that it may be useful to specify `*' for some alternative, in which case the attribute will assume its default value for insns matching that alternative.

    (set_attr_alternative name [value1 value2 ...])
    Depending on the alternative of the insn, the value will be one of the specified values. This is a shorthand for using a cond with tests on the `alternative' attribute.

    (set (attr name) value)
    The first operand of this set must be the special RTL expression attr, whose sole operand is a string giving the name of the attribute being set. value is the value of the attribute.

    The following shows three different ways of representing the same attribute value specification:

    (set_attr "type" "load,store,arith")
    (set_attr_alternative "type"
                          [(const_string "load") (const_string "store")
                           (const_string "arith")])
    (set (attr "type")
         (cond [(eq_attr "alternative" "1") (const_string "load")
                (eq_attr "alternative" "2") (const_string "store")]
               (const_string "arith")))

    The define_asm_attributes expression provides a mechanism to specify the attributes assigned to insns produced from an asm statement. It has the form:

    (define_asm_attributes [attr-sets])

    where attr-sets is specified the same as for both the define_insn and the define_peephole expressions.

    These values will typically be the "worst case" attribute values. For example, they might indicate that the condition code will be clobbered.

    A specification for a length attribute is handled specially. The way to compute the length of an asm insn is to multiply the length specified in the expression define_asm_attributes by the number of machine instructions specified in the asm statement, determined by counting the number of semicolons and newlines in the string. Therefore, the value of the length attribute specified in a define_asm_attributes should be the maximum possible length of a single machine instruction.

    Example of Attribute Specifications

    The judicious use of defaulting is important in the efficient use of insn attributes. Typically, insns are divided into types and an attribute, customarily called type, is used to represent this value. This attribute is normally used only to define the default value for other attributes. An example will clarify this usage.

    Assume we have a RISC machine with a condition code and in which only full-word operations are performed in registers. Let us assume that we can divide all insns into loads, stores, (integer) arithmetic operations, floating point operations, and branches.

    Here we will concern ourselves with determining the effect of an insn on the condition code and will limit ourselves to the following possible effects: The condition code can be set unpredictably (clobbered), not be changed, be set to agree with the results of the operation, or only changed if the item previously set into the condition code has been modified.

    Here is part of a sample `md' file for such a machine:

    (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
    (define_attr "cc" "clobber,unchanged,set,change0"
                 (cond [(eq_attr "type" "load")
                            (const_string "change0")
                        (eq_attr "type" "store,branch")
                            (const_string "unchanged")
                        (eq_attr "type" "arith")
                            (if_then_else (match_operand:SI 0 "" "")
                                          (const_string "set")
                                          (const_string "clobber"))]
                       (const_string "clobber")))
    (define_insn ""
      [(set (match_operand:SI 0 "general_operand" "=r,r,m")
            (match_operand:SI 1 "general_operand" "r,m,r"))]
       move %0,%1
       load %0,%1
       store %0,%1"
      [(set_attr "type" "arith,load,store")])

    Note that we assume in the above example that arithmetic operations performed on quantities smaller than a machine word clobber the condition code since they will set the condition code to a value corresponding to the full-word result.

    Computing the Length of an Insn

    For many machines, multiple types of branch instructions are provided, each for different length branch displacements. In most cases, the assembler will choose the correct instruction to use. However, when the assembler cannot do so, GCC can when a special attribute, the `length' attribute, is defined. This attribute must be defined to have numeric values by specifying a null string in its define_attr.

    In the case of the `length' attribute, two additional forms of arithmetic terms are allowed in test expressions:

    (match_dup n)
    This refers to the address of operand n of the current insn, which must be a label_ref.

    This refers to the address of the current insn. It might have been more consistent with other usage to make this the address of the next insn but this would be confusing because the length of the current insn is to be computed.

    For normal insns, the length will be determined by value of the `length' attribute. In the case of addr_vec and addr_diff_vec insn patterns, the length is computed as the number of vectors multiplied by the size of each vector.

    Lengths are measured in addressable storage units (bytes).

    The following macros can be used to refine the length computation:

    When the length insn attribute is used, this macro specifies the value to be assigned to the address of the first insn in a function. If not specified, 0 is used.

    ADJUST_INSN_LENGTH (insn, length)
    If defined, modifies the length assigned to instruction insn as a function of the context in which it is used. length is an lvalue that contains the initially computed length of the insn and should be updated with the correct length of the insn. If updating is required, insn must not be a varying-length insn.

    This macro will normally not be required. A case in which it is required is the ROMP. On this machine, the size of an addr_vec insn must be increased by two to compensate for the fact that alignment may be required.

    The routine that returns get_attr_length (the value of the length attribute) can be used by the output routine to determine the form of the branch instruction to be written, as the example below illustrates.

    As an example of the specification of variable-length branches, consider the IBM 360. If we adopt the convention that a register will be set to the starting address of a function, we can jump to labels within 4k of the start using a four-byte instruction. Otherwise, we need a six-byte sequence to load the address from memory and then branch to it.

    On such a machine, a pattern for a branch instruction might be specified as follows:

    (define_insn "jump"
      [(set (pc)
            (label_ref (match_operand 0 "" "")))]
       return (get_attr_length (insn) == 4
               ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
      [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
                                          (const_int 4)
                                          (const_int 6)))])

    Constant Attributes

    A special form of define_attr, where the expression for the default value is a const expression, indicates an attribute that is constant for a given run of the compiler. Constant attributes may be used to specify which variety of processor is used. For example,

    (define_attr "cpu" "m88100,m88110,m88000"
      (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
             (symbol_ref "TARGET_88110") (const_string "m88110")]
            (const_string "m88000"))))
    (define_attr "memory" "fast,slow"
      (if_then_else (symbol_ref "TARGET_FAST_MEM")
                    (const_string "fast")
                    (const_string "slow"))))

    The routine generated for constant attributes has no parameters as it does not depend on any particular insn. RTL expressions used to define the value of a constant attribute may use the symbol_ref form, but may not use either the match_operand form or eq_attr forms involving insn attributes.

    Delay Slot Scheduling

    The insn attribute mechanism can be used to specify the requirements for delay slots, if any, on a target machine. An instruction is said to require a delay slot if some instructions that are physically after the instruction are executed as if they were located before it. Classic examples are branch and call instructions, which often execute the following instruction before the branch or call is performed.

    On some machines, conditional branch instructions can optionally annul instructions in the delay slot. This means that the instruction will not be executed for certain branch outcomes. Both instructions that annul if the branch is true and instructions that annul if the branch is false are supported. Delay slot scheduling differs from instruction scheduling in that determining whether an instruction needs a delay slot is dependent only on the type of instruction being generated, not on data flow between the instructions. See the next section for a discussion of data-dependent instruction scheduling.

    The requirement of an insn needing one or more delay slots is indicated via the define_delay expression. It has the following form:

    (define_delay test
                  [delay-1 annul-true-1 annul-false-1
                   delay-2 annul-true-2 annul-false-2

    test is an attribute test that indicates whether this define_delay applies to a particular insn. If so, the number of required delay slots is determined by the length of the vector specified as the second argument. An insn placed in delay slot n must satisfy attribute test delay-n. annul-true-n is an attribute test that specifies which insns may be annulled if the branch is true. Similarly, annul-false-n specifies which insns in the delay slot may be annulled if the branch is false. If annulling is not supported for that delay slot, (nil) should be coded.

    For example, in the common case where branch and call insns require a single delay slot, which may contain any insn other than a branch or call, the following would be placed in the `md' file:

    (define_delay (eq_attr "type" "branch,call")
                  [(eq_attr "type" "!branch,call") (nil) (nil)])

    Multiple define_delay expressions may be specified. In this case, each such expression specifies different delay slot requirements and there must be no insn for which tests in two define_delay expressions are both true.

    For example, if we have a machine that requires one delay slot for branches but two for calls, no delay slot can contain a branch or call insn, and any valid insn in the delay slot for the branch can be annulled if the branch is true, we might represent this as follows:

    (define_delay (eq_attr "type" "branch")
        (eq_attr "type" "!branch,call")
    (define_delay (eq_attr "type" "call")

    Specifying Function Units

    On most RISC machines, there are instructions whose results are not available for a specific number of cycles. Common cases are instructions that load data from memory. On many machines, a pipeline stall will result if the data is referenced too soon after the load instruction.

    In addition, many newer microprocessors have multiple function units, usually one for integer and one for floating point, and often will incur pipeline stalls when a result that is needed is not yet ready.

    The descriptions in this section allow the specification of how much time must elapse between the execution of an instruction and the time when its result is used. It also allows specification of when the execution of an instruction will delay execution of similar instructions due to function unit conflicts.

    For the purposes of the specifications in this section, a machine is divided into function units, each of which execute a specific class of instructions in first-in-first-out order. Function units that accept one instruction each cycle and allow a result to be used in the succeeding instruction (usually via forwarding) need not be specified. Classic RISC microprocessors will normally have a single function unit, which we can call `memory'. The newer "superscalar" processors will often have function units for floating point operations, usually at least a floating point adder and multiplier.

    Each usage of a function units by a class of insns is specified with a define_function_unit expression, which looks like this:

    (define_function_unit name multiplicity simultaneity
                          test ready-delay issue-delay

    name is a string giving the name of the function unit.

    multiplicity is an integer specifying the number of identical units in the processor. If more than one unit is specified, they will be scheduled independently. Only truly independent units should be counted; a pipelined unit should be specified as a single unit. (The only common example of a machine that has multiple function units for a single instruction class that are truly independent and not pipelined are the two multiply and two increment units of the CDC 6600.)

    simultaneity specifies the maximum number of insns that can be executing in each instance of the function unit simultaneously or zero if the unit is pipelined and has no limit.

    All define_function_unit definitions referring to function unit name must have the same name and values for multiplicity and simultaneity.

    test is an attribute test that selects the insns we are describing in this definition. Note that an insn may use more than one function unit and a function unit may be specified in more than one define_function_unit.

    ready-delay is an integer that specifies the number of cycles after which the result of the instruction can be used without introducing any stalls.

    issue-delay is an integer that specifies the number of cycles after the instruction matching the test expression begins using this unit until a subsequent instruction can begin. A cost of N indicates an N-1 cycle delay. A subsequent instruction may also be delayed if an earlier instruction has a longer ready-delay value. This blocking effect is computed using the simultaneity, ready-delay, issue-delay, and conflict-list terms. For a normal non-pipelined function unit, simultaneity is one, the unit is taken to block for the ready-delay cycles of the executing insn, and smaller values of issue-delay are ignored.

    conflict-list is an optional list giving detailed conflict costs for this unit. If specified, it is a list of condition test expressions to be applied to insns chosen to execute in name following the particular insn matching test that is already executing in name. For each insn in the list, issue-delay specifies the conflict cost; for insns not in the list, the cost is zero. If not specified, conflict-list defaults to all instructions that use the function unit.

    Typical uses of this vector are where a floating point function unit can pipeline either single- or double-precision operations, but not both, or where a memory unit can pipeline loads, but not stores, etc.

    As an example, consider a classic RISC machine where the result of a load instruction is not available for two cycles (a single "delay" instruction is required) and where only one load instruction can be executed simultaneously. This would be specified as:

    (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)

    For the case of a floating point function unit that can pipeline either single or double precision, but not both, the following could be specified:

       "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
       "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])

    Note: The scheduler attempts to avoid function unit conflicts and uses all the specifications in the define_function_unit expression. It has recently come to our attention that these specifications may not allow modeling of some of the newer "superscalar" processors that have insns using multiple pipelined units. These insns will cause a potential conflict for the second unit used during their execution and there is no way of representing that conflict. We welcome any examples of how function unit conflicts work in such processors and suggestions for their representation.

    Go to the previous, next section.