Mask Layout

The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow, where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor. Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area, which is used to realize a certain function. On the other hand, the detailed mask layout of logic gates requires a very intensive and time-consuming design effort.

The physical (mask layout) design of CMOS logic gates is an iterative process, which starts with the circuit topology and the initial sizing of the transistors. It is extremely important that the layout design must not violate any of the Layout Design Rules, in order to ensure a high probability of defect-free fabrication of all features described in the mask layout.


In this tutorial, a simple CMOS inverter layout will be drawn step by step. We will start with a simple design idea and will complete the mask layout using different techniques.

Steps of Layout Design

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Moin: Cadence/Tutorial/Layout (last edited 2008-07-19 22:05:42 by localhost)