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I have read about different implementations of HFT systems on FPGAs.

Vendors like Cisco claim they have achieved the same results with high performance NIC's (

My question is, what part of HFT systems are mostly implemented on FPGAs nowadays? Are FPGAs still very popular? Is only the feed handler implemented on the FPGAs? Because some of these systems described above only have a feed handler implemented on the FPGA, because the strategy changes too much, or is too hard to implement on FPGAs. Others claim that they have also implemented trading strategies on FPGAs or using high performance NICs instead of FPGAs to build HFT systems. I've read about different approaches but I find it hard to compare as most of the results are tested on different input sets.

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5 Answers 5

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Here's a way to think about it: imagine you can do something in an ASIC (i.e. directly in hardware). However, the process of fabrication is in itself expensive, and you get a design that you cannot change afterwards. ASICs make sense for predefined tasks such as Bitcoin mining, well-known data processing algorithms, etc.

On the other hand we have ordinary CPUs (as well as coprocessor CPUs and GPUs) which are general-purpose, but process a small (in terms of concurrent instructions) set of instructions at a very high speed.

FPGAs are the middle ground. They are 'hardware emulators' and as such can be considered to be 10x slower than actual hardware, but still way more performant for concurrent operations than CPUs provided you are able to utilize the die to spread your logic accordingly.

Some uses of FPGAs are:

  • Video transcoding (e.g. HD video decoding in TVs) as well as various data acquisition boards
  • Fixed data structure parsing (Regex parsing)
  • Discrete system simulation (for example, simulating the outcome of a card game)
  • Lots of 'properly embedded' applications such as e.g. in aerospace or scientific research

The problem with FPGAs for quant uses is that it's not so good for floating-point calculations, particularly since ordinary CPUs are already optimized for that with things like SIMD. However, for anything fixed-point or fixed-size data structures, FPGA design allows you to configure the device to do a lot of processing at the same time.

Some things done in trading are using FPGA for feed handlers (parsing directly from the network stream) as well as building certain parts of the trading structure (e.g. order books) in hardware in order to be able to deal with the rapidly changing data structure without loading the CPU.

FPGAs mainly aim to address the concern of quickly processing data without paying the propagation costs. This is particularly in contrast with devices such as GPGPU (or any PCI-dwelling card, such as Xeon Phi) which pay performance penalties for getting data to/from the device. That said, DMA options are improving in this regard, too.

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FPGA's are really nothing more than the same logic blocks repeated again and again throughout the silicon, with configurable switches to connect the logic blocks together. This makes FPGA's very good--and fast--at dealing with repetitive problems that can be described in a hardware circuit that does not change during operation. And you can have literally thousands or tens of thousands of these circuits, all working in parallel at the same time, in just one FPGA.

CPU's on the other hand are based around the ALU, which loads instructions, loads data, operates on the data, maybe stores the results, and then does it all over again. CPU's then are very good--and fast--at dealing with problems that are continually changing--both in size and in scope and at switching between different tasks. Today's CPU or core will have tens to hundreds of ALU's with parallel pipelines for data and instructions, which makes them very fast at complex problems that can be worked on in parallel.

These designs make FPGA's faster at simpler problems that can be attacked with a vast parallel architecture--such as condensing down multiple data feeds in less than micro-second, wire-to-wire, or triggering a pre-calculated buy, sell or cancel on a price that matches a particular pattern. CPU's are faster at more complex problems that require less parallelism, such as calculating the basket of buys, sells and cancels needed to keep a portfolio risk-adjusted or integrating a number of price and news sources of varying age and quality into trading indicators used by traders and management to decide what adjustments they will make to the trading system.

Where FPGA's are used in HFT depends a lot on the architecture of particular shop. They are best used performing simple, repetitive, wide tasks and performing them quickly. CPU's are a Swiss knife that can do most anything, especially where the requirements are changing and the dimensions of the problem are not fully understood at the outset.

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Your question really makes not much sense. It's like asking how much of the wiring in trading infrastructure uses optic fiber and how much of it uses copper. The best answer that we can give to you is that an FPGA is not a magic bullet.


This is an incorrect interpretation of Cisco's white paper. There's very little overlap between the use cases of switching fabric and those of a FPGA.

what part of HFT systems are mostly implemented on FPGAs nowadays?

Currently, FPGAs are often used in our printers and TV set-top boxes.

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I want to highlight the “digital signal processing” (DSP) block with ALUs. Today’s FPGAs have hundreds of programmable DSP blocks – the very largest having thousands.

Now, suddenly, you have thousands of small processors at your disposal, all able to perform calculations in parallel. This is vastly in excess of parallelism provided by the Xeon Phi or GPUs. In fact, if you’re doing options price modelling or stochastic risk modelling on FPGA, you can get more than 100-fold increase in performance compared to the latest GPUs and even more compared to the latest CPUs.

Along with the DSP blocks, the other major factor in this performance gain is the memory cache. FPGA has built-in distributed RAM that is extremely fast, allowing bandwidth of 100TB/s to be achieved at datapath level.

Using today’s FPGAs for algo strategies gives large and massively concurrent compute resource that is able to give 100 to 1000 fold increase in performance compared to GPUs or CPUs. The main caveat is that you would have to become proficient in writing in Verilog or VHDL :)

Sanjay Shah CTO Nanospeed

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A variety of powerful, many-core processors are beginning to make their way into the the hardware acceleration space that was previously completely "owned" by FPGAs. Companies like Tilera, Adapteva, and Coherent Logix all provide these processors here in the US, with Enyx from France also making inroads.

The true measure of effectiveness of these massively parallel processors lies in the maturity of their software tools. That's where the prospective user should focus their attention. Nobody wants to program or debug tens or hundreds of cores using manual techniques. Of course, it goes without saying that I/O bandwidth is as important.

In my personal experience in this space I'm seeing customer adoption of Coherent Logix processors as co-processors or hardware accelerators for C-language algo acceleration. By enjoying the rapid design cycle of a C based environment, algo programmers can tweak code to their hearts content and not worry about costly and time intensive HDL coding for FPGAs.

The optimal partitioning is to have FPGAs do what they do best - fixed repetitive operations - and have many-core processors do what they do best: accelerate algo developers productivity and execution speed.

John Irza, Business Development Manager, Coherent Logix, Inc.

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