The incredible shrinking NAND: I'm MEELLLLTING

Flash array bubbles burst

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Blocks and Files NAND is heading to the graveyard, getting closer and closer with every geometry shrink and every added cell bit. Any replacement NV-RAM technology will require controller software rip-and-replace, which could kill one trick pony flash array startups.

NAND flash is non-volatile but expensive to make and both ways of making it more affordable are leading into technology dead-ends. The first way is to shrink the process geometry and so get more flash dies from a wafer, lowering the cost per die. But process shrinks cause the flash's working life, in terms of program/erase (PE) cycles, the number of times a flash cell can be written to, to decline.

It's generally thought that a 59-50nm (5Xnm) process size gives us 10,000 2bit multi-level cell (MLC) PE cycles. A 3Xnm (39-30nm) process gives us 5,000 and a 2Xnm cell gives us 3,000. A 1Xnm cell will provide a derisory endurance rating without greatly over-provisioning the NAND product with extra cells ready to see when the first ones wear out.

NAND controller software can work to overcome this trend, and has already done so – using techniques to reduce the number of writes, get better at treading data from cells that are wearing out, and over-provisioning. The problem is that this usually only takes place as the problems are mounting up.

And they are mounting up, because the second affordability approach is to add extra bits to the basic 1-bit flash cell – single level cell (SLC) flash. MLC is 2 bits per cell. TLC is 3 bits per cell.

With a 3Xnm process: SLC NAND can do 10,000 PE cycles; MLC can do 5,000 cycles; and TLC can do 1,250. It's estimated 2Xnm TLC can do 750 cycles. Imagine the limited and shorter endurance of 1Xnm TLC NAND; are we looking at sub-500 cycles?

We can say with certainty that we will not see 4-bits per cell NAND and that we might not see – in fact probably won't – NAND process geometry going below 10nm, or even below 15nm. It's a dead-end game.

This is known and generally understood and the timescale is such that 2Xnm TLC will enter enterprise storage use this year and take us through to, say, 2014. After that, 1Xnm TLC may be feasible and sub-1Xnm TLC most likely won't happen. So what will happen, because the need for higher-capacity, longer-lived and more affordable non-volatile memory won't go away.



In the worst case, NAND storage start-ups will find their competitive advantage is no longer sustainable and they will fail. The flash SSD controller companies and controller software-owning companies will need to write fresh code stacks if they enter the post-NAND NV-RAM (non-volatile RAM) product space. Suddenly everyone in the NAND controller software business is plonked back down at the starting tape, all starting afresh.

A venture capitalist and a long-term investor looking at this picture and agreeing with it, would say the flash and hybrid flash/disk storage startups have no long-term future with their technology and are stuck on fast-forward into a dead-end. Unless their firms are acquired, the investors behind them will probably not get the return they want and could lose their cash. The smarter ones behind the flash and hybrid flash/disk startups already knew this. Acquisition is the only realistic exit strategy.

Do the potential acquirers know this too? Do they appreciate that sky-high valuations of flash array and hybrid flash/disk array start-ups are short-term and unsustainable? Billion-dollar plus asking prices for buying flash array start-ups could simply not get paid. Expectations have got to come down to earth. We could be in a flash array bubble and it's about to burst because NAND's limitations are becoming ever clearer.

Enterprise flash, in the longer scheme of things, could be over in a flash. ®

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