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Shortcomings of The Simple CPUs Chapter 6.4 - 6.6 Yok Fai Ho.

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Presentation on theme: "Shortcomings of The Simple CPUs Chapter 6.4 - 6.6 Yok Fai Ho."— Presentation transcript:

1 Shortcomings of The Simple CPUs Chapter Yok Fai Ho

2 Shortcomings of The Simple CPUs In this section of the chapter, it go into more detail on how to design a faster and more efficient CPU.

3 Main Points More Internal Registers And Cache. Multiple Buses Within The CPU. Pipelined Instruction Processing. Larger Instruction Sets. Subroutines And Interrupts. Internal Architecture of The Intel 8085 Microprocessor.

4 More Internal registers And Cache Enable to build a faster CPU, one of the best ways to improve the performance of a microprocessor is to incorporate more storage within the CPU. Adding registers and cache makes it possible to replace some external memory accesses with much faster internal accesses. CPURegistersRAMCache

5 More Internal registers And Cache In most of our home PC, there are 256K-512K of cache in the CPUs. Some early model only have 16K of cache. Because the register and cache are more expensive than RAM. So many computer turn to RAM as their main memory storage. But at the same time the speed decrease.

6 More Internal registers And Cache Sun Microsystems. It has 1 MB of cache. Some even go up to 4 MB of cache

7 Multiple Buses Within the CPU Buses are efficient media for routing data between components within a CPU. However, a bus may only contain one value at any given time. Because of that, most CPUs contain multiple buses for multiple data transfers. That reduces the time needed to fetch, decode, and execute instructions, thus improving system performance.

8 Diagram of Simple CPU using multiple buses

9 Pipelined instruction processing In pipelining, instructions are processed like goods on an assembly line. While one instructions is being decoded, the next instruction is fetched, and while the first instruction is being executed, the second is decoded and a third instruction is fetched. This allows programs to be executed more quickly, even though each individual instruction requires the same amount of time.

10 Pipelined instruction processing washerdryercloset washerclosetdryer closetdryerwasher Step 1Step 2Step 3Step 4Step 5 first second third

11 Larger Instruction Sets Having a larger number of instructions in a processor’s instruction set generally allows a program to perform a function using fewer instructions.

12 Larger Instruction Sets (A’ * B’)’ = (A + B) Consider a CPU have a small instruction sets can only have AND. Complement A Complement B AND A and B Complement the result OR A and B

13 Subroutines and Interrupts Almost all CPUs have hardware to handle subroutines, typically a stack pointer, and instructions to call and return from the subroutine. Most CPUs also have interrupt inputs to allow external hardware(like mouse, keyboard …) to interrupt the current operations of the CPU. That is useful, if you know the program is a infinite loop and want to exit the program.

14 Internal organization of the 8085 microprocessor

15 Summary To design a CPU, we first develop its instruction set architecture,including its instruction set and its internal registers. We then create a finite state machine model of the micro-operations needed to fetch, decode, and execute every instruction in its instruction set. Then we develop an RTL specification for this state machine.

16 References Carpinelli, D. John. Computer System Organization and Architecture. Addison-Wesley,

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