Power/Energy Estimation and Optimization for Software-Oriented Embedded Systems

Thesis on modelization of energy consumption on a Texas DSP. Thesis is composed like this : 

  • Reminder on the modeling technique of software
  • Energy consumption Definition of a precise model of energy consumption
  • Evaluation of the influence of the compiler on the power consumption
  • Application of the model on green patterns: modification of loop ...


The importance of power reduction of embedded systems has continuously increased in the past years. Recently, reducing power dissipation and energy consumption of a program have become optimization goals in their own right, no longer considered a side-effect of traditional performance optimizations which mainly target program execution time and/or program size. Nowadays, there is an increasing demand for developing power-optimizing

compilers for embedded systems. This thesis is a step towards such important goal.

In this thesis, we develop functional-level power models and investigate several software optimization techniques for embedded-processor systems. As a speciﬁc example, we consider the powerful Texas Instruments C6416T DSP processor. We analyze the power consumption contributions of the different functional units of this DSP. We assess the effect of the compiler performance optimizations on the energy and power consumption. Moreover, we explore the impact of two special architectural features of this DSP; namely Software Pipelined Loop (SPLOOP) and the SIMD capabilities, on the energy and power consumption.

We also characterize the application-architecture correlation for our targeted architecture. The PCA multivariate statistical technique is employed to visualize the black box impact of the compiler and the hardware architecture over the software applications. This is achieved with the aid of biplots which is depicted in our analysis in such a way, so that it can show the maximum association between the application and the underlying hardware architecture. Hence, it answers the question whether a given hardware architecture is an appropriate choice for a given software application or not.

The currently-available compiler optimization techniques are handicapped for power optimization due to their partial perspective of the algorithms and due to their limited modiﬁcations to the data structures. On the contrary, other software optimization techniques, like source code transformations, can exploit the full knowledge of the algorithm characteristics, with the capability of modifying both data structures and algorithm coding. Furthermore,

inter-procedural optimizations are envisioned. Hence, we investigate several loop, data and procedural source code transformations from the power and energy perspectives.

Based on our results and as a step towards a power-aware optimizing compiler, we can recommend the following recommendations for programmers and compiler designers. First,viii Abstract the programmers, targeting the C6000 DSP family, are strongly recommended to compile and optimize their programs by invoking the optimization level -o3 while disabling the SPLOOP feature (-mu) in conjunction with the utilization of SIMD capabilities via the employment of suitable intrinsic functions.

Second, we recommend the compiler designers to pay more attention to the circular (modulo) and bit reverse addressing schemes which are rarely utilized by the compiler. In addition, they should utilize the power-aware source code transformations.

Third, developers of power simulators need to embed a functional level power consumption model for the target processor in their simulators software.


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