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Several common packaging methods for electronic components

Release Date：2020-05-19

Component packaging plays a role in mounting, fixing, sealing, protecting chips and enhancing electrothermal performance. In addition, according to the contacts on the chip, the power lines are connected to the pins of the package casing. Such pins are connected to other components according to the power lines on the printed circuit board, thereby completing the internal chip and the external power circuit Connection.

Therefore, the chip must be protected from the outside to avoid the erosion of the chip power circuit caused by the residue in the air, resulting in the degradation of the performance of electrical equipment. And the packaged chips are also more conducive to installation and transportation. Because the quality of packaging immediately jeopardizes the full performance of the chip itself and the PCB design and manufacturing connected to it, packaging technology is particularly important.

The key index value considering whether a chip packaging technology is excellent is: the ratio of the total area of the chip to the total area of the package. The closer this ratio is to 1, the better.

Key considerations when packaging:

The ratio of the total area of the chip to the total area of the package is as close to 1: 1 as possible to improve the high efficiency of the package.

The pins should be as short as possible to reduce the delay time, and the spacing between the pins should be as far as possible to ensure mutual influence and improve performance.

According to the heat pipe heat dissipation regulations, the thinner the package, the better.

The following is a detailed introduction of the actual packaging method:


PLCC shows the abbreviation of "Plastic Leaded Chip Carrier" in English, that is, plastic package J wire chip package. PLCC packaging method, the design is square, 32-pin package, there are pins around, the size is much smaller than DIP package. The PLCC package is suitable for installing traces on the PCB using SMT surface mounting technology, which has the advantages of small size and high reliability.


TQFP shows the abbreviation of "Thin Quad Flat Package" in English, that is, thin plastic package four-corner flat package. The four-sided flat packaging process can reasonably use the indoor space, thereby reducing the size of the printed circuit board indoor space. Because of the reduced aspect ratio and volume, this type of packaging process is particularly suitable for applications that require higher indoor space requirements, such as PCMCIA cards and Internet components. Basically all ALTERA CPLD / FPGA are available in TQFP packages.


PQFP shows the abbreviation of "Plastic Quad Flat Package" in English, that is, plastic quadrilateral flat package. PQFP packaged chip pins have a small center pitch, and the pins are very thin. General scale or integrated circuit technology IC chips use this type of packaging, and the number of pins is usually above 100.


TSOP shows the abbreviation of "Thin Small Outline Package" in English, which is a thin small-sized package. A typical feature of TSOP running memory packaging technology is to make pins around the packaged chip. TSOP is suitable for mounting traces on PCB with SMT (Surface Mount) technology.

TSOP package design reduces parasitic parameters (when the amount of current changes greatly, causing the output voltage to oscillate). It is suitable for high-frequency use, and the actual operation is more convenient and the credibility is higher.


BGA shows the abbreviation of "Ball Grid Array Package" in English, that is, ball grid array package. In the 1990s, with the development of technology, the chip processing speed continued to increase, the number of I / O pins increased significantly, and the power also expanded, and the regulations on integrated circuit chip packaging were also more stringent. In order to consider the necessity of the development trend, BGA packaging has just been used in manufacturing.

The running memory packaged with BGA technology can increase the memory space by two to three times without changing the volume of the memory. Compared with TSOP, BGA has a smaller volume, stronger heat pipe heat dissipation and electrical performance. BGA packaging technology has greatly improved the storage capacity per square inch. Under the same volume, the operating memory products using BGA packaging technology can only be one-third of the TSOP package. In addition, compared with the traditional TSOP packaging method, the BGA packaging method has a more rapid and reasonable heat pipe heat dissipation method.

The I / O terminals of the BGA package are distributed under the package in a ring or column spot welding in an array. The advantage of the BGA technology is that although the number of I / O pins has increased, the pin spacing has not decreased but has increased. In turn, the assembly output rate is increased. Despite its increased power, the BGA can be welded with a controllable collapse chip method, which in turn can improve its electrothermal performance. The thickness and net weight are reduced to some extent compared with the previous packaging technology; the parasitic parameters are reduced, the data signal transmission delay time is small, and the application frequency is further improved; the assembly can be welded by coplanar welding, with high reliability.

Tiny BGA

When it comes to BGA packaging, it is necessary to mention Kingmax ’s patented TinyBGA technology. TinyBGA English is called "TinyBallGrid", which belongs to a branch of BGA packaging technology. It was developed and designed by Kingmax in August 1999 and succeeded. The ratio of the total area of the chip to the total area of the package is not less than 1: 1.14, which can increase the memory space by 2 to 3 times without changing the volume of the memory. Compared with TSOP packaged products, it has a smaller volume, stronger heat pipe heat dissipation performance and electrical performance.

Running memory products using TinyBGA packaging technology, under the same volume condition, only 1/3 of the TSOP package. The pins of the TSOP package running memory are drawn from the periphery of the chip, while the TinyBGA is drawn from the chip management center. This type of method reasonably reduces the transmission distance of the data signal. The length of the data signal coaxial cable is only 1/4 of the traditional TSOP technology, so the attenuation coefficient of the data signal also decreases. That not only greatly improves the chip's anti-interference and anti-noise performance, but also improves the electrical performance. The TinyBGA packaged chip can resist the external frequency of 300MHz, while the traditional TSOP packaging technology can only resist the external frequency of 150MHz.

The operating memory of the Tiny BGA package is thinner and thinner (the package aspect ratio is less than 0.8 mm), and the reasonable heat pipe heat dissipation relative path from the metal-based steel plate to the heat pipe heat sink is only 0.36 mm. Therefore, TinyBGA running memory has a higher thermal conductivity and high efficiency, which is very suitable for long-term operation of system software and has excellent reliability.


QFP is the abbreviation of "Quad Flat Package", that is, small and medium-sized lattice plan package. QFP packaging is often used in the initial discrete graphics cards, but there are small QFP graphics card memory with a rate above 4ns. Due to the processing technology and performance problems, it has been slowly replaced by TSOP-II and BGA at this stage. QFP encapsulates the needle corners around the particles, which is very obvious to identify. Flat package with four-sided pins. One of the surface mount packages, the pins are drawn from the four sides to form a red-billed gull wing (L) type.

There are three kinds of plates: porcelain, metal material and plastic. From the total point of view, plastic packaging accounts for the vast majority. When the raw materials are not clearly indicated, most of the conditions are plastic QFP. Plastic QFP is the most popular multi-pin LSI package. It is not only used for digital logic LSI power circuits such as microcontrollers and door display designs, but also used to simulate LSI power circuits such as VTR signal analysis and speaker signal analysis.

The center distance of the pin management is 1.b250m, 0.8 mm, 0.65mm, 0. mm, 0.4mm, 0.2mm and other specifications. The maximum number of pins in the 0.65mm management center distance is 304.

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