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Sobel Edge Detection Algorithm with Computer Vision Toolbox

This example shows and explains the "Top-Down" design methodology that is applied to Sobel Edge Detection algorithm. The Sobel Edge Detection algorithm is a popular yet simple edge detection algorithm and is the focus of this example. With this example you will learn:



  • How to co-simulate hand-written HDL code (corresponding to your Simulink model) with ModelSim® or Cadence® Incisive® in the Simulink environment.




  • Simulink

  • Fixed-Point Designer™

  • HDL Verifier™

  • Computer Vision Toolbox™

  • DSP System Toolbox™

  • ModelSim SE or PE. or Cadence Incisive

The Executable Specification of Sobel Edge Detection Algorithm


To implement a DSP algorithm on hardware such as ASIC or an FPGA, a system level engineer first designs the algorithm and verifies that the algorithm satisfies the project requirements. This design later becomes the golden reference for the engineers responsible for taking the algorithm to the hardware.




Design and Verification of the Algorithm for Implementation


In this example, the developers may decide to eliminate the square operations and replace them with the absolute value operation for more efficient hardware implementation. This will cause a difference between the cosimulation result and the golden reference but for the sake of this example, we assume that the difference is acceptable. Open the edge detection design model. You can see the same test vectors as the previous model are still being used. The result can be easily verified against the golden reference. A numerical display shows the mean difference between the golden reference and the new design.

Fixed-Point Design

Since our ultimate goal is to implement the algorithm in an FPGA or an ASIC, we must convert our double precision design to a fixed-point design. This can be done easily using Simulink. We use the double precision model we developed in the previous section to directly develop a fixed-point model without introducing any new blocks. Simulink allows us to determine the number of bits and scaling for data as well as mathematical operations, and provides a great environment for analyzing the fixed-point operation of a system.


Open the fixed-point model and examine how the fixed-point is implemented by double clicking on the computational blocks, such as the 2D filters or the addition block, and looking at the corresponding fixed-point panel.

Elaboration of the Design



This operation is done only for the bottom filter. As expected, the new design is still producing the same exact results as before. Two delay elements have been added to compensate for the buffing in the serializer block. This design also showcases the multi-rate capability of Simulink. The output of the serializer block is 20000 times higher in sampling rate relative to the input to that block.

Simulink® Cosimulation

The model from the previous section can be passed to the HDL designer who can use the 2D filter designed in the last section to write the corresponding VHDL or Verilog code. Once the code is written, the HDL designer can use HDL Verifier™ to simulate the HDL design in the Simulink environment using ModelSim or Incisive, and compare the output of the HDL design to the output of the executable specification. Note that in this process, there is no need for generating an HDL test bench. The Simulink model feeds the input test vector to ModelSim or Incisive through HDL Verifier and extracts the data from ModelSim or Incisive back to the Simulink environment. The HDL designer can readily verify whether the HDL code runs in accordance with the specifications.

  • ModelSim/QuestaSim

Refer to VHDL model or Verilog model to see how HDL Verifier is used to cosimulate Simulink and ModelSim. The last figure shows a snap shot of the signals displayed in ModelSim.

  • Incisive/Xcelium Refer to Verilog model to see how HDL Verifier software is used to cosimulate Simulink and the Incisive platform.