You are here

Phase Locked Loop

Study Project
April, 2002

Phase Locked Loop is an important circuit found in various communication devices, and here studied in a set up to synchronize input and local carrier signals for coherent demodulation of AM signals. PLL consists of a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector and loop filter combined produces an error signal which amplitude is linearly related to the phase difference of input and local carrier signals. The voltage-controlled oscillator adjusts appropriately to tune both signals as desired. PLL in integrated chip LM565C was studied and the working principals of PLL were verified. Parameters such as capture range, hold in range and loop gain were investigated. Capture range was determined to be 7.4 to 12.3 kHz, and the hold in range was found to be 4.8 to 14.6 kHz. PLL is an important and intricate circuit that can be studied at greater lengths.


Theme by Danetsoft and Danang Probo Sayekti inspired by Maksimer