Electronics > FPGA

HDL code for positive edge triggered J-K flip-flop with preset and clear

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Hi all,
I' new to HDL and I'm not yet able to write my own code so I'm using block diagram/schematics under Quartus II.I'm looking for Verilog code (I prefer this over VHDL) to implement TTL gates .I need code for a positive edge triggered J-K flip-flop with preset, clear and complementary outputs (like the 74LS109 for example).Can some one help me?Thanks in advance!

Try searching for "verilog jk flip flop" and I expect you will have your pick of examples.

I did many searches but found only example of JK flip flop with no preset.As aid, I need something like the 74LS019.

I speak VHDL, not Verilog, so I'm afraid I can't help with your example - but...

All too often I see people trying to learn a hardware description language by coding individual logic functions, then trying to build those up into a model of the circuit they actually want - like you'd have to do if you were restricted to building your circuit using off-the-shelf components.

I've seen examples that show ridiculously simple logic - like, say, a single OR gate - and wrap it up in a process or even a whole component, then instantiate it at a higher level in order to actually use it. This is kind of OK as a way to demonstrate the syntax of the language, but as a way to learn how to really use HDL, it's terribly misleading.

The beauty of an FPGA is that you can describe the behaviour you want without having to worry about how that behaviour might, possibly, be realised using off-the-shelf logic gates. If you're following a tutorial or worked example which does spend more than a trivial amount of time creating complex circuits this way, I'd advise you to look elsewhere. Don't ever get into the mind set of building real circuits directly from these traditional building blocks; that's the job of the synthesis tool, not you.

First you need the Truth Table for a JK flop with Preset
Pay very close attention to the effect of the asynchronous Preset and Clear inputs.

At page 6, there is a VHDL description for a JK flop with Preset

On page 7 there is code for the flop.  Note how the asynchronous Preset and Clear inputs are handled in the process before the clocking is even considered.  These asynchronous inputs mask out any transition change that might occur from the J and K inputs and the clock.

I don't use Verilog so transmorgifying from VHDL to Verilog is on you.


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