Interested In VHDL Training? Click Here

0 votes
in Verilog by (220 points)

What is repeat in Verilog and how do I use it?

3 Answers

0 votes
by (220 points)

Executes a statement a fixed number of times. If the expression evaluates to unknown or high impedance, it is treated as zero, and no statement is executed.

repeat (5) begin
i_data = 77;
@(negedge i_clk) i_en_str = 1;
@(negedge i_clk) i_en_str = 0;
@(posedge o_done);
speed = 434 * 2;

repeat (64) begin
@(posedge isys.clk);[15:8] = 8'h80 | (operation_index + start_position) % 64;;[7:0] = aes3_to_i2s_test_info.registers_expected[(operation_index + start_position) % 64];
if ((operation_index + start_position) % 64 == 0)[7] = 1'b0;
while (iuart_tx.busy) @(posedge isys.clk);
iuart_tx.enstr = 1'b1;
@(posedge isys.clk);
iuart_tx.enstr = 1'b0;
@(posedge iuart_tx.done);
0 votes
by (200 points)

The repeat statement is used to run a selected portion of code a specific number of times. It is similar to a for-loop. The difference is that there is no condition and the index is not used inside the loop. Repeat loop is used when we simply want to run a portion of code repeatedly for a fixed number of iterations. Example is given below:

module repeat_example (); 
reg r_Clock = 1'b0;
repeat (10)
#5 r_Clock = !r_Clock;
$display("Simulation Complete");
0 votes
by (220 points)

This is one of the loop statements of Verilog, and is usually used in testbench design. In case we would like to repeat the statement on how many times we want.

Want to improve your VHDL skills?

Click Here - Sign Up For VHDL Training



Send Us A Message
About Us

By using this site, you agree to the following:

Privacy Policy
Terms and Conditions
DMCA Policy
Earnings Disclaimer
Legal Disclaimer