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Although memristive devices with threshold voltages are the norm rather than the exception in experimentally realizable systems, their SPICE programming is not yet common. Here, we show how to implement such systems in the SPICE environment. Specifically, we present SPICE models of a popular voltage-controlled memristive system specified by five different parameters for PSPICE and NGSPICE circuit simulators. We expect this implementation to find widespread use in circuits design and testing.

In the last few years, circuit elements with memory, namely, memristive [@chua76a], memcapacitive and meminductive [@diventra09a] systems have attracted considerable attention from different disciplines due to their capability of non-volatile low-power information storage, potential applications in analog and digital circuits, and their ability to store and manipulate information on the same physical platform [@pershin11a]. However, when combined into complex circuits, progress in this field significantly relies on the available tools at our disposal. One such tool is the SPICE simulation environment, commonly used in circuit simulations and testing. While several SPICE models of memristive [@Biolek2009-1; @Benderli2009-1; @Biolek2009-2; @Shin10a; @Rak10a; @Yakopcic11a; @Kvatinsky12a], memcapacitive [@Biolek2009-2; @Biolek10b] and meminductive [@Biolek2009-2; @Biolek11b] elements are already available, they typically [@Biolek2009-1; @Benderli2009-1; @Biolek2009-2; @Shin10a; @Rak10a] rely on physical models without a threshold (see, e.g., Refs. [@strukov08a; @joglekar09a]).

Threshold-type switching is instead an extremely important common feature of memristive devices (for examples, see Ref. [@pershin11a]) and, due to physical constraints, likely to be common in memcapacitive and meminductive elements as well [@diventra13a]. Indeed, it is the threshold-type switching which is responsible for non-volatile information storage, serves as a basis for logic operations [@borghetti10a; @pershin12a], etc., and therefore, it can not be neglected. For instance, experimentally demonstrated memristive logic circuits [@borghetti10a] and emerging memory architectures [@linn10a] support fixed-threshold modeling [@pershin09b] of memristive devices. Moreover, the atomic migration responsible for resistance switching in many important experimental systems is induced by the applied field and not by the electric current flow. Therefore, models with voltage threshold [@pershin09b; @Yakopcic11a] are physically better justified than those with the current one [@Kvatinsky12a].

In the present paper we introduce a SPICE model for a memristive device with threshold voltage that has been proposed by the present authors [@pershin09b]. Using this type of memristive devices, we have already demonstrated and analyzed several electronic circuits including a learning circuit [@pershin09b], memristive neural networks [@pershin10c], logic circuits [@pershin12a], analog circuits [@pershin10d] and circuits transforming memristive response into memcapacitive and meminductive ones [@pershin09e]. These previous results thus demonstrate the range of applicability of the selected physical model. As a consequence, we expect its SPICE implementation to find numerous applications as well.

![image](fig1){width="6.5cm"}

The equations describing memristive systems can be formulated in the voltage- or current-controlled form [@chua76a]. In some cases, a voltage-controlled memristive system can be easily re-formulated as a current-controlled one and vice versa [@pershin11a]. Let us then focus on voltage-controlled memristive systems whose general definition (for an $n$th-order voltage-controlled memristive system) is given by the following relations $$\begin{aligned}
I(t)&=&R_M^{-1}\left(X,V_M,t \right)V_M(t) , \label{Condeq1}\\
\dot{X}&=&f\left( X,V_M,t\right) \label{Condeq2}\end{aligned}$$ where $X$ is the vector representing $n$ internal state variables, $V_M(t)$ and $I(t)$ denote the voltage and current across the device, and $R_M$ is a scalar, called the [*memristance*]{} (for memory resistance).

\[t\]

![image](fig2){width="5.5cm"}

    .subckt memristor pl mn PARAMS: Ron=1K Roff=10K Rinit=5K alpha=0 beta=1E13 Vt=4.6
    Bx 0 x I='(f1(V(pl,mn))>0) && (V(x)<Roff) ? {f1(V(pl,mn))}: (f1(V(pl,mn))<0) && (V(x)>Ron) ? {f1(V(pl,mn))}: {0}'
    Cx x 0 1 IC={Rinit}
    R0 pl mn 1E12
    Rmem pl mn r={V(x)}
    .func f1(y)={beta*y+0.5*(alpha-beta)*(abs(y+Vt)-abs(y-Vt))}
    .ends

    .subckt memristor pl mn PARAMS: Ron=1K Roff=10K Rinit=5K beta=1E13 Vtp=4.6 Vtm=4.6 nu1=0.0001 nu2=0.1
    Gx 0 x value={f1(V(pl)-V(mn))*(f2(f1(V(pl)-V(mn)))*f3(Roff-V(x))+f2(-f1(V(pl)-V(mn)))*f3(V(x)-Ron))}
    Raux x 0 1E12
    Cx x 0 1 IC={Rinit}
    Gpm pl mn value={(V(pl)-V(mn))/V(x)}
    .func f1(y)={beta*(y-Vtp)/(exp(-(y-Vtp)/nu1)+1)+beta*(y+Vtm)/(exp(-(-y-Vtm)/nu1)+1)}
    .func f2(y1)={1/(exp(-y1/nu1)+1)}
    .func f3(y)={1/(exp(-y/nu2)+1)}
    .ends

A specific realization of a voltage-controlled memristive system [*with threshold*]{} has been suggested by the present authors in Ref. [@pershin09b]. Such a memristive system is described by $$\begin{aligned}
I&=&X^{-1}V_M, \label{eq3} \\
\frac{\textnormal{d}X}{\textnormal{d}t}&=&f\left( V_M\right) \left[
\nonumber \theta\left( V_M\right)\theta\left( R_{off}-X\right) + \right. \\
 &{} &\qquad \qquad \qquad \left.
\theta\left(-V_M\right)\theta\left( X-R_{on}\right)\right], \label{eq4}\end{aligned}$$ with $$f(V_M)=\beta V_M+0.5\left( \alpha-\beta\right)\left[ |V_M+V_t|-|V_M-V_t| \right] \label{eq5}$$ where $V_t$ is the threshold voltage, $R_{on}$ and $R_{off}$ are limiting values of the memristance $R_M\equiv X$, and the $\theta$-functions (step functions) are used to limit the memristance to the region between $R_{on}$ and $R_{off}$. The important model parameters are the coefficients $\alpha$ and $\beta$ that characterize the rate of memristance change at $|V_M|< V_t$ and $|V_M|> V_t$, respectively. These two coefficients define the slopes of the $f(V_M)$ curve below and above the threshold (see Fig. \[fig1\]). When $\alpha=0$ (Fig. \[fig1\](b)), the device state changes only if $\left| V_M \right|>V_t$. Note that Eqs. (\[eq3\])-(\[eq5\]) are written in such a way that a positive/negative voltage applied to the top terminal with respect to the bottom terminal denoted by the black thick line always tends to increase/decrease the memristance $R_M$ (the opposite convention has been used in Ref. [@pershin09b]).

![image](fig3){width="4.5cm"}

The SPICE model for these devices is formulated following the general idea of Ref. [@Biolek2009-1]. For NGSPICE circuit simulator, the memristive system is realized as a sub-circuit combining a behavioral resistor $R$ (a resistor whose resistance can be specified by an expression), a current source $\uparrow$, and a capacitor $C$. Table \[tbl1\] presents the code of the sub-circuit. Its second line ([*Bx ...*]{}) defines the current source with the current specified through ternary functions. (A ternary function is defined in the code as $a$ ? $b$ : $c$ , which means “IF a, THEN b, ELSE c” [@ngspice].) The purpose of these functions is to limit $R_M$ between $R_{on}$ and $R_{off}$. The third line of the code in Table \[tbl1\] specifies the capacitor $C$ ([*Cx ...*]{}) with an initial condition. The fourth line ([*Rmem ...*]{}) defines the behavioral resistor whose resistance takes the same numerical value as the voltage across the capacitor. The next line ([*.func ...*]{}) provides the function $f$ according to Eq. (\[eq5\]). We have not experienced any convergence problems using Table \[tbl1\] model with NGSPICE simulator that potentially could result from “IF-THEN” statements. Clearly, Eq. (\[eq3\])-(\[eq5\]) could be programmed differently, employing smoothing functions (e.g., arctan(), sigmoid or similar function) as we do below in the case of PSPICE simulator model. Moreover, instead of “IF...THEN” statement in the Table \[tbl1\], one can use a step function based expression. In this case, the “Bx ...” line of the code should be replaced with “Bx 0 x I=$\{$f1(V(pl,mn))\*(u(V(pl,mn))\*u(Roff-V(x))+u(V(mn,pl))\*u(V(x)-Ron))$\}$”.

For PSPICE circuit simulator, the SPICE model of memristive device with threshold is formulated slightly differently without the use of behavioral resistor. Instead, we employ an additional current source playing the role of behavioral resistor [@Basso05a]. In addition, in order to avoid convergence problems, the function $f$ in Eq. (\[eq5\]) should be smoothed. In the most important case of $\alpha=0$, the smoothing of $f$ is straightforward. Table \[tbl2\] presents the code for PSPICE circuit simulator for this case. In Table \[tbl2\], $nu1$ and $nu2$ are smoothing parameters used in smoothed step functions $f2$ and $f3$ (although we prefer to use different smoothing parameters for functions of voltages and resistances, a common smoothing function could also be used). We have verified that simulation results are identical in both versions of SPICE and that PSPICE code is also compatible with LTspice circuit simulator. In addition, we note that the value of $beta$ in Table \[tbl2\] was selected to match switching times of real memristive devices that are in nanoseconds range. We suggest to select the maximum allowable time step not exceeding 0.01ns when using this value of $beta$.

Let us consider a memristive device with threshold directly connected to a sinusoidal voltage source $V(t)=V_0 \sin(2\pi \nu t)$ as presented in Fig. \[fig3\]. The circuit simulations are performed as a transient analysis of the circuit taking into account initial conditions (the [*uic*]{} option of [*.tran*]{}) within the NGSPICE circuit simulator. In our simulations, we consider two different types of memristive devices with threshold corresponding to two cases of functions $f(V_M)$ as presented in Fig. \[fig1\]. In the first case (that can be dubbed as a memristive device with a [*soft threshold*]{}) the coefficients $\alpha,\beta>0$ and $\alpha <\beta$. In this case, the memristance changes at any $V\neq 0$. However, the change is faster when the applied voltage magnitude is above the threshold voltage ($|V|>V_t$). In the second case (Fig. \[fig1\](b)), $\alpha =0$. Consequently, the memristance changes only when the applied voltage exceeds the threshold voltage ($|V|>V_{t}$). This second case is closer to the actual behavior of many experimentally realizable memristive systems [@pershin11a]. We call this type of systems as memristive devices with [*hard threshold*]{}.

\[fig4\]

Fig. \[fig4\] presents selected results of our simulations showing the circuit dynamics at long times (the initial transient interval is omitted). We consider two types of memristive devices – one with a soft and another with hard thresholds ($\alpha=0.1\beta$ and $\alpha=0$, respectively) – and plot the applied voltage, current and memristance as functions of time for these two cases at a frequency $\nu=0.05$GHz. Clearly, in both cases, the current through the device is not of the simple sine form. The plot of memristance as a function of time demonstrates that the range of memristance change in (a) is larger than in (b) (actually, in (a), $R_M$ switches between $R_{on}$ and $R_{off}$). The vertical dashed line in Fig. \[fig4\](a) helps noticing that in Fig. \[fig4\](a) the memristance starts changing as soon as the sign of applied voltage changes. In Fig. \[fig4\](b), instead, the change of $R_M$ occurs solely when $|V|>V_t$. As a consequence, the shapes of $R_M(t)$ in Fig. \[fig4\](a) and (b) are slightly different, and the steps in $R_M(t)$ in Fig. \[fig4\](b) are shifted along the horizontal axis compared to those in Fig. \[fig4\](a).

The current as a function of voltage at several selected values of $\nu$ is plotted in Fig. \[fig5\]. Clearly, these curves are typical frequency-dependent pinched hysteresis loops [@chua76a; @diventra09a]. The character of the loops for memristive systems with hard and soft thresholds is slightly different. While for memristive systems with soft threshold the curve for the lowest frequency has the smallest loop span, the situation for the memristive system with hard threshold is opposite: the largest loop span occurs at the lowest frequency. This result, however, is not surprising if we take into account the fact that in the memristive system with soft threshold the change of $R_M$ occurs at lower voltages. Moreover, the insets of Fig. \[fig5\] demonstrate the memristance $R_M(t)$ as a function of $V(t)$ at a particular frequency. It is not difficult to notice that in the case of the memristive system with hard threshold (shown in the inset of Fig. \[fig5\](b)), $R_M$ changes only when $\left| V\right|$ exceeds $V_t=4.6$V .

We have developed and tested a SPICE model of memristive devices with threshold voltage. In this model, the limiting conditions for the memristance are realized using ternary functions which adhere more closely to the actual physical situation, compared with the window functions approach previously suggested [@joglekar09a]. The memristive device is realized as a sub-circuit consisting of several elements. While the present model is based on a single internal state variable, $X$, it can be easily generalized to more complex physical models involving several internal state variables. We would like to note that the NGSPICE model presented in Table \[tbl1\] was included into the last distribution of NGSPICE [@ngspice]. Moreover, different convergence and simulation issues of memelements in SPICE will be considered in our future publication [@Biolek13a]. Finally, we note that threshold models of memcapacitive and meminductive systems can be implemented in the SPICE environment in a similar way.

[**Acknowledgements**]{}

This work has been partially supported by NSF grants No. DMR-0802830 and ECCS-1202383, and the Center for Magnetic Recording Research at UCSD.

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CHUA, L. O., KANG, S. M. Memristive devices and systems. *Proc. IEEE*, 1976, vol. 64, p. 209 - 223.

DI VENTRA, M., PERSHIN, Y. V., CHUA, L. O. Circuit elements with memory: Memristors, memcapacitors, and meminductors. *Proc. IEEE*, 2009, vol. 97, no. 10, pp. 1717 - 1724.

PERSHIN, Y. V., DI VENTRA, M. Memory effects in complex materials and nanoscale systems. *Advances in Physics*, 2011, vol. 60, p. 145 - 227.

BIOLEK, Z., BIOLEK, D., BIOLKOVA, V. SPICE model of memristor with nonlinear dopant drift. *Radioengineering*, 2009, vol. 18, no. 2, p. 210 - 214.

BENDERLI, S., WEY, T. A. On [SPICE]{} macromodelling of TiO2 memristors. *Electron. Lett.*, 2009, vol. 45, no. 7, p. 377 - 378.

BIOLEK, Z., BIOLEK, D., BIOLKOVA, V. SPICE modeling of memristive, memcapacitative and meminductive systems. *Proc. of ECCTD ’09, European Conference on Circuit Theory and Design*, August 23-27, 2009, p. 249 - 252.

SHIN, S., KIM, K., KANG, S.-M. Compact models for memristors based on charge-flux constitutive relationships. *IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.*, 2010, vol. 29, p. 590.

RAK, A., CSEREY, G. Macromodeling of the memristor in SPICE. *IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.*, 2010, vol. 29, p. 632.

YAKOPCIC, C., TAHA, T. M., SUBRAMANYAM, G., PINO, R. E., ROGERS, S. A memristor device model. *[IEEE]{} El. Dev. Lett.*, 2011, vol. 32, p. 1436.

KVATINSKY, S., FRIEDMAN, E. G., KOLODNY, A., WEISER, U. C. TEAM: ThrEshold adaptive memristor model. *[IEEE]{} Trans. Circ. Syst. I*, 2013, vol. 60, p. 211.

BIOLEK, D., BIOLEK, Z., BIOLKOVA, V. SPICE modelling of memcapacitor. *El. Lett.*, 2010, vol. 46, p. 520.

——. PSPICE modeling of meminductor. *Analog. Integr. Circ. Sig. Process.*, 2011, vol. 66, p. 129.

STRUKOV, D. B., SNIDER, G. S., STEWART, D. R., WILLIAMS, R. S. The missing memristor found. *Nature*, 2008, vol. 453, p. 80 - 83.

JOGLEKAR, Y. N., WOLF, S. J. The elusive memristor: properties of basic electrical circuits. *Eur. J. Phys.*, 2009, vol. 30, p. 661.

DI VENTRA, M., PERSHIN, Y. V. On the physical properties of memristive, memcapacitive, and meminductive systems. *Nanotechnology (in press)*, 2013; arXiv:1302.7063.

BORGHETTI, J., SNIDER, G. S., KUEKES, P. J., YANG, J. J., STEWART, D. R., WILLIAMS,R. S. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. *Nature*, 2010, vol. 464, p. 873 - 876.

PERSHIN, Y. V., DI VENTRA, M. Neuromorphic, digital and quantum computation with memory circuit elements *Proc. [IEEE]{}*, 2012, vol. 100, p. 2071.

LINN, E., ROSEZIN, R., WASER, R. Complementary resistive switches for passive nanocrossbar memories. *Nature Mat.*, 2010, vol. 9, p. 403.

PERSHIN, Y. V., LA FONTAINE, S., DI VENTRA, M. Memristive model of amoeba learning. *Phys. Rev. E*, 2009, vol. 80, p. 021926.

PERSHIN, Y. V., DI VENTRA, M. Experimental demonstration of associative memory with memristive neural networks. *Neural [N]{}etworks*, 2010, vol. 23, p. 881.

——. Practical approach to programmable analog circuits with memristors. *[IEEE]{} Trans. Circ. Syst. I*, 2010, vol. 57, p. 1857.

——. Memristive circuits simulate memcapacitors and meminductors. *Electronics Letters*, 2010, vol. 46, p. 517 - 518.

NENZI, P., VOGT, H. Ngspice Users Manual, version 25plus. 2013. Available at: http://ngspice.sourceforge.net/docs/ngspice-manual.pdf

BASSO, C. SPICE analog behavioral modeling of variable passives. *Power Electronics Technology*, April 2005, pp. 57 - 59.

BIOLEK, D., DI VENTRA, M., PERSHIN, Y. V. in preparation.

[**About Authors…**]{}

**Yuriy V. PERSHIN** was born in Russia. He received his Ph.D. degree in theoretical physics from the University of Konstanz, Konstanz, Germany, in 2002. His research interests span broad areas of nanotechnology, including physics of semiconductor nanodevices, spintronics, and biophysics.

**Massimiliano Di Ventra** was born in Italy. He received his Ph.D. degree in theoretical physics from the Ecole Polytechnique Federale de Lausanne, Switzerland, in 1997. His research interests are in the theory of electronic and transport properties of nanoscale systems, non-equilibrium statistical mechanics, DNA sequencing/polymer dynamics in nanopores, and memory effects in nanostructures for applications in unconventional computing and biophysics.
