{"push_id":915346312,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"2a144976728bc1cf7cc3c120ee20d4f542014e75","before":"34647abf49680c21be4f823121e64ff5da4eaca1","commits":[{"sha":"2a144976728bc1cf7cc3c120ee20d4f542014e75","author":{"email":"9a71e7c977055f3216e6ac993c790af4dbadc86f@gmail.com","name":"andrewray"},"message":"towards memories....\n\nStart a framework for replacing $memrd and $memwr cells.  Start with\na simple single port solution.  Will need specific xilinx, altera,\nasic etc generators.\n\nAlso, $meminit.","distinct":true,"url":"https://api.github.com/repos/ujamjar/hardcaml-yosys/commits/2a144976728bc1cf7cc3c120ee20d4f542014e75"}]}