{"push_id":716485267,"size":16,"distinct_size":16,"ref":"refs/heads/master","head":"1f440f60fbc99050ef24fe94b539564c93e56678","before":"2c2e05ad79f712d33136319bbc5049d3865c0a47","commits":[{"sha":"d8a3ed49a59fdf54ac3f311a75dca3e94b13eb26","author":{"email":"5ab9cdb82979a5e22201150e8d4ff9f187271b68@rock-chips.com","name":"Yunzhi Li"},"message":"libpayload: udc: dwc2: support force_shutdown() routine\n\nAdd force_shutdown() routine for dwc2 udc driver to support\ndisconnect and reconnect case when fastboot receiving data.\n\nBUG=chrome-os-partner:41687\nBRANCH=None\nTEST=None\n\nChange-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9\nOriginal-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0\nOriginal-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/281130\nOriginal-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Tested-by: Lin Huang <hl@rock-chips.com>\nOriginal-Commit-Queue: Jeffy Chen <jeffy.chen@rock-chips.com>\nReviewed-on: http://review.coreboot.org/10770\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/d8a3ed49a59fdf54ac3f311a75dca3e94b13eb26"},{"sha":"a1e5a7761ad824ffd8449db02fec9274eb165bc2","author":{"email":"3b0deacc4b5357f519084f1ea34bd42bf5d34545@chromium.org","name":"David Hendricks"},"message":"veyron_danger: EDP changes for v2\n\nEDP-related hardware modifications for v2:\n- BL_EN moved from GPIO7_A3 to GPIO7_A2\n- EDP_HPD added to GPIO7_B3\n\nBUG=none\nBRANCH=none\nTEST=built and booted Danger v2 with EDP panel attached, saw dev\nmode screen come up\n\nChange-Id: I47383610082b371a612aced656e56f1bd1cfa098\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845\nOriginal-Signed-off-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/280855\nOriginal-Reviewed-by: Julius Werner <jwerner@chromium.org>\nReviewed-on: http://review.coreboot.org/10771\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/a1e5a7761ad824ffd8449db02fec9274eb165bc2"},{"sha":"c2b48e55f1d4bd02a07515164ddcca472bf47351","author":{"email":"c9fe3c0450a180d111405ace687410d20d0d0895@rock-chips.com","name":"huang lin"},"message":"rockchip: rk3288: correct ddr 300MHz clock setting\n\nCRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz\nsetting can't meet this request, so modify it\n\nBRANCH=None\nBUG=None\nTEST=Set ddr frequency to 300MHz and boot from mickey\n\nChange-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5\nOriginal-Change-Id: I885704542293ed55e429a0b4b30135af7978990f\nOriginal-Signed-off-by: huang lin <hl@rock-chips.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282445\nOriginal-Reviewed-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Reviewed-by: Julius Werner <jwerner@chromium.org>\nReviewed-on: http://review.coreboot.org/10772\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/c2b48e55f1d4bd02a07515164ddcca472bf47351"},{"sha":"394933640bc0515617117ed0cb8de7702bc9c1bf","author":{"email":"fd5f93af191bf7e8f73ea71cc3c0f66b41b1dd49@chromium.org","name":"Daisuke Nojiri"},"message":"libpayload: arm(64): add read8/16/32 and write8/16/32\n\nThis applys the same change made by\nhttps://chromium-review.googlesource.com/261692\nto libpayload.\n\nBUG=none\nBRANCH=tot\nTEST=built for veyron_jerry, rush_ryu, samus\n\nChange-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030\nOriginal-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7\nOriginal-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282541\nOriginal-Reviewed-by: Aaron Durbin <adurbin@chromium.org>\nReviewed-on: http://review.coreboot.org/10773\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/394933640bc0515617117ed0cb8de7702bc9c1bf"},{"sha":"aa33609d289c4ee07ec10e4825bc055492fa107c","author":{"email":"5ab9cdb82979a5e22201150e8d4ff9f187271b68@rock-chips.com","name":"Yunzhi Li"},"message":"libpayload: usb: dwc2: support interrupt transfer\n\ndwc2 host core do not have a periodic schedule list, so try to send\nan interrupt packet in poll_intr_queue() function and use frame\nnumber read from usb core register to calculate time and schedule\ntransfers.\n\nBUG=None\nTEST=Tested on RK3288 with two USB keyboards(connect to SoC without\nUSB hub), both work correctly.\nBRANCH=None\n\nChange-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157\nOriginal-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777\nOriginal-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/280750\nOriginal-Reviewed-by: Julius Werner <jwerner@chromium.org>\nOriginal-Commit-Queue: Lin Huang <hl@rock-chips.com>\nOriginal-Tested-by: Lin Huang <hl@rock-chips.com>\nReviewed-on: http://review.coreboot.org/10774\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/aa33609d289c4ee07ec10e4825bc055492fa107c"},{"sha":"af42f069ea1bd8651a3e830323da27aee54290e5","author":{"email":"3b0deacc4b5357f519084f1ea34bd42bf5d34545@chromium.org","name":"David Hendricks"},"message":"rk3288: Auto-detect display.\n\nWe currently select either HDMI or EDP (default). This patch\nallows us to use HDMI as a fallback for devices that may have\na display connected on either interface. It also renames the\nenums to sound a little more sensible in other contexts (more\non that in the follow-up patches).\n\nVOP_MODE_AUTO is added to the mode enum which will make it explicit\nthat a board can support either. In AUTO_MODE we will try EDP first\nand then fallback to HDMI. Other modes can be set to force a certain\nbehavior such as HDMI-only on Mickey where it doesn't make sense to\ntry EDP.\n\nA follow-up patch will add logic for when we explicitly don't want\nto probe for any display (headless devices).\n\nBUG=none\nBRANCH=none\nTEST=On veyron_danger, connected EDP and HDMI displays and saw dev\nmode screen appear on EDP display. Unplugged EDP and then dev mode\nscreen showed up on HDMI.\n\nChange-Id: I22b38031c4ab3d79fbb182f7a906da1197f35543\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 3f57ed3758c4e516d9fd226ad9499b102b81b423\nOriginal-Change-Id: I352dcde16f7f3ebbf5796852b685685e541eb794\nOriginal-Signed-off-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/281076\nOriginal-Reviewed-by: Julius Werner <jwerner@chromium.org>\nReviewed-on: http://review.coreboot.org/10775\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/af42f069ea1bd8651a3e830323da27aee54290e5"},{"sha":"e6883a3d9b198ccc9a2fc6d724f41e689aa6d1d6","author":{"email":"3b0deacc4b5357f519084f1ea34bd42bf5d34545@chromium.org","name":"David Hendricks"},"message":"veyron_*: Set vop_mode in devicetree.cb files\n\nThis avoids any ambiguity or breakage in case the vop_modes get\nshuffled around or changed in some future patch or copy+paste job.\n\nBrain and Rialto need some more work done so their devicetree.cb\nfiles will be updated in follow-up patches.\n\nBUG=none\nBRANCH=none\nTEST=compiled only (for danger, jerry, mickey, romy, speedy)\n\nChange-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db\nOriginal-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093\nOriginal-Signed-off-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282610\nOriginal-Reviewed-by: Julius Werner <jwerner@chromium.org>\nReviewed-on: http://review.coreboot.org/10776\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/e6883a3d9b198ccc9a2fc6d724f41e689aa6d1d6"},{"sha":"d8086876a74743db2191a62c5a75e344c907143f","author":{"email":"4d12f06cff3725783b352157673a720bc67c4afe@chromium.org","name":"Julius Werner"},"message":"lzma: Return correct amount of decompressed bytes\n\nThe LZMA functions are supposed to return the decompressed size, but\nwhat they actually return is just an unaltered field from the LZMA\nheader that is *supposed* to contain the decompressed size. Apparently\nsome encoders just overshoot that for no good reason. This patch changes\nthe code such that the actual amount of decompressed bytes is returned.\n\nBRANCH=smaug\nBUG=None\nTEST=Printed output bytes when decompressing kernels with LZMA in\ndepthcharge, noted that amounts now make sense.\n\nChange-Id: Icdd8f782aa87841f770eff4c14a08973530c7446\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 24b2fa8c9a342ca4288dad1430c8965395f00263\nOriginal-Change-Id: Ib4cf8673846aedd34656e594ce7b8ea875b56099\nOriginal-Signed-off-by: Julius Werner <jwerner@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282742\nOriginal-Reviewed-by: Stefan Reinauer <reinauer@google.com>\nOriginal-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>\nReviewed-on: http://review.coreboot.org/10777\nTested-by: build bot (Jenkins)\nReviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/d8086876a74743db2191a62c5a75e344c907143f"},{"sha":"51e73c3f6ef6622812e6c8b0b929a157745f11d5","author":{"email":"3b0deacc4b5357f519084f1ea34bd42bf5d34545@chromium.org","name":"David Hendricks"},"message":"veyron_brain: Add basic HDMI support\n\nThis adds a configure_hdmi() function that drives the HDMI\nenable output high and configures the iomux. Calls to PMIC\nfunctions to enable HDMI power are moved here as well.\n\nBUG=none\nBRANCH=none\nTEST=with follow-up patches, we now get a dev screen on Brain.\n\nChange-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013\nOriginal-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e\nOriginal-Signed-off-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282046\nReviewed-on: http://review.coreboot.org/10778\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>\nReviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/51e73c3f6ef6622812e6c8b0b929a157745f11d5"},{"sha":"cc828514ce9d571e01b03efea8fcb33637a44723","author":{"email":"3b0deacc4b5357f519084f1ea34bd42bf5d34545@chromium.org","name":"David Hendricks"},"message":"rk3288: Add VOP_MODE_NONE for headless devices\n\nBUG=none\nBRANCH=none\nTEST=built w/ follow-up rialto patch\n\nChange-Id: I166c75673c199e8c6860f601db6759cdc3cb9c96\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: ba0e0b639f12654ec54216d4366c688baa5b3253\nOriginal-Change-Id: Id21c87ace2f4d381a1e374e1d5fe15cf1cd96da0\nOriginal-Signed-off-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282047\nReviewed-on: http://review.coreboot.org/10779\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/cc828514ce9d571e01b03efea8fcb33637a44723"},{"sha":"5bcf8d637becc29aaaf2ed1797e6fe89bf1c07f8","author":{"email":"6be5c96c464778f89679b1062a2e0a6af93d2aa5@google.com","name":"Furquan Shaikh"},"message":"t210: MTC cleanup\n\n1. Correct MTC weak function definitions.\n2. Correct MTC message in case no training data is present.\n\nBUG=None\nBRANCH=None\nTEST=Compiles successfully and boots to kernel prompt on smaug.\n\nChange-Id: Iba3c994982da947af3fbd2d7e9a06dff7947f2b9\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: ce9a4cd7d824acd0da5615b33319869f6cf1cd56\nOriginal-Change-Id: I037439246709c8ec0ec7f12ea109cbe0ae1073ae\nOriginal-Signed-off-by: Furquan Shaikh <furquan@google.com>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/278027\nOriginal-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>\nOriginal-Tested-by: Furquan Shaikh <furquan@chromium.org>\nOriginal-Reviewed-by: Tom Warren <twarren@nvidia.com>\nOriginal-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>\nOriginal-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Queue: Furquan Shaikh <furquan@chromium.org>\nReviewed-on: http://review.coreboot.org/10780\nReviewed-by: Furquan Shaikh <furquan@google.com>\nTested-by: build bot (Jenkins)","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/5bcf8d637becc29aaaf2ed1797e6fe89bf1c07f8"},{"sha":"e0a8a88912031feba7f69fe1a7bdfe4c9bda1867","author":{"email":"fd5f93af191bf7e8f73ea71cc3c0f66b41b1dd49@chromium.org","name":"Daisuke Nojiri"},"message":"update common base header files\n\nIS_ENABLED is defined in kconfig.h, thus, should be included in\nlibpayload.h.\n\nBUG=none\nBRANCH=tot\nTEST=built coreboot/libpayload for veyron_jerry\n\nChange-Id: I9c5879b6125ac66a75a507ab07a6816ab54ed0ba\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 51dcd58a841009081fdefcadf9aa74286152dde6\nOriginal-Change-Id: I30e6d87c9de827a214a6100449cd716e773c2ba3\nOriginal-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282587\nOriginal-Reviewed-by: Randall Spangler <rspangler@chromium.org>\nReviewed-on: http://review.coreboot.org/10781\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/e0a8a88912031feba7f69fe1a7bdfe4c9bda1867"},{"sha":"3740546bd849755f6c8a74634e34447e9a31d358","author":{"email":"fd5f93af191bf7e8f73ea71cc3c0f66b41b1dd49@chromium.org","name":"Daisuke Nojiri"},"message":"sysinfo: remove unused tag for struct spi_flash\n\nThis will conflict with struct spi_flash defined in spi_flash.h\n\nBUG=none\nBRANCH=tot\nTEST=built libpayload for veyron jerry\n\nChange-Id: I7e1be28cf430021944fc96890082a0704d093e9f\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 0f0b8a7ec114046335fb1a51b6a92e10e5a16520\nOriginal-Change-Id: I6d4f8a8e93aeb055f7dd6e5e8fd5e6c6153ab837\nOriginal-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282588\nOriginal-Reviewed-by: Randall Spangler <rspangler@chromium.org>\nReviewed-on: http://review.coreboot.org/10782\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/3740546bd849755f6c8a74634e34447e9a31d358"},{"sha":"9150e5e0f26a1f2908d8ab95c2f82e3ccad423dc","author":{"email":"fd5f93af191bf7e8f73ea71cc3c0f66b41b1dd49@chromium.org","name":"Daisuke Nojiri"},"message":"cbfs: define libpayload_init_default_cbfs_media weakly\n\nTo allow a payload to define its own libpayload_init_default_cbfs_media,\ndefault implementation needs to be defined weakly.\n\nBUG=none\nBRANCH=tot\nTEST=dumped a cbfs file from depthcharge cli on jerry\n\nChange-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352\nOriginal-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83\nOriginal-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/283061\nOriginal-Reviewed-by: Aaron Durbin <adurbin@chromium.org>\nReviewed-on: http://review.coreboot.org/10783\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/9150e5e0f26a1f2908d8ab95c2f82e3ccad423dc"},{"sha":"cd500134b18fd579dd912df0a3c227458935d4fe","author":{"email":"3b0deacc4b5357f519084f1ea34bd42bf5d34545@chromium.org","name":"David Hendricks"},"message":"veyron_rialto: Use VOP_MODE_NONE for display init.\n\nThis uses VOP_MODE_NONE for display init on veyron_rialto and\nadds a mainboard_power_on_backlight() stub so that we can finally\nget rid of SKIP_DISPLAY_INIT_HACK.\n\nBUG=none\nBRANCH=none\nTEST=built for veyron_rialto\n\nChange-Id: Ia6b420a962fe266e773c804b8e5c68da35848753\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d\nOriginal-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43\nOriginal-Signed-off-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282048\nReviewed-on: http://review.coreboot.org/10784\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/cd500134b18fd579dd912df0a3c227458935d4fe"},{"sha":"1f440f60fbc99050ef24fe94b539564c93e56678","author":{"email":"3b0deacc4b5357f519084f1ea34bd42bf5d34545@chromium.org","name":"David Hendricks"},"message":"veyron*: Kill SKIP_DISPLAY_INIT_HACK\n\nNow that we have functioning display code for all platforms,\nwe can just get rid of this ugly hack used on non-Chromebook\nveyrons.\n\nBUG=none\nBRANCH=none\nTEST=built for Brain, Rialto, Mickey, Romy\n\nChange-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5\nSigned-off-by: Patrick Georgi <pgeorgi@chromium.org>\nOriginal-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5\nOriginal-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3\nOriginal-Signed-off-by: David Hendricks <dhendrix@chromium.org>\nOriginal-Reviewed-on: https://chromium-review.googlesource.com/282049\nOriginal-Reviewed-by: Julius Werner <jwerner@chromium.org>\nReviewed-on: http://review.coreboot.org/10785\nTested-by: build bot (Jenkins)\nReviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>\nReviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/1f440f60fbc99050ef24fe94b539564c93e56678"}]}