{"push_id":693903329,"size":3,"distinct_size":3,"ref":"refs/heads/master","head":"5affdb04be568e50b3a77107a87664924702fd20","before":"9435afa5dc9dadf98bea5040c8ce8a4c087134a0","commits":[{"sha":"9410e081423ebdfe64ee92905fba201c5d364aa7","author":{"email":"094212ffe4b4057b260622a8880ccf5efb2ff766@multicorewareinc.com","name":"Dnyaneshwar G"},"message":"asm: 10bpp avx2 code for intra_pred_ang32x32 mode 11 & 25\n\nperformance improvement over SSE:\nintra_ang_32x32[11]    8256c->4236c, 48%\nintra_ang_32x32[25]    5646c->2755c, 51%","distinct":true,"url":"https://api.github.com/repos/videolan/x265/commits/9410e081423ebdfe64ee92905fba201c5d364aa7"},{"sha":"33130b4269874996f910143741f1ae339570a20f","author":{"email":"094212ffe4b4057b260622a8880ccf5efb2ff766@multicorewareinc.com","name":"Dnyaneshwar G"},"message":"asm: 10bpp avx2 code for intra_pred_ang32x32 mode 12 & 24\n\nperformance improvement over SSE:\nintra_ang_32x32[12]    8084c->4584c, 43%\nintra_ang_32x32[24]    5629c->2934c, 48%","distinct":true,"url":"https://api.github.com/repos/videolan/x265/commits/33130b4269874996f910143741f1ae339570a20f"},{"sha":"5affdb04be568e50b3a77107a87664924702fd20","author":{"email":"6aa0e0056fab6c36b3040c05d33e2e0413746609@multicorewareinc.com","name":"Aasaipriya Chandran"},"message":"asm: avx2 interp_8tap_hv_pp for 8bpp\n\nRemoving x265_interp_8tap_hv_pp_16x16_avx2 seperate asm code, since its giving same performnace as calling interp_8tap_hv_pp_cpu C function(which calls luma_hps and luma_vsp asm functions individually)\n\nIncluding ALL_LUMA_PU_T for luma_hvpp which calls interp_8tap_hv_pp_cpu C function.\nALL_LUMA_PU_T has declared all sizes except 4x4, hence including luma_hvpp[4x4] separately.","distinct":true,"url":"https://api.github.com/repos/videolan/x265/commits/5affdb04be568e50b3a77107a87664924702fd20"}]}