{"push_id":869719839,"size":64,"distinct_size":64,"ref":"refs/heads/master","head":"4db6dc51b048994a891f983f192b44792305d595","before":"4d60f67763b08c19335b29e96a61ad4cbce034d9","commits":[{"sha":"96902bf6e3e4386650908541a13e084bceb79850","author":{"email":"6b31706989f3cf9466bfddbf48eab0c43e646ba8@gmail.com","name":"Rafael Espindola"},"message":"Add MemoryBufferRef(MemoryBuffer&) constructor.\n\npatch by Jonathan Anderson!\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253311 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/96902bf6e3e4386650908541a13e084bceb79850"},{"sha":"485ed67da51dbb52c94b78eaa6f24303269cb29b","author":{"email":"ceadf621e01489dc9705a269a331fb3c9fbbaef3@imgtec.com","name":"Zlatko Buljan"},"message":"Added microMIPSDSPr1 assembler and disassembler tests to existing microMIPSDSPr2 test files.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253320 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/485ed67da51dbb52c94b78eaa6f24303269cb29b"},{"sha":"4ea617263b3dc9298ed21c25c5ef3b0a3798eab9","author":{"email":"bce72489011e5753569f2110bd524579066fa193@intel.com","name":"Igor Breger"},"message":"AVX512 : regenerate the test file against trunk.\n\nDifferential Revision: http://reviews.llvm.org/D14742\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253321 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/4ea617263b3dc9298ed21c25c5ef3b0a3798eab9"},{"sha":"a56e1d65adf14de4cd62dc11e5b4c4fc4deac60f","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"Fix a typo in BasicAliasAnalysis\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253322 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/a56e1d65adf14de4cd62dc11e5b4c4fc4deac60f"},{"sha":"bef6034cc2b3c10c7762d8aa7831bf4b44d56854","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"[AliasAnalysis] CatchPad and CatchRet can modify escaped memory\n\nCatchPad and CatchRet behave a lot like function calls: they can\npotentially modify any memory which has been escaped.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253323 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/bef6034cc2b3c10c7762d8aa7831bf4b44d56854"},{"sha":"6c42346ff43d1058a174a7a28595d4f3528445cf","author":{"email":"91e3633c38bc6fd718df7399f7dc1021ae7646ee@gmail.com","name":"Jay Foad"},"message":"Fix typos in comments.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253324 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/6c42346ff43d1058a174a7a28595d4f3528445cf"},{"sha":"e0d7dbe7db6ac2b56f6610137583e23cfaba37b7","author":{"email":"ceadf621e01489dc9705a269a331fb3c9fbbaef3@imgtec.com","name":"Zlatko Buljan"},"message":"[mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions\nDifferential Revision: http://reviews.llvm.org/D14279\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253326 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/e0d7dbe7db6ac2b56f6610137583e23cfaba37b7"},{"sha":"43f1dd7a0084daba57a9f791cfad74d0667d2307","author":{"email":"94cff2ce4b0d642d902b3e53b6d230493f404544@arm.com","name":"Oliver Stannard"},"message":"[Assembler] Allow non-fatal errors after parsing\n\nThis adds reportError to MCContext, which can be used as an alternative to\nreportFatalError when the assembler wants to try to continue processing the\nrest of the file after the error is reported, so that all of the errors ina\nfile can be reported. It records the fact that an error was encountered, so we\ncan avoid emitting an object file if any errors occurred.\n\nThis patch doesn't add any uses of this function (a later patch will convert\nmost uses of reportFatalError to use it), but there is a small functional\nchange: we use the SourceManager to print the error message, even if we have a\nnull SMLoc. This means that we get a SourceManager-style message, with the file\nand line information shown as <unknown>, rather than the \"LLVM ERROR\" style\nused by report_fatal_error.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253327 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/43f1dd7a0084daba57a9f791cfad74d0667d2307"},{"sha":"99ab11202f6fd4905def11e75f260d487a589f9c","author":{"email":"94cff2ce4b0d642d902b3e53b6d230493f404544@arm.com","name":"Oliver Stannard"},"message":"[Assembler] Make fatal assembler errors non-fatal\n\nCurrently, if the assembler encounters an error after parsing (such as an\nout-of-range fixup), it reports this as a fatal error, and so stops after the\nfirst error. However, for most of these there is an obvious way to recover\nafter emitting the error, such as emitting the fixup with a value of zero. This\nmeans that we can report on all of the errors in a file, not just the first\none. MCContext::reportError records the fact that an error was encountered, so\nwe won't actually emit an object file with the incorrect contents.\n\nDifferential Revision: http://reviews.llvm.org/D14717\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253328 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/99ab11202f6fd4905def11e75f260d487a589f9c"},{"sha":"affe4356e9e66c1291258f90ad0359a5d2162a12","author":{"email":"ceadf621e01489dc9705a269a331fb3c9fbbaef3@imgtec.com","name":"Zlatko Buljan"},"message":"[mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions\nDifferential Revision: http://reviews.llvm.org/D14114\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253329 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/affe4356e9e66c1291258f90ad0359a5d2162a12"},{"sha":"38bd0daf4d15082c71160dfc13a119b6e2d1fc19","author":{"email":"f0ffa6f967f90214e3dddd44a9618a10ee27acfa@arm.com","name":"Bradley Smith"},"message":"[ARM] Properly initialize ARMArch in the ARM subtarget\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253331 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/38bd0daf4d15082c71160dfc13a119b6e2d1fc19"},{"sha":"3a6c5daba9637910d531600cda21cf662e17d6fc","author":{"email":"ceadf621e01489dc9705a269a331fb3c9fbbaef3@imgtec.com","name":"Zlatko Buljan"},"message":"[mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions\nDifferential Revision: http://reviews.llvm.org/D14174\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253332 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/3a6c5daba9637910d531600cda21cf662e17d6fc"},{"sha":"377cc21860b673e2a34fde23e8871578bf201e36","author":{"email":"668fee4df0f19a4cdadb88bb7cf11ae1d9674c1f@arm.com","name":"Charlie Turner"},"message":"[ARM] Match VABDL from log2 shuffles.\n\nDifferential Revision: http://reviews.llvm.org/D14664\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253334 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/377cc21860b673e2a34fde23e8871578bf201e36"},{"sha":"50827137f2139a6dbd3c7f74692a819cfac25a1f","author":{"email":"f0ffa6f967f90214e3dddd44a9618a10ee27acfa@arm.com","name":"Bradley Smith"},"message":"[ARM] Default to ARMv4t in favour of adding Other to ARMArch\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253335 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/50827137f2139a6dbd3c7f74692a819cfac25a1f"},{"sha":"08e6ab9d252aa0140800f45672bb2c8c57fb3ade","author":{"email":"f939b98ebdb1b556bd21d42c021221cb2cbb4d27@codeaurora.org","name":"Chad Rosier"},"message":"Typo.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253336 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/08e6ab9d252aa0140800f45672bb2c8c57fb3ade"},{"sha":"7673d242f73b19a7f5f011c9a1679f46ddf8de2a","author":{"email":"71eab3ed3d51db0f4cf11b125aa0a655cfc1b887@gmail.com","name":"Dan Gohman"},"message":"Use TargetRegisterInfo for printing MachineOperand register comments\n\nSeveral places in AsmPrinter.cpp print comments describing MachineOperand\nregisters using MCRegisterInfo, which uses MCOperand-oriented names. This\ndoesn't work for targets that use virtual registers exclusively, as\nWebAssembly does, since virtual registers are represented and printed\ndifferently.\n\nThis patch preserves what seems to be the spirit of r229978, avoiding the\nuse of TM.getSubtargetImpl(), while still using MachineOperand-oriented\nprinting for MachineOperands.\n\nDifferential Revision: http://reviews.llvm.org/D14709\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253338 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/7673d242f73b19a7f5f011c9a1679f46ddf8de2a"},{"sha":"4d186a129b13aab048e427c7f0cb64903e6e2d83","author":{"email":"6566d4ac644d552ecc4d7a106c3806f21b7ba0aa@microsoft.com","name":"Pat Gavlin"},"message":"Lower statepoints with multi-def targets.\n\nStatepoint lowering currently expects that the target method of a\nstatepoint only defines a single value. This precludes using\nstatepoints with ABIs that return values in multiple registers\n(e.g. the SysV AMD64 ABI). This change adds support for lowering\nstatepoints with mutli-def targets.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253339 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/4d186a129b13aab048e427c7f0cb64903e6e2d83"},{"sha":"8dc1efba5877e8332a425071dcd68bca397e86a0","author":{"email":"71eab3ed3d51db0f4cf11b125aa0a655cfc1b887@gmail.com","name":"Dan Gohman"},"message":"Update DebugInfo tests for the change in DEBUG_VALUE output in r253338.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253340 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/8dc1efba5877e8332a425071dcd68bca397e86a0"},{"sha":"fa084bd00c2affb7b94766f2e5b06b953e959ab8","author":{"email":"1cd424918902c1dbc16c61ea09f30b31f6c2f0e9@freebsd.org","name":"Davide Italiano"},"message":"[JIT/Memory] Fix up semantic of setExecutable().\n\nsetExecutable() should do everything that's needed to make the memory\nexecutable on host, i.e. unconditionally set permissions + invalidate\ninstruction cache. llvm-rtdyld will be updated in my next commit.\n\nDiscusseed with: Lang Hames (as part of D13631).\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253341 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/fa084bd00c2affb7b94766f2e5b06b953e959ab8"},{"sha":"a17892dba0312a9bcd27938cf99bc32da1203cd7","author":{"email":"1cd424918902c1dbc16c61ea09f30b31f6c2f0e9@freebsd.org","name":"Davide Italiano"},"message":"[llvm-rtdyld] Don't waste cycles invalidating instruction cache.\n\nNow that setExecutable() changed to do all the ground work to make\nmemory executable on the host, we can remove all (redundant) calls\nto invalidate instruction cache here.\n\nAs an added bonus, this makes invalidateInstructionCache() dead\ncode, so it can be removed.\n\nDifferential Revision:\thttp://reviews.llvm.org/D13631\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253343 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/kraj/llvm/commits/a17892dba0312a9bcd27938cf99bc32da1203cd7"}]}