{"action":"created","issue":{"url":"https://api.github.com/repos/lawrancej/logisim/issues/10","labels_url":"https://api.github.com/repos/lawrancej/logisim/issues/10/labels{/name}","comments_url":"https://api.github.com/repos/lawrancej/logisim/issues/10/comments","events_url":"https://api.github.com/repos/lawrancej/logisim/issues/10/events","html_url":"https://github.com/lawrancej/logisim/issues/10","id":19793235,"number":10,"title":"Import/Export to Verilog/VHDL","user":{"login":"lawrancej","id":600809,"avatar_url":"https://avatars.githubusercontent.com/u/600809?v=3","gravatar_id":"","url":"https://api.github.com/users/lawrancej","html_url":"https://github.com/lawrancej","followers_url":"https://api.github.com/users/lawrancej/followers","following_url":"https://api.github.com/users/lawrancej/following{/other_user}","gists_url":"https://api.github.com/users/lawrancej/gists{/gist_id}","starred_url":"https://api.github.com/users/lawrancej/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/lawrancej/subscriptions","organizations_url":"https://api.github.com/users/lawrancej/orgs","repos_url":"https://api.github.com/users/lawrancej/repos","events_url":"https://api.github.com/users/lawrancej/events{/privacy}","received_events_url":"https://api.github.com/users/lawrancej/received_events","type":"User","site_admin":false},"labels":[{"url":"https://api.github.com/repos/lawrancej/logisim/labels/enhancement","name":"enhancement","color":"84b6eb"}],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":4,"created_at":"2013-09-20T02:56:27Z","updated_at":"2015-12-27T02:48:08Z","closed_at":null,"body":"Logisim cannot play nicely with other formats for describing circuits. It should support exporting and importing Verilog or VHDL code, using comments to annotate placement of components.\r\n\r\nThere's already some code for [exporting to Verilog](http://msdl.cs.mcgill.ca/people/naomi/Research). It'd be good to see if this still works, and if so, try it out with [Icarus Verilog](http://iverilog.icarus.com/).\r\n\r\nFor VHDL, there's [GHDL](http://gna.org/projects/ghdl/)"},"comment":{"url":"https://api.github.com/repos/lawrancej/logisim/issues/comments/167376097","html_url":"https://github.com/lawrancej/logisim/issues/10#issuecomment-167376097","issue_url":"https://api.github.com/repos/lawrancej/logisim/issues/10","id":167376097,"user":{"login":"chibill","id":2133449,"avatar_url":"https://avatars.githubusercontent.com/u/2133449?v=3","gravatar_id":"","url":"https://api.github.com/users/chibill","html_url":"https://github.com/chibill","followers_url":"https://api.github.com/users/chibill/followers","following_url":"https://api.github.com/users/chibill/following{/other_user}","gists_url":"https://api.github.com/users/chibill/gists{/gist_id}","starred_url":"https://api.github.com/users/chibill/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/chibill/subscriptions","organizations_url":"https://api.github.com/users/chibill/orgs","repos_url":"https://api.github.com/users/chibill/repos","events_url":"https://api.github.com/users/chibill/events{/privacy}","received_events_url":"https://api.github.com/users/chibill/received_events","type":"User","site_admin":false},"created_at":"2015-12-27T02:48:08Z","updated_at":"2015-12-27T02:48:08Z","body":"Any progress on this idea."}}