{"push_id":815381548,"size":25,"distinct_size":0,"ref":"refs/heads/master-next","head":"6e21224a35c2ec236df45e1bd2469b0c9d659ba9","before":"80de3c807939e2ef7d03def17c569421264bf0d7","commits":[{"sha":"805b88c0bdad62f8647b4b94c4f68864cd30c488","author":{"email":"cddab1f837c400ff9c3b002761e2cb74669ec6d1@xilinx.com","name":"Christian Kohn"},"message":"v4l: subdev: add compat_ioctl32, otherwise arm64 compilation fails\n\nSigned-off-by: Christian Kohn <christian.kohn@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/805b88c0bdad62f8647b4b94c4f68864cd30c488"},{"sha":"340f285d9322b24778cbea3940187ad8c525f33f","author":{"email":"852ef8128b42a63613e8b59bfc81e54a2a35ad7a@xilinx.com","name":"Subbaraya Sundeep Bhatta"},"message":"usb: phy: Add platform driver support for ULPI phys\n\nModified to add platform driver support to ULPI phys.\n\nSigned-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/340f285d9322b24778cbea3940187ad8c525f33f"},{"sha":"1f9586a82eb932e7040e33d66ffb980737b3d16d","author":{"email":"852ef8128b42a63613e8b59bfc81e54a2a35ad7a@xilinx.com","name":"Subbaraya Sundeep Bhatta"},"message":"usb: chipidea: Use usb2 phy for Zynq platform\n\nAdd usb2 phy to Zynq platform data.\n\nSigned-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/1f9586a82eb932e7040e33d66ffb980737b3d16d"},{"sha":"7be1ce169687f4e3ccbfe87459dc20c12f558a3a","author":{"email":"852ef8128b42a63613e8b59bfc81e54a2a35ad7a@xilinx.com","name":"Subbaraya Sundeep Bhatta"},"message":"usb: chipidea: Add support for VBUS control with PHY\n\nSome platforms make use of VBUS control over PHY which\nmeans controller driver has to access PHY registers to\nturn on/off VBUS line.This patch adds support for\nsuch platforms in chipidea.\n\nSigned-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/7be1ce169687f4e3ccbfe87459dc20c12f558a3a"},{"sha":"fe9996a37df353853f9773d173346f25f88b8f21","author":{"email":"852ef8128b42a63613e8b59bfc81e54a2a35ad7a@xilinx.com","name":"Subbaraya Sundeep Bhatta"},"message":"ARM: zynq: defconfig: Enable ULPI PHYs for Zynq\n\nThis patch enables:\n\tULPI PHYs for Zynq USB controllers\n\tOTG state machine\n\tMass storage gadget\n\nSigned-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/fe9996a37df353853f9773d173346f25f88b8f21"},{"sha":"54fea6456754d64f0cc17efec0d2a222dfc399e6","author":{"email":"852ef8128b42a63613e8b59bfc81e54a2a35ad7a@xilinx.com","name":"Subbaraya Sundeep Bhatta"},"message":"ARM: dts: zynq: Add ULPI phys instead of NOP transceivers\n\nZynq USB controller needs explicit access to ULPI PHY registers\nso ULPI PHY node is used instead of NOP node.\n\nSigned-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/54fea6456754d64f0cc17efec0d2a222dfc399e6"},{"sha":"d0da3a052ad94286606bdbc8a7041625beb8bd07","author":{"email":"c01a8c815a4ad165fff2d1c0d35ddf5b16bd3d7b@freescale.com","name":"Peter Chen"},"message":"usb: chipidea: add identification registers access APIs\n\nUsing hw_write_id_reg and hw_read_id_reg to write and read identification\nregisters contents, they can be used to get controller information, change\nsome system configurations, and so on.\n\nReviewed-by: Stefan Agner <stefan@agner.ch>\nSigned-off-by: Peter Chen <peter.chen@freescale.com>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/d0da3a052ad94286606bdbc8a7041625beb8bd07"},{"sha":"fa956cd66cee0170521e4599ea30465db4ad93ea","author":{"email":"852ef8128b42a63613e8b59bfc81e54a2a35ad7a@xilinx.com","name":"Subbaraya Sundeep Bhatta"},"message":"usb: chipidea: add chipidea revision information\n\nDefine ci_get_revision API to know the controller revision\ninformation according to chipidea 1.1a, 2.0a and 2.5a spec.\nBesides, add one entry at struct ci_hdrc to indicate revision\ninformation, it can be used for adding different code for\nrevisions, eg kinds of errata.\n\nSigned-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/fa956cd66cee0170521e4599ea30465db4ad93ea"},{"sha":"99e5d829103e63180eab9d5920b41b7991caccbf","author":{"email":"729782c736785f3c610b2ccb0320baaeca32a38f@gmail.com","name":"Sanchayan Maity"},"message":"usb: chipidea: Add errata for revision 2.40a\n\nAt chipidea revision 2.40a, there is a below errata:\n\n9000531823  B2-Medium  Adding a dTD to a Primed Endpoint May Not Get Recognized\n\nTitle: Adding a dTD to a Primed Endpoint May Not Get Recognized\n\nImpacted Configuration: All device mode configurations.\n\nDescription:\nThere is an issue with the add dTD tripwire semaphore (ATDTW bit in USBCMD register)\nthat can cause the controller to ignore a dTD that is added to a primed endpoint.\nWhen this happens, the software can read the tripwire bit and the status bit at '1'\neven though the endpoint is unprimed.\n\nAfter executing a dTD, the device controller endpoint state machine executes a final\nread of the dTD terminate bit to check if the application added a dTD to the linked\nlist at the last moment. This read is done in the finpkt_read_latest_next_td (44) state.\nAfter the read is performed, if the terminate bit is still set, the state machine moves\nto unprime the endpoint. The decision to unprime the endpoint is done in the\ncheckqh_decision (59) state, based on the value of the terminate bit.\nBefore reaching the checkqh_decision state, the state machine traverses the\nwriteqhtd_status (57), writeqh_status (56), and release_prime_mask (42) states.\nAs shown in the waveform, the ep_addtd_tripwire_clr signal is not set to clear\nthe tripwire bit in these states.\n\nWorkaround:\nThe software must implement a periodic poll cycle, and check for each dTD\npending on execution (Active = 1), if the enpoint is primed. It can do this by reading\nthe corresponding bits in the ENDPTPRIME and ENDPTSTAT registers. If these bits are\nread at 0, the software needs to re-prime the endpoint by writing 1 to the corresponding\nbit in the ENDPTPRIME register. This can be done for every microframe, every frame or\nwith a larger interval, depending on the urgency of transfer execution for the application.\n\nTested-by: Stefan Agner <stefan@agner.ch>\nSigned-off-by: Peter Chen <peter.chen@freescale.com>\nSigned-off-by: Sanchayan Maity <maitysanchayan@gmail.com>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/99e5d829103e63180eab9d5920b41b7991caccbf"},{"sha":"496744dd3c645583717697489b88416b7a32012a","author":{"email":"852ef8128b42a63613e8b59bfc81e54a2a35ad7a@xilinx.com","name":"Subbaraya Sundeep Bhatta"},"message":"usb: chipidea: Make errata apllicable for all revisions\n\nThis patch removes check for controller version and makes\nerrata fix applicable for all revisions.\n\nSigned-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/496744dd3c645583717697489b88416b7a32012a"},{"sha":"4c16a042d880821d9b5a007eb6a42098a8dce6c9","author":{"email":"f774d01c6448567a362c0a8f043dfc5105e95890@xilinx.com","name":"Punnaiah Choudary Kalluri"},"message":"net: macb: Enable SG mode support for zynq\n\nSince zynq ethernet controller supports scatter gather IO, Enabling\nthis feature for zynq.\n\nSigned-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/4c16a042d880821d9b5a007eb6a42098a8dce6c9"},{"sha":"1e7a09e10543ec4812f0438058864cbaf0b27f4f","author":{"email":"a0d963800e63a77fef2415988ce56bb5b410af41@xilinx.com","name":"Harini Katakam"},"message":"net: macb: Merge mainline changes related to jumbo frames\n\nIn mainline kernel, jumbo frame selection is done by adding capabilities\nand corresponding max jumbo length in a new zynqmp config entry.\nReflect the same and other minor style changes to be in sync with mainline.\n\nSigned-off-by: Harini Katakam <harinik@xilinx.com>\nReviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/1e7a09e10543ec4812f0438058864cbaf0b27f4f"},{"sha":"f3ad0c4ffd3f20dc0604a9c805768d818ff839df","author":{"email":"a0d963800e63a77fef2415988ce56bb5b410af41@xilinx.com","name":"Harini Katakam"},"message":"net: macb: Add support for extended BD with a config option\n\nCadence GEM supports extended buffer descriptors.\nThis patch adds a config option to enable use of extended BD.\nThis adds two extra words to the TX BD and RX BD by configuring the\nnecessary registers. Corresponding variables are added to the\nmacb_dma_desc structure.\n\nSigned-off-by: Harini Katakam <harinik@xilinx.com>\nReviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/f3ad0c4ffd3f20dc0604a9c805768d818ff839df"},{"sha":"8fddb0b6216d174a750424440944cad639b80247","author":{"email":"a0d963800e63a77fef2415988ce56bb5b410af41@xilinx.com","name":"Harini Katakam"},"message":"net: macb: Add support for 1588 for Zynq Ultrascale+ MPSoC\n\nCadence GEM in Zynq Ultrascale+ MPSoC supports 1588 and provides a\n102 bit time counter with 48 bits for seconds, 30 bits for nsecs and\n24 bits for sub-nsecs. The timestamp is made available to the SW through\nregisters as well as (more precisely) through upper two words in\nan extended BD.\n\nThis patch does the following:\n- Adds MACB_CAPS_TSU in zynqmp_config.\n- Registers to ptp clock framework (after checking for timestamp support in\n  IP and capability in config).\n- TX BD and RX BD control registers are written to populate timestamp in\n  extended BD words.\n- Timer initialization is done by writing time of day to the timer counter.\n- ns increment register is programmed as NS_PER_SEC/TSU_CLK.\n  For a 24 bit subns precision, the subns increment equals\n  remainder of (NS_PER_SEC/TSU_CLK) * (2^24).\n  TSU (Time stamp unit) clock is obtained by the  driver from devicetree.\n- HW time stamp capabilities are advertised via ethtool and macb ioctl is\n  updated accordingly.\n- For all PTP event frames, nanoseconds and the lower 5 bits of seconds are\n  obtained from the BD. This offers a precise timestamp. The upper bits\n  (which dont vary between consecutive packets) are obtained from the\n  TX/RX PTP event/PEER registers. The timestamp obtained thus is updated\n  in skb for upper layers to access.\n- The drivers register functions with ptp to perform time and frequency\n  adjustment.\n- Time adjustment is done by writing to the 1558_ADJUST register.\n  The controller will read the delta in this register and update the timer\n  counter register. Alternatively, for large time offset adjustments,\n  the driver reads the secs and nsecs counter values, adds/subtracts the\n  delta and updates the timer counter. In order to be as precise as possible,\n  nsecs counter is read again if secs has incremented during the counter read.\n- Frequency adjustment is not directly supported by this IP.\n  addend is the initial value ns increment and similarly addendesub.\n  The ppb (parts per billion) provided is used as\n  ns_incr = addend +/- (ppb/rate).\n  Similarly the remainder of the above is used to populate subns increment.\n  In case the ppb requested is negative AND subns adjustment greater than\n  the addendsub, ns_incr is reduced by 1 and subns_incr is adjusted in\n  positive accordingly.\n\nSigned-off-by: Harini Katakam <harinik@xilinx.com>\nReviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/8fddb0b6216d174a750424440944cad639b80247"},{"sha":"830655f3ae7fbb09c875b52e80df4d40af740ac2","author":{"email":"a0d963800e63a77fef2415988ce56bb5b410af41@xilinx.com","name":"Harini Katakam"},"message":"devicetree: Add compatible string for Zynq Ultrascale+ MPSoC\n\nAdd \"cdns,zynqmp-gem\" to be used for Zynq Ultrascale+ MPSoC.\n\nSigned-off-by: Harini Katakam <harinik@xilinx.com>\nReviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/830655f3ae7fbb09c875b52e80df4d40af740ac2"},{"sha":"2c15ec7e32052f2aafcb305953802242ec9cae65","author":{"email":"a0d963800e63a77fef2415988ce56bb5b410af41@xilinx.com","name":"Harini Katakam"},"message":"devicetree: macb: Add optional property tsu-clk\n\nAdd TSU clock frequency to be used for 1588 support in macb driver.\n\nSigned-off-by: Harini Katakam <harinik@xilinx.com>\nReviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/2c15ec7e32052f2aafcb305953802242ec9cae65"},{"sha":"718784a01910710d2bb3c5aaa5374a1d379a96a8","author":{"email":"9bacd21e47fc2ddea630100ed3197df31a57b144@xilinx.com","name":"Kedareswara rao Appana"},"message":"net: phy: Use proper duplex settings for SGMII case\n\nThe duplex setting is not set by the Xilinx phy driver\nWhich causes issues such that SGMII won't switch rates.\nWhen the duplex is not set it is a value of -1 which then messes\nUp the adjust_link() function in the driver as -1 is 0xFFFFFFFF\nWhich than causes it not to see any link state change.\n\nReported-by: John Linn <john.linn@xilinx.com>\nSigned-off-by: Kedareswara rao Appana <appanad@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/718784a01910710d2bb3c5aaa5374a1d379a96a8"},{"sha":"e35cbad62bce8710bf74b91b78f4931d83e711de","author":{"email":"9bacd21e47fc2ddea630100ed3197df31a57b144@xilinx.com","name":"Kedareswara rao Appana"},"message":"net: ethernet: xilinx: Fix issues with the optional phy_type property\n\nThe xlnx,phy-type is a optional DT property.\nIf it is not specified in the device tree then it defaults to 0\nWhich is the value for XAE_PHY_TYPE_MII which then causes an error\nWhen trying to switch from 10/100 to 1000 when in SGMII mode.\n\nReported-by: John Linn <john.linn@xilinx.com>\nSigned-off-by: Kedareswara rao Appana <appanad@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/e35cbad62bce8710bf74b91b78f4931d83e711de"},{"sha":"332aa92529748c9ffae5fee8d6bc3ff2b1656d59","author":{"email":"9bacd21e47fc2ddea630100ed3197df31a57b144@xilinx.com","name":"Kedareswara rao Appana"},"message":"net: ethernet: xilinx: Update link state change properly in the driver\n\nThe last link state in the driver in adjust_link() was not being updated unless\nThere was the speed was set which could then cause the mac speed error message\nForever at a periodic rate.This patch fixes this issue.\n\nReported-by: John Linn <john.linn@xilinx.com>\nSigned-off-by: Kedareswara rao Appana <appanad@xilinx.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/332aa92529748c9ffae5fee8d6bc3ff2b1656d59"},{"sha":"88089552f5ed51a20f22c6239b5ba12f0f567b72","author":{"email":"59190c1867e3222b932a0de3c668eb2d980d69a2@gmail.com","name":"Florian Fainelli"},"message":"net: phy: Add phy_interface_is_rgmii helper\n\nRGMII interfaces come in 4 different flavors that the PHY library needs\nto care about: regular RGMII (no delays), RGMII with either RX or TX\ndelay, and both. In order to avoid errors of checking only for one type\nof RGMII interface and miss the 3 others, introduce a convenience\nfunction which tests for all values.\n\nSuggested-by: David S. Miller <davem@davemloft.net>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/Xilinx/linux-xlnx/commits/88089552f5ed51a20f22c6239b5ba12f0f567b72"}]}