{"action":"created","issue":{"url":"https://api.github.com/repos/fpga-logi/logi-projects/issues/4","labels_url":"https://api.github.com/repos/fpga-logi/logi-projects/issues/4/labels{/name}","comments_url":"https://api.github.com/repos/fpga-logi/logi-projects/issues/4/comments","events_url":"https://api.github.com/repos/fpga-logi/logi-projects/issues/4/events","html_url":"https://github.com/fpga-logi/logi-projects/issues/4","id":54887203,"number":4,"title":"Stable, Dev and missing dependencies","user":{"login":"peepo","id":260305,"avatar_url":"https://avatars.githubusercontent.com/u/260305?v=3","gravatar_id":"","url":"https://api.github.com/users/peepo","html_url":"https://github.com/peepo","followers_url":"https://api.github.com/users/peepo/followers","following_url":"https://api.github.com/users/peepo/following{/other_user}","gists_url":"https://api.github.com/users/peepo/gists{/gist_id}","starred_url":"https://api.github.com/users/peepo/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/peepo/subscriptions","organizations_url":"https://api.github.com/users/peepo/orgs","repos_url":"https://api.github.com/users/peepo/repos","events_url":"https://api.github.com/users/peepo/events{/privacy}","received_events_url":"https://api.github.com/users/peepo/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":1,"created_at":"2015-01-20T14:13:27Z","updated_at":"2015-01-20T14:35:50Z","closed_at":null,"body":"Jonathan,\r\n\r\nplease accept my apologies if I have misconstrued how to build these projects.\r\nI'm only just starting and they are quite large, at least for me.... \r\nIt's a little difficult for me to give sufficient but not superfluous detail, please bear with me.\r\n\r\nI am happy to contribute to either fpga-logi or fpga-logi-dev, but both might fry my brains.\r\nplease advise...\r\n\r\nI am trying to synthesise logi_camera_test.xise,\r\nthough I may work through all the projects,\r\nbut camera & hardCV is my concern.\r\n\r\nusing fpga-logi-dev: \r\nlogi-hard is missing directory wishbone and contents, nb clock_gen is present vv\r\nsee: https://github.com/fpga-logi-dev/logi-hard\r\n\r\nusing  fpga-logi:\r\ndirectory logi-projects/logi-camera-test/hw/logipi/ise/ipcore_dir/clock_gen is missing\r\nsee: https://github.com/fpga-logi/logi-projects/tree/master/logi-camera-test/hw/logipi/ise/ipcore_dir\r\n\r\nplease advise what would be the most efficient approach.\r\n\r\nI am keen to minimise both confusion, and the number of pull requests.\r\n\r\nmany thanks once again,\r\n\r\n~:\"\r\n"},"comment":{"url":"https://api.github.com/repos/fpga-logi/logi-projects/issues/comments/70662189","html_url":"https://github.com/fpga-logi/logi-projects/issues/4#issuecomment-70662189","issue_url":"https://api.github.com/repos/fpga-logi/logi-projects/issues/4","id":70662189,"user":{"login":"jpiat","id":2315876,"avatar_url":"https://avatars.githubusercontent.com/u/2315876?v=3","gravatar_id":"","url":"https://api.github.com/users/jpiat","html_url":"https://github.com/jpiat","followers_url":"https://api.github.com/users/jpiat/followers","following_url":"https://api.github.com/users/jpiat/following{/other_user}","gists_url":"https://api.github.com/users/jpiat/gists{/gist_id}","starred_url":"https://api.github.com/users/jpiat/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jpiat/subscriptions","organizations_url":"https://api.github.com/users/jpiat/orgs","repos_url":"https://api.github.com/users/jpiat/repos","events_url":"https://api.github.com/users/jpiat/events{/privacy}","received_events_url":"https://api.github.com/users/jpiat/received_events","type":"User","site_admin":false},"created_at":"2015-01-20T14:35:49Z","updated_at":"2015-01-20T14:35:49Z","body":"I'll need to fix this project, the problem is that the clock_gen has to be\r\ngenerated locally. GIve me a day to do the fix.\r\n\r\n2015-01-20 15:13 GMT+01:00 Jonathan Chetwynd <notifications@github.com>:\r\n\r\n> Jonathan,\r\n>\r\n> please accept my apologies if I have misconstrued how to build these\r\n> projects.\r\n> I'm only just starting and they are quite large, at least for me....\r\n> It's a little difficult for me to give sufficient but not superfluous\r\n> detail, please bear with me.\r\n>\r\n> I am happy to contribute to either fpga-logi or fpga-logi-dev, but both\r\n> might fry my brains.\r\n> please advise...\r\n>\r\n> I am trying to synthesise logi_camera_test.xise,\r\n> though I may work through all the projects,\r\n> but camera & hardCV is my concern.\r\n>\r\n> using fpga-logi-dev:\r\n> logi-hard is missing directory wishbone and contents, nb clock_gen is\r\n> present vv\r\n> see: https://github.com/fpga-logi-dev/logi-hard\r\n>\r\n> using fpga-logi:\r\n> directory\r\n> logi-projects/logi-camera-test/hw/logipi/ise/ipcore_dir/clock_gen is missing\r\n> see:\r\n> https://github.com/fpga-logi/logi-projects/tree/master/logi-camera-test/hw/logipi/ise/ipcore_dir\r\n>\r\n> please advise what would be the most efficient approach.\r\n>\r\n> I am keen to minimise both confusion, and the number of pull requests.\r\n>\r\n> many thanks once again,\r\n>\r\n> ~:\"\r\n>\r\n> —\r\n> Reply to this email directly or view it on GitHub\r\n> <https://github.com/fpga-logi/logi-projects/issues/4>.\r\n>"}}