{"push_id":856077067,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"af4bb57907a86d46e9a02dd7c6fea7a4dbc0eacf","before":"99ee897f5441f6bc2d70ef24f92cd9c37269cd41","commits":[{"sha":"bf0ce512c5ecaff0631b0c12ff85b0d3e2b5de12","author":{"email":"788c14eeffa2067e120409a238fa186a04f20a10@amd.com","name":"Matt Arsenault"},"message":"AMDGPU: Hack for VS_32 register pressure\n\nFor some reason VS_32 ends up factoring into the pressure heuristics\neven though we should never see a virtual register with this class.\n\nWhen SGPRs are reserved for register spilling, this for some reason\ntriggers reg-crit scheduling.\n\nSetting isAllocatable = 0 may help with this since that seems to remove\nit from the default implementation's generated table.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252321 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/bf0ce512c5ecaff0631b0c12ff85b0d3e2b5de12"},{"sha":"af4bb57907a86d46e9a02dd7c6fea7a4dbc0eacf","author":{"email":"788c14eeffa2067e120409a238fa186a04f20a10@amd.com","name":"Matt Arsenault"},"message":"AMDGPU: Fix hardcoded alignment of spill.\n\nInstead of forcing 4 alignment when spilled, set register class\nalignments.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252322 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/af4bb57907a86d46e9a02dd7c6fea7a4dbc0eacf"}]}