{"push_id":575037214,"size":22,"distinct_size":22,"ref":"refs/heads/master","head":"cd2d5541271f1934345d8ca42f5fafff1744eee7","before":"449008f86418583a1f0fb946cf91ee7b4797317d","commits":[{"sha":"951c6300f74ace35d87c079affc57cfc513a6a35","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Move some opcode generation functions out of line\n\nSome of these functions are really quite large.  We have a number of\nthings that ought to be circularly dependent, but we duplicated code\nto break that chain for the inlines.\n\nThis saved 25% of the code size of one of the translators I examined.\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/951c6300f74ace35d87c079affc57cfc513a6a35"},{"sha":"3a13c3f34ce2058e0c2decc3b0f9f56be24c9400","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Reduce ifdefs in tcg-op.c\n\nAlmost completely eliminates the ifdefs in this file, improving\nconfidence in the lesser used 32-bit builds.\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/3a13c3f34ce2058e0c2decc3b0f9f56be24c9400"},{"sha":"0a7df5da986bd7ee0789f2d7b8611f2e8eee5046","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Move emit of INDEX_op_end into gen_tb_end\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/0a7df5da986bd7ee0789f2d7b8611f2e8eee5046"},{"sha":"fe700adb3db5b028b504423b946d4ee5200a8f2f","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Introduce tcg_op_buf_count and tcg_op_buf_full\n\nThe method by which we count the number of ops emitted\nis going to change.  Abstract that away into some inlines.\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/fe700adb3db5b028b504423b946d4ee5200a8f2f"},{"sha":"c45cb8bb89fc798489869982c4c463b26ce43d7b","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Put opcodes in a linked list\n\nThe previous setup required ops and args to be completely sequential,\nand was error prone when it came to both iteration and optimization.\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/c45cb8bb89fc798489869982c4c463b26ce43d7b"},{"sha":"0c627cdca20155753a536c51385abb73941a59a0","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Remove opcodes instead of noping them out\n\nWith the linked list scheme we need not leave nops in the stream\nthat we need to process later.\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/0c627cdca20155753a536c51385abb73941a59a0"},{"sha":"a4ce099a7a4b4734c372f6bf28f3362e370f23c1","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Implement insert_op_before\n\nRather reserving space in the op stream for optimization,\nlet the optimizer add ops as necessary.\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/a4ce099a7a4b4734c372f6bf28f3362e370f23c1"},{"sha":"15fc7daa770764cc795158cbb525569f156f3659","author":{"email":"aea4fd857e97ee7d33f60175ba9388a955b9d916@twiddle.net","name":"Richard Henderson"},"message":"tcg: Remove unused opcodes\n\nWe no longer need INDEX_op_end to terminate the list, nor do we\nneed 5 forms of nop, since we just remove the TCGOp instead.\n\nReviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/15fc7daa770764cc795158cbb525569f156f3659"},{"sha":"bf439db4993b02033d4fba8460ca4dc45b15071a","author":{"email":"3ad82b0c937b9aa51276120cedd545efc822be04@suse.de","name":"Alexander Graf"},"message":"pci: Allocate PCIe host bridge PCI ID\n\nWe are going to introduce a PCIe host controller that doesn't exist that\nway in real hardware, but still needs to expose some PCIe root device which\nhas PCI IDs.\n\nAllocate a PCI ID in the Red Hat space that we use for other devices of this\nkind.\n\nSigned-off-by: Alexander Graf <agraf@suse.de>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/bf439db4993b02033d4fba8460ca4dc45b15071a"},{"sha":"4d8fde1126419c5a858926a457a9b320a27a921a","author":{"email":"3ad82b0c937b9aa51276120cedd545efc822be04@suse.de","name":"Alexander Graf"},"message":"pci: Add generic PCIe host bridge\n\nWith simple exposure of MMFG, ioport window, mmio window and an IRQ line we\ncan successfully create a workable PCIe host bridge that can be mapped anywhere\nand only needs to get described to the OS using whatever means it likes.\n\nThis patch implements such a \"generic\" host bridge. It handles 4 legacy IRQ\nlines. MSIs need to be handled external to the host bridge.\n\nThis device is particularly useful for the \"pci-host-ecam-generic\" driver in\nLinux.\n\nSigned-off-by: Alexander Graf <agraf@suse.de>\nReviewed-by: Claudio Fontana <claudio.fontana@huawei.com>\nTested-by: Claudio Fontana <claudio.fontana@huawei.com>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/4d8fde1126419c5a858926a457a9b320a27a921a"},{"sha":"4ab29b8214cc4b54e0c1a8270b610a340311470e","author":{"email":"3ad82b0c937b9aa51276120cedd545efc822be04@suse.de","name":"Alexander Graf"},"message":"arm: Add PCIe host bridge in virt machine\n\nNow that we have a working \"generic\" PCIe host bridge driver, we can plug\nit into ARM's virt machine to always have PCIe available to normal ARM VMs.\n\nI've successfully managed to expose a Bochs VGA device, XHCI and an e1000\ninto an AArch64 VM with this and they all lived happily ever after.\n\nSigned-off-by: Alexander Graf <agraf@suse.de>\nTested-by: Claudio Fontana <claudio.fontana@huawei.com>\n[PMM: Squashed in fix for off-by-one error in bus-range DT property\n from Laszlo Ersek <lersek@redhat.com>]\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/4ab29b8214cc4b54e0c1a8270b610a340311470e"},{"sha":"332261de2b979610aacde22eb15ef6e59f3c2da9","author":{"email":"3ad82b0c937b9aa51276120cedd545efc822be04@suse.de","name":"Alexander Graf"},"message":"pci: Move PCI VGA to pci.mak\n\nEvery platform that supports PCI can also spawn the Bochs VGA PCI adapter. Move\nit to pci.mak to enable it for everyone.\n\nSigned-off-by: Alexander Graf <agraf@suse.de>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/332261de2b979610aacde22eb15ef6e59f3c2da9"},{"sha":"fb8d6c24b095c426151b9bba8c8b0e58b03d6503","author":{"email":"a006f1f12a27194501d281fc3cf5769062a45c6f@linaro.org","name":"Greg Bellows"},"message":"target-arm: Add CPU property to disable AArch64\n\nAdds registration and get/set functions for enabling/disabling the AArch64\nexecution state on AArch64 CPUs.  By default AArch64 execution state is enabled\non AArch64 CPUs, setting the property to off, will disable the execution state.\nThe below QEMU invocation would have AArch64 execution state disabled.\n\n    $ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off\n\nAlso adds stripping of features from CPU model string in acquiring the ARM CPU\nby name.\n\nSigned-off-by: Greg Bellows <greg.bellows@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1423736974-14254-2-git-send-email-greg.bellows@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/fb8d6c24b095c426151b9bba8c8b0e58b03d6503"},{"sha":"f313369fdb78f849ecbbd8e5d88f01ddf38786c8","author":{"email":"a006f1f12a27194501d281fc3cf5769062a45c6f@linaro.org","name":"Greg Bellows"},"message":"target-arm: Add feature parsing to virt\n\nAdded machvirt parsing of feature keywords added to the -cpu command line\noption.  Parsing occurs during machine initialization.\n\nSigned-off-by: Greg Bellows <greg.bellows@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1423736974-14254-3-git-send-email-greg.bellows@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/f313369fdb78f849ecbbd8e5d88f01ddf38786c8"},{"sha":"ce02049dbf1828b4bc77d921b108a9d84246e5aa","author":{"email":"a006f1f12a27194501d281fc3cf5769062a45c6f@linaro.org","name":"Greg Bellows"},"message":"target-arm: Add 32/64-bit register sync\n\nAdd AArch32 to AArch64 register sychronization functions.\nReplace manual register synchronization with new functions in\naarch64_cpu_do_interrupt() and HELPER(exception_return)().\n\nSigned-off-by: Greg Bellows <greg.bellows@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1423736974-14254-4-git-send-email-greg.bellows@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/ce02049dbf1828b4bc77d921b108a9d84246e5aa"},{"sha":"560739702764d4882662f0e70b584fa5dff7241a","author":{"email":"a006f1f12a27194501d281fc3cf5769062a45c6f@linaro.org","name":"Greg Bellows"},"message":"target-arm: Add AArch32 guest support to KVM64\n\nAdd 32-bit to/from 64-bit register synchronization on register gets and puts.\nSet EL1_32BIT feature flag passed to KVM\n\nSigned-off-by: Greg Bellows <greg.bellows@linaro.org>\nMessage-id: 1423736974-14254-5-git-send-email-greg.bellows@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/560739702764d4882662f0e70b584fa5dff7241a"},{"sha":"1743d55c8b38bcee632cf6eb2de81131635bb3d2","author":{"email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org","name":"Peter Maydell"},"message":"target-arm: A64: Fix shifts into sign bit\n\nFix attempts to shift into the sign bit of an int, which is undefined\nbehaviour in C and warned about by the clang sanitizer.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1423233250-15853-2-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/1743d55c8b38bcee632cf6eb2de81131635bb3d2"},{"sha":"e167adc9d9f5df4f8109aecd4552c407fdce094a","author":{"email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org","name":"Peter Maydell"},"message":"target-arm: A64: Fix handling of rotate in logic_imm_decode_wmask\n\nThe code in logic_imm_decode_wmask attempts to rotate a mask\nvalue within the bottom 'e' bits of the value with\n    mask = (mask >> r) | (mask << (e - r));\nThis has two issues:\n * if the element size is 64 then a rotate by zero results\n   in a shift left by 64, which is undefined behaviour\n * if the element size is smaller than 64 then this will\n   leave junk in the value at bit 'e' and above, which is\n   not valid input to bitfield_replicate(). As it happens,\n   the bits at bit 'e' to '2e - r' are exactly the ones\n   which bitfield_replicate is going to copy in there,\n   so this isn't a \"wrong code generated\" bug, but it's\n   confusing and if we ever put an assert in\n   bitfield_replicate it would fire on valid guest code.\n\nFix the former by not doing anything if r is zero, and\nthe latter by masking with bitmask64(e).\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1423233250-15853-3-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/e167adc9d9f5df4f8109aecd4552c407fdce094a"},{"sha":"037e1d009e2fcb80784d37f0e12aa999787d46d4","author":{"email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org","name":"Peter Maydell"},"message":"target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addr\n\nShifting a negative integer left is undefined behaviour in C.\nAvoid it by assembling and shifting the offset fields as\nunsigned values and then sign extending as the final action.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1423233250-15853-4-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/037e1d009e2fcb80784d37f0e12aa999787d46d4"},{"sha":"c2ebd862a54b7e12175d65c03ba259926cb2237a","author":{"email":"313afa09ce093b19ae1dd74f57c1ebd94508584c@linaro.org","name":"Peter Maydell"},"message":"target-arm: A64: Avoid signed shifts in disas_ldst_pair()\n\nAvoid shifting potentially negative signed offset values in\ndisas_ldst_pair() by keeping the offset in a uint64_t rather\nthan an int64_t.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-id: 1423233250-15853-5-git-send-email-peter.maydell@linaro.org","distinct":true,"url":"https://api.github.com/repos/J-Liu/qemu/commits/c2ebd862a54b7e12175d65c03ba259926cb2237a"}]}