{"push_id":810713601,"size":7,"distinct_size":7,"ref":"refs/heads/master","head":"ccf4f6c3d7616c546d78eb21d22ebda812b5e2bb","before":"c05d268cfabbe26d032d73abcea6dc921c49e549","commits":[{"sha":"52d521e4337995d417b6f7b68644959edcc0c6b4","author":{"email":"d29e28ee198f946bb48a393ea01442bceee58118@arm.com","name":"Mitch Hayenga"},"message":"cpu: Change thread assignments for heterogenous SMT\n\nTrying to run an SE system with varying threads per core (SMT cores + Non-SMT\ncores) caused failures due to the CPU id assignment logic.  The comment\nabout thread assignment (worrying about core 0 not having tid 0) seems\nnot to be valid given that our configuration scripts initialize them in\norder.\n\nThis removes that constraint so a heterogenously threaded sytem can work.","distinct":true,"url":"https://api.github.com/repos/gem5/gem5/commits/52d521e4337995d417b6f7b68644959edcc0c6b4"},{"sha":"582a0148b441fe9f4a6f977094c5ce6bf7ab6313","author":{"email":"d29e28ee198f946bb48a393ea01442bceee58118@arm.com","name":"Mitch Hayenga"},"message":"config,cpu: Add SMT support to Atomic and Timing CPUs\n\nAdds SMT support to the \"simple\" CPU models so that they can be\nused with other SMT-supported CPUs. Example usage: this enables\nthe TimingSimpleCPU to be used to warmup caches before swapping to\ndetailed mode with the in-order or out-of-order based CPU models.","distinct":true,"url":"https://api.github.com/repos/gem5/gem5/commits/582a0148b441fe9f4a6f977094c5ce6bf7ab6313"},{"sha":"fafa83ed32933fe250d34dfca23fba348429b176","author":{"email":"d29e28ee198f946bb48a393ea01442bceee58118@arm.com","name":"Mitch Hayenga"},"message":"cpu: Add per-thread monitors\n\nAdds per-thread address monitors to support FullSystem SMT.","distinct":true,"url":"https://api.github.com/repos/gem5/gem5/commits/fafa83ed32933fe250d34dfca23fba348429b176"},{"sha":"e255fa053f8d105de8d188077a318124a3aad9ce","author":{"email":"d29e28ee198f946bb48a393ea01442bceee58118@arm.com","name":"Mitch Hayenga"},"message":"arm: SMT MPIDR Setting\n\nChanges assignment of the MPIDR for multi-threaded systems only.","distinct":true,"url":"https://api.github.com/repos/gem5/gem5/commits/e255fa053f8d105de8d188077a318124a3aad9ce"},{"sha":"a5c4eb3de9deb3a71a6a5230a25ff5962e584980","author":{"email":"d29e28ee198f946bb48a393ea01442bceee58118@arm.com","name":"Mitch Hayenga"},"message":"isa,cpu: Add support for FS SMT Interrupts\n\nAdds per-thread interrupt controllers and thread/context logic\nso that interrupts properly get routed in SMT systems.","distinct":true,"url":"https://api.github.com/repos/gem5/gem5/commits/a5c4eb3de9deb3a71a6a5230a25ff5962e584980"},{"sha":"9e07a7504c94973e7837d1d3e96dbdb8d95cfad3","author":{"email":"d29e28ee198f946bb48a393ea01442bceee58118@arm.com","name":"Mitch Hayenga"},"message":"cpu,isa,mem: Add per-thread wakeup logic\n\nChanges wakeup functionality so that only specific threads on SMT\ncapable cpus are woken.","distinct":true,"url":"https://api.github.com/repos/gem5/gem5/commits/9e07a7504c94973e7837d1d3e96dbdb8d95cfad3"},{"sha":"ccf4f6c3d7616c546d78eb21d22ebda812b5e2bb","author":{"email":"d29e28ee198f946bb48a393ea01442bceee58118@arm.com","name":"Mitch Hayenga"},"message":"arm: Change TLB Software Caching\n\nIn ARM, certain variables are only updated when a necessary change is\ndetected.  Having 2 SMT threads share a TLB resulted in these not being\nupdated as required.  This patch adds a thread context identifer to\nassist in the invalidation of these variables.","distinct":true,"url":"https://api.github.com/repos/gem5/gem5/commits/ccf4f6c3d7616c546d78eb21d22ebda812b5e2bb"}]}