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MK60DN512VLL10\n\nThe port should with a high probability also support the following variations of the above CPUs (untested):\n\n - MK60DN256VLL10\n\nAnd possibly also:\n\n - MK60DX256VLL10\n - MK60DX512VLL10\n - MK60DN512VLQ10\n - MK60DN256VLQ10\n - MK60DX256VLQ10\n - MK60DN512VMC10\n - MK60DN256VMC10\n - MK60DX256VMC10\n - MK60DN512VMD10\n - MK60DX256VMD10\n - MK60DN256VMD10\n\nCurrently not working on the following CPUs (Missing PIT channel\nchaining necessary for kinetis_common/periph/timer implementation):\n\n - MK60DN256ZVLL10\n - MK60DN512ZVLL10\n - MK60DX256ZVLL10\n - MK60DX512ZVLL10\n - MK60DN512ZVLQ10\n - MK60DN256ZVLQ10\n - MK60DX256ZVLQ10\n - MK60DN512ZVMC10\n - MK60DN256ZVMC10\n - MK60DX256ZVMC10\n - MK60DN512ZVMD10\n - MK60DX256ZVMD10\n - MK60DN256ZVMD10\n\nRegarding header files from Freescale:\n\n   dist/tools/licenses: Add Freescale CMSIS PAL license pattern\n\nRedistribution is OK according to:\n\nhttps://community.freescale.com/message/477976?et=watches.email.thread#477976\n\nArchive copy in case the above link disappears:\n\nhttps://web.archive.org/web/20150328073057/https://community.freescale.com/message/477976?et=watches.email.thread\n\nApplies to:\n - MK60DZ10.h (K60 variant)","distinct":false,"url":"https://api.github.com/repos/gebart/RIOT/commits/de486ff79f618e2d6aa760e9d9103b75e668b3d3"},{"sha":"4ae819c011228f1b84bbafef50b0f3f6005dc445","author":{"email":"d097f2c6c8fee73e3ea75e1d62412e3886346faa@eistec.se","name":"Joakim Gebart"},"message":"mulle: Initial import of Eistec Mulle board.\n\nInitially supports only Mulles with serial number > 220 (due to missing\nMK60DN256ZVLL10 support in k60).\n\nSee also: https://github.com/RIOT-OS/RIOT/wiki/Board%3A-Mulle\n\nSigned-off-by: Joakim Gebart <joakim.gebart@eistec.se>","distinct":false,"url":"https://api.github.com/repos/gebart/RIOT/commits/4ae819c011228f1b84bbafef50b0f3f6005dc445"}]}